Test and diagnosis of analogue, mixed signal and rf integrated circuits the system on chip approach

Tai Lieu Chat Luong Test and Diagnosis of Analogue, Mixed-signal and RF Integrated Circuits The system on chip approach Edited by Yichuang Sun The Institution of Engineering and Technology Published by The Institution of Engineering and Technology, London, United Kingdom © 2008 The Institution of Engineering and Technology First published 2008 This publication is copyright under the Berne Convention and the Universal Copyright Convention All rights reserved Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act, 1988, this publication may be reproduced, stored or transmitted, in any form or by any means, only with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms of licences issued by the Copyright Licensing Agency Inquiries concerning reproduction outside those terms should be sent to the publishers at the undermentioned address: The Institution of Engineering and Technology Michael Faraday House Six Hills Way, Stevenage Herts, SG1 2AY, United Kingdom www.theiet.org While the authors and the publishers believe that the information and guidance given in this work are correct, all parties must rely upon their own skill and judgement when making use of them Neither the authors nor the publishers assume any liability to anyone for any loss or damage caused by any error or omission in the work, whether such error or omission is the result of negligence or any other cause Any and all such liability is disclaimed The moral rights of the authors to be identified as authors of this work have been asserted by him in accordance with the Copyright, Designs and Patents Act 1988 British Library Cataloguing in Publication Data Test and diagnosis of analogue, mixed-signal and RF integrated circuits : the system on chip approach – (Circuits, devices & systems ; v 19) Linear integrated circuits – Testing Mixed signal circuits – Testing Radio frequency integrated circuits – Testing I Sun, Yichuang II Institution of Engineering and Technology 621.3’815’0287 ISBN 978-0-86341-745-0 Typeset in India by Newgen Imaging Systems (P) Ltd, Chennai Printed in the UK by Athenaeum Press Ltd, Gateshead, Tyne & Wear Preface System on chip (SoC) integrated circuits (ICs) for communications, multimedia and computer applications are receiving considerable international attention One example of a SoC is a single-chip transceiver Modern microelectronic design processes adopt a mixed-signal approach since a SoC is a mixed-signal system that includes both analogue and digital circuits There are several IC technologies currently available, however, the low-cost and readily available CMOS technique is the mainstream technology used in IC production for applications such as computer hard disk drive systems, sensors and sensing systems for health care, video, image and display systems and cable modems for wired communications, radio frequency (RF) transceivers for wireless communications and high-speed transceivers for optical communications Currently, microelectronic circuits and systems are mainly based on submicron and deep-submicron CMOS technologies, although nano-CMOS technology has already been used in computer, communication and multimedia chip design While still pushing the limits of CMOS, preparation for the post-CMOS era is well under way with many other potential alternatives being actively pursued There is an increasing interest in the testing of SoC devices as automatic testing becomes crucially important to drive down the overall cost of SoC devices due to the imperfect nature of the manufacturing process and its associated tolerances Traditional external test has become more and more irrelevant for SoC devices, because these devices have a very limited number of test nodes Design for testability (DfT) and built-in self-test (BIST) approaches have thus been the choice for many applications The concept of on chip test systems including test generation, measurement and processing has also been proposed for complex integrated systems Test and fault diagnosis of analogue and mixed-signal circuits, however, is much more difficult than that of digital circuits due to tolerances, parasitics and non-linearities, and thus it remains a bottleneck for automatic SoC test Recently, the closely related tuning, calibration and correction issues of analogue, mixed-signal and RF circuits have been intensively studied However, the papers on testing, diagnosis and tuning have been published in a diverse range of journals and conferences, and thus they have been treated quite separately by the associated communities For example, work on tuning has been mainly published in journals and conferences concerned with circuit design and has not therefore come to the attention of the testing community Similarly, analogue fault xvi Test and diagnosis of analogue, mixed-signal and RF integrated circuits diagnosis was mainly investigated by circuit theorists in the past, although it has now become a serious topic in the testing community The scope of this book is to consider the whole range of automatic testing, diagnosis and tuning of analogue, mixed-signal and RF ICs and systems It aims to provide a comprehensive treatment of testing, diagnosis and tuning in a coherent way and to report systematically the most recent developments in all these areas in a single source for the first time The book attempts to provide a balanced view of the three important topics, however, stress has been put on the testing side Motivated by recent SoC test concepts, the diagnosis, testing and tuning issues of analogue, mixed-signal and RF circuits are addressed, in particular, from the SoC perspective, which forms another unique feature of this book The book contains 11 chapters written by leading international researchers in the subject areas It covers three theme topics: diagnosis, testing and tuning The first four chapters are concerned with fault diagnosis of analogue circuits Chapter systematically presents various circuit-theory-based diagnosis methodologies for both linear and non-linear circuits including some material not previously available in the public domain This chapter also serves as an overview of fault diagnosis The following three chapters cover the three most popular diagnosis approaches; the symbolic function, neural network and hierarchical decomposition techniques, respectively Then testing of analogue, mixed-signal and RF ICs is discussed extensively in Chapters 5-10 Chapter gives a general review of all aspects of testing with emphasis on DfT and BIST Chapters 6–10 focus in depth on recent advances in testing analogue filters, data converters, sigma-delta modulators, phase-locked loops, RF transceivers and components, respectively Finally, Chapter 11 discusses auto-tuning and calibration of analogue, mixed-signal and RF circuits including continuous-time filters, voltage-controlled oscillators and phase-locked loops synthesizers, impedance matching networks and antenna tuning units The book can be used as a text or reference for a broad range of readers from both academia and industry It is especially useful for those who wish to gain a viewpoint from which to understand the relationship of diagnosis, testing and tuning An indispensible reference companion to researchers and engineers in electronic and electrical engineering, the book is also intended to be a text for graduate and senior undergraduate students, as may be appropriate I would like to thank staff members in the Publishing Department of the IET for their support and assistance, especially the former Commissioning Editors Sarah Kramer and Nick Canty and the current Commissioning Editor, Lisa Reading I am very grateful to the chapter authors for their considerable efforts in contributing these high-quality chapters; their professionalism is highly appreciated I must also thank my wife Xiaohui, son Bo and daughter Lucy for their understanding and support; without them behind me this book would not have been possible As a final note, it has been my long dream to write or edit something in the topic area of this book The first research paper published in my academic career was about fault diagnosis in analogue circuits This was over 20 years ago when I studied for the MSc degree The real motivation for doing this book, however, came along with the proposal for a special issue on analogue and mixed-signal test for SoCs for IEE Preface xvii Proceedings: Circuits, Devices and Systems (published in 2004) It has since been a long journey for the book to come into being as you see now, however, the book has indeed been significantly improved with the time during the editorial process I sincerely hope that the efforts from the editor and authors pay off as a truly useful and long-lasting companion in your successful career Yichuang Sun Contents Preface List of contributors Fault diagnosis of linear and non-linear analogue circuits Yichuang Sun 1.1 1.2 1.3 1.4 1.5 Introduction Multiple-fault diagnosis of linear circuits 1.2.1 Fault incremental circuit 1.2.2 Branch-fault diagnosis 1.2.3 Testability analysis and design for testability 1.2.4 Bilinear function and multiple excitation method 1.2.5 Node-fault diagnosis 1.2.6 Parameter identification after k-node fault location 1.2.7 Cutset-fault diagnosis 1.2.8 Tolerance effects and treatment Class-fault diagnosis of analogue circuits 1.3.1 Class-fault diagnosis and general algebraic method for classification 1.3.2 Class-fault diagnosis and topological technique for classification 1.3.3 t-class-fault diagnosis and topological method for classification Fault diagnosis of non-linear circuits 1.4.1 Fault modelling and fault incremental circuits 1.4.2 Fault location and identification 1.4.3 Alternative fault incremental circuits and fault diagnosis Recent advances in fault diagnosis of analogue circuits 1.5.1 Test node selection and test signal generation xv xix 1 3 10 12 15 15 16 18 19 21 21 24 26 29 29 viii Test and diagnosis of analogue, mixed-signal and RF integrated circuits 1.5.2 1.5.3 1.5.4 1.6 1.7 Summary References 30 31 31 32 33 Symbolic function approaches for analogue fault diagnosis Stefano Manetti and Maria Cristina Piccirilli 37 2.1 2.2 37 39 40 40 41 42 47 52 57 57 2.3 2.4 2.5 2.6 2.7 Symbolic approach for fault diagnosis of analogue circuits Neural-network- and wavelet-based methods for analogue fault diagnosis Hierarchical approach for large-scale circuit fault diagnosis Introduction Symbolic analysis 2.2.1 Symbolic analysis techniques 2.2.2 The SAPWIN program Testability and ambiguity groups 2.3.1 Algorithms for testability evaluation 2.3.2 Ambiguity groups 2.3.3 Singular-value decomposition approach 2.3.4 Testability analysis of non-linear circuits Fault diagnosis of linear analogue circuits 2.4.1 Techniques based on bilinear decomposition of fault equations 2.4.2 Newton–Raphson-based approach 2.4.3 Selection of the test frequencies Fault diagnosis of non-linear circuits 2.5.1 PWL models 2.5.2 Transient analysis models for reactive components 2.5.3 The Katznelson-type algorithm 2.5.4 Circuit fault diagnosis application 2.5.5 The SAPDEC program Conclusions References Neural-network-based approaches for analogue circuit fault diagnosis Yichuang Sun and Yigang He 3.1 3.2 Introduction Fault diagnosis of analogue circuits with tolerances using artificial neural networks 3.2.1 Artificial neural networks 3.2.2 Fault diagnosis of analogue circuits 3.2.3 Fault diagnosis using ANNs 59 62 67 71 72 73 73 74 75 77 77 83 83 84 85 87 88 List of contents 3.2.4 3.3 3.4 3.5 3.6 Hierarchical/decomposition techniques for large-scale analogue diagnosis Peter Shepherd 4.1 4.2 4.3 4.4 4.5 Neural-network approach for fault diagnosis of large-scale analogue circuits 3.2.5 Illustrative examples Wavelet-based neural-network technique for fault diagnosis of analogue circuits with noise 3.3.1 Wavelet decomposition 3.3.2 Wavelet feature extraction of noisy signals 3.3.3 WNNs 3.3.4 WNN algorithm for fault diagnosis 3.3.5 Example circuits and results Neural-network-based L1 -norm optimization approach for fault diagnosis of non-linear circuits 3.4.1 L1 -norm optimization approach for fault location of non-linear circuits 3.4.2 NNs applied to L1 -norm fault diagnosis of non-linear circuits 3.4.3 Illustrative example Summary References ix Introduction 4.1.1 Diagnosis definitions Background to analogue fault diagnosis 4.2.1 Simulation before test 4.2.2 Simulation after test Hierarchical techniques 4.3.1 Simulation after test 4.3.2 Simulation before test 4.3.3 Mixed SBT/SAT approaches Conclusions References 90 90 94 94 95 96 97 98 100 103 105 109 110 111 113 113 114 115 115 116 121 121 131 135 137 138 DFT and BIST techniques for analogue and mixed-signal test Mona Safi-Harb and Gordon Roberts 141 5.1 5.2 5.3 141 142 146 146 147 148 Introduction Background Signal generation 5.3.1 Direct digital frequency synthesis 5.3.2 Oscillator-based approaches 5.3.3 Memory-based signal generation x Test and diagnosis of analogue, mixed-signal and RF integrated circuits 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.3.4 Multi-tones 5.3.5 Area overhead Signal capture Timing measurements and jitter analysers 5.5.1 Single counter 5.5.2 Analogue-based interpolation techniques: time-to-voltage converter 5.5.3 Digital phase-initerpolation techniques: delay line 5.5.4 Vernier delay line 5.5.5 Component-invariant VDL for jitter measurement 5.5.6 Analogue-based jitter measurement device 5.5.7 Time amplification 5.5.8 PLL and DLL – injection methods for PLL tests Calibration techniques for TMU and TDC Complete on-chip test core: proposed architecture in Reference 11 and its versatile applications 5.7.1 Attractive and flexible architecture 5.7.2 Oscilloscope/curve tracing 5.7.3 Coherent sampling 5.7.4 Time domain reflectometry/transmission 5.7.5 Crosstalk 5.7.6 Supply/substrate noise 5.7.7 RF testing – amplifier resonance 5.7.8 Limitations of the proposed architecture in Reference 11 Recent trends Conclusions References 149 150 151 154 154 155 156 157 159 160 162 163 164 166 166 168 169 169 169 170 171 172 172 173 174 Design-for-testability of analogue filters Yichuang Sun and Masood-ul Hasan 179 6.1 6.2 179 181 181 186 188 188 189 190 192 193 196 199 6.3 6.4 Introduction DfT by bypassing 6.2.1 Bypassing by bandwidth broadening 6.2.2 Bypassing using duplicated/switched opamp DfT by multiplexing 6.3.1 Tow-Thomas biquad filter 6.3.2 The Kerwin–Huelsman–Newcomb biquad filter 6.3.3 Second-order OTA-C filter OBT of analogue filters 6.4.1 Test transformations of active-RC filters 6.4.2 OBT of OTA-C filters 6.4.3 OBT of SC biquadratic filter Index Terms Links fractional-N synthesizer 365 frequency domain approach 30 frequency-response characterization system (FRCS) 311 BIST implementation 314 experimental evaluation 319 operating principle 311 testing methodology 313 frequency synthesizers, self-calibration 365 G genetic algorithms 30 global ambiguity groups 49 52 H HABIST™ 229 hierarchical techniques 121 extensions using the self-test algorithm large-scale circuit fault diagnosis 121 31 mixed SBT/SAT approaches 135 neural-network-based approaches 130 Newton–Raphson-based approach 136 simulation-after-test (SAT) 121 simulation-before-test (SBT) 129 symbolic analysis 124 131 This page has been reformatted by Knovel to provide easier navigation Index Terms Links I IFA (inductive fault analysis) 115 impedance matching, on-chip antennas 371 impedance sensors 376 matching network 373 tuning algorithms 377 incremental sensitivity analysis 30 inductive fault analysis (IFA) 115 intellectual properties (IPs) 144 interpolation-based time-to-digital converter (TDC) IPs (intellectual properties) 155 144 J jitter measurement analogue-based device 160 phase-locked loops (PLLs) 164 283 295 306 Vernier delay line 158 Katznelson-type algorithm 73 159 K k-branch-fault diagnosis method bilinear function design for testability multiple excitation method testability analysis This page has been reformatted by Knovel to provide easier navigation 298 Index Terms k-cutset-fault diagnosis Links 12 branch-fault diagnosis equations 14 loop- and mesh-fault diagnosis 14 tree selection 14 Kerwin–Huelsman–Newcomb (KHN) biquad filter multiplexing technique 189 oscillation-based test (OBT) 198 state-variable filter oscillation-based test (OBT) k-fault diagnosis methods class-fault diagnosis fault incremental circuit 193 15 non-linear circuits 22 recent advances 29 relation of branch-, node- and cutset-fault diagnosis 14 test node selection 29 tolerance effects and treatment 15 see also k-branch-fault diagnosis method; k-cutset-fault diagnosis; k-node-fault diagnosis KHN: see Kerwin–Huelsman–Newcomb (KHN) k-node-fault diagnosis parameter identification 10 This page has been reformatted by Knovel to provide easier navigation Index Terms Links L L1-norm optimization approach 84 illustrative example 109 neural network application 105 100 ladder-based filters multiplexing technique 205 tuning 361 large-scale circuit fault diagnosis background hierarchical techniques 113 31 121 mixed SBT/SAT approaches 135 simulation-after-test (SAT) 121 simulation-before-test (SBT) 129 131 90 92 neural-network-based approach leapfrog (LF) filters, tuning 360 linear programming neural networks (LPNN) 105 loop- and mesh-fault diagnosis 14 M MADBIST (mixed-analogue-digital BIST) 144 manufacturable-by construction design 173 MARS (multi-variate adaptive regression splines) 136 memory-based signal generation 148 mixed-analogue-digital BIST (MADBIST) 144 MLF: see multiple loop feedback (MLF) filters modified nodal analysis (MNA) 124 MOSFET-C filters 180 This page has been reformatted by Knovel to provide easier navigation Index Terms Links multiple-fault diagnosis: see k-fault diagnosis methods multiple loop feedback (MLF) filters bypassing method 203 multiplexing technique 205 tuning 360 multiplexing technique 188 203 multi-tone signal generation 149 256 multi-variate adaptive regression splines (MARS) mutual exclusive (MUTEX) circuit 136 162 N neural-network-based approaches 31 artificial neural networks 84 L1-norm optimization 84 wavelet neural networks 94 Newton–Raphson-based approach 62 83 130 105 136 node-fault diagnosis: see k -node-fault diagnosis noise effects analogue-to-digital (A/D) converters 219 sigma-delta (Σ) converters 236 supply/substrate noise 170 wavelet-based neural-network technique 247 94 non-linear circuits bilinear function for k-fault parameter identification 25 fault incremental circuits 21 fault location and identification 24 26 This page has been reformatted by Knovel to provide easier navigation Index Terms Links non-linear circuits (Cont.) fault modelling 21 26 L1-norm optimization approach 84 100 mixed-fault incremental circuit 26 quasi-fault incremental circuit 26 symbolic function approach 71 piecewise linear (PWL) models 72 SAPDEC application 74 transient analysis models for reactive components 73 testability analysis 57 two-step diagnosis methods 28 non-linear constrained optimization 106 non-linear regression models 136 O OBT (oscillation-based test) 192 207 on-chip testing: see built-in self test (BIST) open architecture optimization-based identification technique oscillation-based test (OBT) 173 192 207 OTA-C filters multiplexing technique 190 oscillation-based test (OBT) 196 tuning 349 207 This page has been reformatted by Knovel to provide easier navigation Index Terms Links P parallel testing parametric fault diagnosis 141 145 37 59 admittance-function-based parameter identification 87 bilinear decomposition of fault equations 59 bilinear function 25 k-node-fault diagnosis 10 Newton–Raphson-based approach 62 non-linear circuits 84 phase-locked loops (PLLs) test frequency selection 287 67 see also L1-norm optimization approach; symbolic function approach phase frequency detectors 279 306 phase-locked loops (PLLs) 163 277 architecture 277 capture and lock range measurements 303 charge pump and loop filter configuration 280 charge pump current measurement 295 digital structures 282 fault models 283 frequency lock test (FLT) 288 frequency synthesizers, calibration 365 gain and linearity measurement 297 302 jitter measurement 283 295 298 This page has been reformatted by Knovel to provide easier navigation 306 Index Terms Links phase-locked loops (PLLs) (Cont.) lock range and capture range measurement on-chip filter frequency tuning 288 356 operational-parameter-based measurements 287 operation and test issues 277 phase frequency detector 279 306 phase transfer function monitoring 292 303 production focussed tests 298 step response test 290 structural decomposition tests 295 test issues 277 test parameters 282 transient response monitoring 288 voltage controlled oscillator (VCO) 281 297 30 71 30 71 236 247 piecewise linear (PWL) models PLL: see phase-locked loops (PLLs) PWL (piecewise linear) models Q quantization noise quasi-fault incremental circuit 26 R radio frequency (RF): see RF testing RC filters: see active-RC filters reactive components, transient analysis models 73 This page has been reformatted by Knovel to provide easier navigation Index Terms Links RF amplitude detectors (RFD) 324 RF testing 149 RF wireless transceivers 309 amplitude detector method 324 frequency-response characterization 311 BIST implementation 314 experimental evaluation 319 operating principle 311 testing methodology 313 gain and compression point measurement 327 sequence of testing 310 simulation results 339 switched loop-back architecture 333 testing strategy 337 171 S Sallen-Key band-pass filter oscillation-based test (OBT) 195 parametric fault diagnosis 64 testability analysis 50 wavelet-based neural-network technique 98 sampled data switched-capacitor (SC) filters: see SC filters sampling-offset TDC (SOTDC) 165 SAPDEC (Symbolic Analysis Program for Diagnosis of Electronic Circuits) SAPWIN 72 74 40 46 55 SAT: see simulation-after-test (SAT) SBF: see simulation-before-test (SBT) This page has been reformatted by Knovel to provide easier navigation 56 Index Terms Links SC filters bypassing method bypassing by bandwidth broadening 183 bypassing using duplicated/switched opamp oscillation-based test (OBT) self-test (ST) algorithm hierarchical/decomposition techniques 187 199 116 121 see also built-in self test (BIST) sensitivity analysis 30 120 hierarchical techniques 124 127 ‘sequence of expressions’ (SOE) 124 128 sigma-delta (Σ) converters 235 architecture 239 behavioural model 264 built-in self test (BIST) 255 defect-oriented testing 258 design for testability (DfT) 261 digital filtering and decimation 238 262 dynamic performance parameters 246 first-order modulators 240 241 functional testing 254 256 high-order modulators 241 histogram testing 246 model-based testing 259 performance characterization 243 polynomial model 262 principle of operation 236 quantization noise 247 This page has been reformatted by Knovel to provide easier navigation Index Terms Links sigma-delta (Σ) converters (Cont.) servo-loop method 246 spectral analysis technique 248 static performance parameters 244 signal capture 151 analogue-to-digital (A/D) converters 221 complete on-chip test core 168 digitization 151 153 undersampling 152 154 143 146 signal generation area overhead 150 complete on-chip test core 168 direct digital frequency synthesis (DDFS) 146 memory-based 148 multi-tones 149 oscillator-based approaches 147 simulation-after-test (SAT) 37 hierarchical techniques 121 self-test (ST) algorithm 116 121 30 120 37 58 sensitivity analysis 59 116 see also fault verification method; parametric fault diagnosis; symbolic analysis simulation-before-test (SBT) symbolic function approach 115 129 see also fault dictionary method singular-value decomposition (SVD) approach 52 SoC: see systems on chip (SoCs) SOTDC (sampling-offset TDC) 165 This page has been reformatted by Knovel to provide easier navigation Index Terms Links spectral analysis technique, sigma-delta (Σ) converters 248 standardized test platforms 173 statistical process control 172 structural test: see built-in self test (BIST) successive approximation register (SAR) 151 switched-capacitor (SC) filters: see SC filters switched opamp techniques symbolic analysis hierarchical techniques 186 202 30 39 124 Symbolic Analysis Program for Diagnosis of Electronic Circuits (SAPDEC) 72 74 (SYFAD) 46 50 symbolic function approach 31 SYmbolic FAult Diagnosis bilinear decomposition of fault equations 59 non-linear circuits 57 71 piecewise linear (PWL) models 72 parametric fault diagnosis Newton–Raphson-based approach 62 test frequency selection 67 symbolic analysis 30 testability analysis 44 ambiguity groups 47 non-linear circuits 57 singular-value decomposition (SVD) 52 39 124 transient analysis models for reactive components 73 This page has been reformatted by Knovel to provide easier navigation Index Terms Links systems on chip (SoCs) 141 144 347 157 164 T TAGA (Testability and Ambiguity Group Analysis) TDC (time-to-digital converter) 55 155 TDR/TDT (time domain reflectometry/transmission) 169 TEI (test error index) 68 testability analysis 41 ambiguity groups 42 evaluation algorithms 42 k-fault diagnosis methods 47 numerical approach 43 symbolic approach 44 ambiguity groups 47 non-linear circuits 57 singular-value decomposition (SVD) 52 Testability and Ambiguity Group Analysis (TAGA) testable groups 55 49 test control 172 test costs 141 test error index (TEI) 68 test node selection 28 test points 41 test signal generation 29 time amplification time domain approach 52 46 162 30 This page has been reformatted by Knovel to provide easier navigation Index Terms Links time domain reflectometry/transmission (TDR/TDT) 169 time measurement unit (TMU) 156 164 time-to-digital converter (TDC) 155 157 time-to-voltage converter 155 timing measurements 154 time shuffling: see equivalent time sampling analogue-based interpolation techniques 155 calibration techniques 164 digital phase-interpolation techniques 156 jitter measurement 159 single counter 154 time amplification 162 Vernier delay line 157 TMU (time measurement unit) 156 164 tolerance effects and treatment 15 31 164 115 see also sensitivity analysis topological methods class-fault diagnosis 18 symbolic analysis 40 Tow-Thomas (TT) band-pass filter 56 biquad filter multiplexing technique 188 190 oscillation-based test (OBT) 194 197 transient analysis models, reactive components 73 TT: see Tow-Thomas (TT) two-integrator loop biquad filter 196 201 This page has been reformatted by Knovel to provide easier navigation 347 Index Terms Links two-stage common emitter (CE) audio amplifier 69 U undersampling 152 154 V Vernier delay line 157 voltage controlled oscillator (VCO) gain and linearity measurement 297 phase-locked loops (PLLs) 281 365 31 83 W wavelet-based neural-network technique algorithm for fault diagnosis 97 example circuits and results 98 feature extraction of noisy signals 95 four opamp biquad high-pass filter 99 wavelet decomposition 94 wavelet neural networks 96 wavelet packet decomposition 94 30 wireless transceivers: see RF wireless transceivers This page has been reformatted by Knovel to provide easier navigation