Boca Raton London New York Singapore A CRC title, part of the Taylor & Francis imprint, a member of the Taylor & Francis Group, the academic division of T&F Informa plc. SILICON NANOELECTRONICS Edited by Shunri Oda • David Ferry Copyright © 2006 Taylor & Francis Group, LLC Published in 2006 by CRC Press Taylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300 Boca Raton, FL 33487-2742 ©2006 by Taylor &Francis Group, LLC CRC Press is an imprint of Taylor &Francis Group No claim to original U.S. Government works Printed in the United States of America on acid-free paper 10 9 8 7 6 5 4 3 2 1 International Standard Book Number-10: 0-8247-2633-2 (Hardcover) International Standard Book Number-13: 978-0-8247-2633-1 (Hardcover) Library of Congress Card Number 2005005007 This book contains information obtained from authenticand highly regarded sources. Reprinted material is quoted with permission, and sources are indicated. Awide variety of references are listed. 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Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identification and explanation without intent to infringe. Library of Congress Cataloging-in-Publication Data Silicon nanoelectronics / edited by Shunri Oda and David Ferry. p. cm. ISBN 0-8247-2633-2 1. Molecular electronics. [DNLM: 1. Nanotechnology. 2. Silicon Compounds. ] I. Oda, Shunri. II. Ferry, David K. TK7874.8.S55 2005 621.381 dc22 2005005007 Visit the Taylor & Francis Web site at http://www.taylorandfrancis.com and the CRC Press Web site at http://www.crcpress.com Taylor & Francis Group is the Academic Division of T&F Informa plc. Copyright © 2006 Taylor & Francis Group, LLC Preface The advances in ultra-large-scale integration (ULSI) technology mainly have been based on downscaling of the minimum feature size of complementary metal-oxide semiconductor (CMOS) transistors. The limit of scaling is approaching and there are unsolved problems such as the number of electrons in the device’s active region. If this number is reduced to less than 10 electrons (or holes), quantum fluctuation errors will occur and the gate insulator thickness will become too small to block quantum mechanical tunneling, which may result in unacceptably large leakage currents. On the other hand, the recent evolution of nanotechnology may provide opportunities for novel devices, such as single-electron devices, carbon nanotubes, Si nanowires, and new materials, which may solve these problems. Utilization of quantum effects and ballistic transport characteristics also may provide novel func- tions for silicon-based devices. Among various candidate materials for nanometer scale devices, silicon nanodevices are particularly promising because of the existing silicon process infrastructure in semiconductor industries, the compatibility to CMOS circuits, and a nearly perfect interface between the natural oxide and silicon. The goal of this book is to give an update of the current state of the art in the field of silicon nanoelectronics. This book is a compact reference source for students, scientists, engineers and specialists in various fields including electron devices, solid- state physics and nanotechnology. Shunri Oda and David Ferry Copyright © 2006 Taylor & Francis Group, LLC About the Editors Shunri Oda is a professor at the Quantum Nano- electronics Research Center and the chair of the Department of Physical Electronics at the Tokyo Institute of Technology in Tokyo, Japan, where he obtained his doctorate in physical information pro- cessing. He is the director of the CREST and SORST NeoSilicon projects, which are sponsored by the Japan Science and Technology Agency. His recent research interests include formation of well- controlled silicon quantum structures and nanoscale silicon devices. He has authored more than 200 papers published in journals and conference pro- ceedings. David K. Ferry is the Regents’ Professor of Elec- trical Engineering at the Arizona State University in Tempe, Arizona, where he is actively involved in thesis and postdoctoral mentoring. He received his doctorate in elecrical engineering from The Univer- sity of Texas at Austin. He has coauthored many recent articles relevant to nanotechnology. In 2000, he received Arizona State University’s Outstanding Graduate Mentor Award, and in 1999 he received the Institute of Electrical and Electronics Engi- neers’s Cledo Brunetti Award, for advances in nano- electronics theory and experiment. Copyright © 2006 Taylor & Francis Group, LLC Contributors Richard Akis Department of Electrical Engineering Arizona State University Tempe, Arizona Haroon Ahmed Microelectronics Research Centre Cambridge, United Kingdom David K. Ferry Department of Electrical Engineering Arizona State University Tempe, Arizona David J. Frank IBM Watson Research Center Yorktown Heights, New York Akira Fujiwara NTT Basic Research Laboratories NTT Corporation Kanagawa, Japan Matthew J. Gilbert Department of Electrical Engineering Arizona State University Tempe, Arizona L. Jay Guo Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor, Michigan Toshiro Hiramoto Institute of Industrial Science University of Tokyo Tokyo, Japan Hiroya Ikeda Research Institute of Electronics Shizuoka University Hamamatsu, Japan Hiroshi Inokawa NTT Basic Research Laboratories NTT Corporation Kanagawa, Japan Yasuhiko Ishikawa Research Institute of Electronics Shizuoka University Hamamatsu, Japan Hisao Kawaura Fundamental Research Laboratories NEC Corporation Ibaraki, Japan Hiroshi Mizuta Department of Physical Electronics Tokyo Institute of Technology Tokyo, Japan Kazuo Nakazato Department of Electrical Engineering and Computer Science Nagoya University Nagoya, Japan Copyright © 2006 Taylor & Francis Group, LLC Katsuhiko Nishiguchi Quantum Nanoelectronics Research Center Tokyo Institute of Technology Tokyo, Japan Shunri Oda Tokyo Institute of Technology Quantum Nanoelectronics Research Center Tokyo, Japan Yukinori Ono NTT Basic Research Laboratories NTT Corporation Kanagawa, Japan Stephen M. Ramey Department of Electrical Engineering Arizona State University Tempe, Arizona Michiharu Tabe Research Institute of Electronics Shizuoka University Hamamatsu, Japan Yasuo Takahashi Graduate School of Information Science and Technology Hokkaido University Sapporo, Japan Sandip Tiwari School of Electrical and Computer Engineering Cornell University Ithaca, New York Kazuo Yano Hitachi Central Research Laboratory Tokyo, Japan Copyright © 2006 Taylor & Francis Group, LLC Contents Chapter 1 Physics of Silicon Nanodevices 1 David K. Ferry, Richard Akis, Matthew J. Gilbert, and Stephen M. Ramey 1.1 Introduction 1 1.2. Small MOSFETs 2 1.2.1 The Simple One-Dimensional Theory 3 1.2.2 Ballistic Transport in the MOSFET 4 1.3 Granularity 8 1.4 Quantum Behavior in the Device 10 1.4.1 The Effective Potential 10 1.4.1.1 Effective Carrier Wave Packet 11 1.4.1.2 Statistical Considerations 13 1.4.2. Quantum Simulations 16 1.4.2.1 The Device Structure 16 1.4.2.2 The Wave Function and Technique 17 1.4.2.3 Results 21 1.5 Quantum Dot Single-Electron Devices 23 1.6 Many-Body Interactions 23 1.7 Acknowledgments 26 References 26 Chapter 2 Practical CMOS Scaling 33 David J. Frank 2.1 Introduction 33 2.2 CMOS Technology Overview 33 2.2.1 Current CMOS Device Technology 33 2.2.2 International Technology Roadmap for Semiconductors (ITRS) Projections 35 2.3 Scaling Principles 36 2.3.1 General Scaling 37 2.3.2 Characteristic Scale Length 38 2.4 Exploratory Technology 40 2.4.1 New Materials 41 2.4.2 Fully Depleted SOI 42 2.4.3 Double-Gate and Multiple-Gate FET Structures 43 Copyright © 2006 Taylor & Francis Group, LLC 2.5 Limits to Scaling 48 2.5.1 Quantum Mechanics 48 2.5.2 Atomistic Effects 50 2.5.3 Thermodynamic Effects 53 2.5.4 Practical Considerations 53 2.6 Power-Constrained Scaling Limits 54 2.7 Summary 58 Acknowledgments 58 References 58 Chapter 3 The Scaling Limit of MOSFETs due to Direct Source-Drain Tunneling 65 Hisao Kawaura 3.1 Introduction 65 3.2 EJ-MOSFETs 68 3.2.1 Concept of EJ-MOSFETs 68 3.2.2 Fabrication of the Device Structure 70 3.2.3 Basic Operation 72 3.3 Direct Source-Drain Tunneling 75 3.3.1 Detection of the Tunneling Current 75 3.3.2 Numerical Study of the Tunneling Current 78 3.4 The Scaling Limit of MOSFETs 83 3.4.1 Estimation of Direct Source-Drain Tunneling in MOSFETs 83 3.4.2 Future Trends in Post-6-nm MOSFETs 85 3.5 Conclusion 86 Acknowledgments 86 References 86 Chapter 4 Quantum Effects in Silicon Nanodevices 89 Toshiro Hiramoto 4.1 Introduction 89 4.2 Quantum Effects in MOSFETs 90 4.2.1 Band Structures of Silicon 90 4.2.2 Surface Quantization 90 4.2.3 Carrier Confinement in Thin SOI MOS Structures 92 4.2.4 Mobility of Confined Carriers 92 4.3 Influences of Quantum Effects in MOSFETs 93 4.3.1 Threshold Voltage Increase in Bulk MOSFETs 93 4.3.2 Threshold Voltage Increase in FD-SOI MOSFETs 94 4.3.3 Mobility in Ultrathin FD-SOI MOSFETs 95 4.4 Quantum Effects in Ultranarrow Channel MOSFETs 95 4.4.1 Advantage of Quantum Effects in Ultranarrow Channel MOSFETs 95 Copyright © 2006 Taylor & Francis Group, LLC 4.4.2 Threshold Voltage Increase in n-Type Narrow Channel MOSFETs 95 4.4.3 Threshold Voltage Increase in n-Type and p-Type Narrow Channel MOSFETs 97 4.4.4 Threshold Voltage Adjustment Using Quantum Effects 99 4.4.5 Mobility Enhancement due to Quantum Effects 100 4.5 Summary 102 References 103 Chapter 5 Ballistic Transport in Silicon Nanostructures 105 Hiroshi Mizuta, Katsuhiko Nishiguchi and Shunri Oda 5.1 Introduction 105 5.2 Ballistic Transport in Quantum Point Contacts 106 5.3 Ballistic Transport in Ultra-Short Channel Vertical Silicon Transistors 113 5.3.1 Fabrication of Nanoscale Vertical FETs 113 5.3.2 Conductance Quantization in Nanoscale Vertical FETs 117 5.3.3 Characteristics under a Magnetic Field 121 5.3.4 Effects of Cross-Sectional Channel Geometries 125 5.4 Summary and Future Subjects 128 References 129 Chapter 6 Resonant Tunneling in Si Nanodevices 133 Michiharu Tabe, Hiroya Ikeda, and Yasuhiko Ishikawa 6.1 Introduction 133 6.1.1 Outline of Resonant Tunneling 133 6.1.1.1 Early Work on Resonant Tunneling 133 6.1.1.2 Resonant Tunneling in Si-Based Materials — Si/SiGe and Si/SiO 2 134 6.1.2 Quantum Confinement Effect in a Thin Si Layer 134 6.1.3 Double-Barrier Structures of SiO 2 /Si/SiO 2 Formed by Anisotropic Etching 136 6.2 Resonant Tunneling in SiO 2 /Si/SiO 2 139 6.2.1 Fabrication of an RTD 139 6.2.2 Resonant Tunneling in the Low Voltage Region 141 6.2.3 Hot-Electron Storage in the High-Voltage Region 143 6.2.4 Switching of Tunnel-Modes: Comparison with a Single Barrier 147 6.3 Zero-Dimensional Resonant Tunneling 148 6.3.1 Coexistence of Coulomb Blockade and Resonant Tunneling 148 6.3.2 Fabrication of a SiO 2 /Si-Dots/SiO 2 Structure 149 6.3.3 I-V Characteristics of an SiO 2 /Si-Dots/SiO 2 Tunnel Diode 151 Acknowledgment 152 References 152 Copyright © 2006 Taylor & Francis Group, LLC Chapter 7 Silicon Single-Electron Transistor and Memory 155 L. Jay Guo 7.1 Introduction 155 7.1.1 Quantum Dot Transistor 156 7.2 Theoretical Background 158 7.2.1 Energy of the Quantum Dot System 159 7.2.2 Conductance Oscillation and Potential Fluctuation 161 7.2.3 Transport under Finite Temperature and Finite Bias 162 7.3 Device Structure and Fabrication 165 7.4 Experimental Results and Analysis 166 7.4.1 Single-Electron Quantum-Dot Transistor 167 7.4.2 Single-Hole Quantum-Dot Transistor 168 7.4.3 Transport Characteristics under Finite Bias 169 7.4.4 Transport Through Excited States 172 7.5 Artificial Atom 173 7.6 Single Charge Trapping 174 7.7 Introduction to Memory Devices 176 7.8 Floating Gate Scheme 177 7.9 Single-Electron MOS memory (SEMM) 179 7.9.1 Structure of SEMM 179 7.9.2 Fabrication Procedure 180 7.9.3 Experimental Observations 181 7.9.4 Analysis 183 7.9.5 Effects of Trap States 186 7.10 Effect of Thicker Tunnel Oxide 187 7.11 Discussion 190 References 191 Chapter 8 Silicon Memories Using Quantum and Single-Electron Effects 195 Sandip Tiwari 8.1 Introduction 195 8.2 Single-Electron Effect 196 8.3 Single-Electron Transistors and Their Memories 199 8.3.2 Memories by Scaling Floating Gates of Flash Structures 200 8.4 Modeling of Transport: Tunneling 204 8.4.1 Tunneling in Oxide 204 8.4.2 Quantum Kinetic Equation 205 8.4.3 Carrier Statistics and Charge Fluctuations 207 8.5 Experimental Behavior of Memories 208 8.5.1 Percolation Effects 212 8.5.2 Limitations in Use of Field Effect 212 8.5.3 Confinement and Random Effects in Semiconductors 213 8.5.4 Variances due to Dimensions 213 8.5.5 Limits due to Tunneling 215 Copyright © 2006 Taylor & Francis Group, LLC [...]... 298 11.5 Conclusion 301 References 301 Copyright © 2006 Taylor & Francis Group, LLC 1 Physics of Silicon Nanodevices David K Ferry, Richard Akis, Matthew J Gilbert, and Stephen M Ramey 1.1 INTRODUCTION For the past several decades, miniaturization in silicon integrated circuits has progressed steadily with an exponential scale described by Moore’s Law.1 This incredible progress... as the full quantum treatment is discussed in a later section 1.3 GRANULARITY By granularity, we refer to the failure of thermodynamic averaging in small devices If we consider a silicon- on-insulator (SOI) MOSFET, with the silicon channel 10 nm thick, 20 nm wide and 10 nm long, and doped to 1019 cm-3, then there are only 20 dopant atoms in the channel If the carrier density is 1013 cm-2, then there... 257 10.4.2.1 Local Stability 257 10.4.2.2 Global Stability .260 10.4.3 Experimental Single-Electron Memory 264 10.4.3.1 First Experimental Single-Electron Memory 264 10.4.3.2 Silicon Single-Electron Memory 269 10.4.4 Single-Electron Memory Array .273 10.5 Conclusion 276 References 277 Copyright © 2006 Taylor & Francis Group, LLC Chapter 11...8.5.5.1 Tunneling in Oxide 215 8.5.5.2 Tunneling in Silicon 215 8.6 Can We Avoid Use of Collective Phenomena? 217 8.7 Summary 219 References 220 Chapter 9 SESO Memory Devices 223 Kazuo Yano 9.1 Introduction... metaloxide-semiconductor field-effect transistors (MOSFETs) and then turn to the much more important role in small transistors We follow this with a discussion of the 1 Copyright © 2006 Taylor & Francis Group, LLC 2 Silicon Nanoelectronics ultimately small device—the quantum dot and single-electron tunneling Finally, a discussion is given of many-body effects in such small devices Each of these topics will be discussed... important, because the same intuitive ideas carry over to the Landauer formula,15 which is often invoked in pure quantum transport situations Copyright © 2006 Taylor & Francis Group, LLC 3 Physics of Silicon Nanodevices 1.2.1 THE SIMPLE ONE-DIMENSIONAL THEORY In general, the current through a semiconductor device is found by writing an equation for the differential voltage drop along a point in the... in the channel, and µ V 2L (2.5) is the (average) velocity in the channel Hence, we may rewrite Equation (2.3) once again as I D = We nS v S Copyright © 2006 Taylor & Francis Group, LLC nD v D (2.6) 4 Silicon Nanoelectronics Decoherence regions L FIGURE 1.1 A conceptual device under bias The source is at the left and the drain at the right, as indicated by the two gray areas, which may be considered... the channel and return to x = 0 Here, vT is the velocity of the positively and negatively directed fluxes, and y is the direction of the channel Copyright © 2006 Taylor & Francis Group, LLC 5 Physics of Silicon Nanodevices depth (normal to the oxide-semiconductor interface) Solving for ts in Equation (2.9) and using this in Equation (2.8) yields aD = vT n (0, y ) tc 1 rc = vT n (0, y ) 1 + rc 1 + rc (2.10)... has given another version of a ballistic transport treatment for the MOSFET, and has used this to some success in fitting to experimental data19 Although Copyright © 2006 Taylor & Francis Group, LLC 6 Silicon Nanoelectronics Natori developed his expression with a full quantum mechanical basis, the approach is an outgrowth of the Duke tunneling formula,20 and we can follow a variation of the semiclassical... = 1 We now rescale the energy through the introduction of the scaled k vectors as kx2 = m x mz 2 k x , kz 2 = mx so that Copyright © 2006 Taylor & Francis Group, LLC m x mz 2 kz mz (2.18) 7 Physics of Silicon Nanodevices (k 2m * 2 E= 2 x ) + kz 2 , m* = mx mz (2.19) With this transformation, we may change the variables in Equation (2.17) as dk x dkz = my mx m* dk x dkz = dk x dkz = k dk d = 2 dEd m* . & Francis Web site at http://www.taylorandfrancis.com and the CRC Press Web site at http://www.crcpress.com Taylor & Francis Group is the Academic Division of T&F Informa plc. Copyright. Ferry Copyright © 2006 Taylor & Francis Group, LLC Published in 2006 by CRC Press Taylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300 Boca Raton, FL 33487-2742 ©2006 by Taylor &Francis. London New York Singapore A CRC title, part of the Taylor & Francis imprint, a member of the Taylor & Francis Group, the academic division of T&F Informa plc. SILICON NANOELECTRONICS Edited