Introduction to computing laboratory manual implementation of basic logic gates and functional ics on fpga

VIET NAM NATIONAL UNIVERSITY HO CHI MINH CITY – UNIVERSITY OF TECHNOLOGY FACULTY OF ELECTRICAL AND ELECTRONICS ENGINEERING DEPARTMENT OF ELECTRONICS oOo— INTRODUCTION TO COMPUTING LABORATORY MANUAL TABLE OF CONTENT ABOUT THE MANUAL LAB 1: IMPLEMENTATION OF BOOLEAN FUNCTION ON BREADBOARD WITH LOGIC GATES AND FUNCTIONAL ICS A PRELAB I IMPLEMENTATION OF DIGITAL CIRCUIT ON BREADBOARD II QUESTIONS: B LAB MANUAL: 13 I OBJECTIVES: .13 II LAB PREPARATION: 13 III LAB INSTRUCTION: 13 LAB 2: IMPLEMENTATION OF BASIC LOGIC GATES AND FUNCTIONAL ICs ON FPGA 26 A PRELAB .26 B LAB MANUAL: 34 I OBJECTIVES: .34 II LAB PREPARATION: 34 III LAB INSTRUCTIONS: .34 APPENDIX 1: A QUARTUS AND UBUNTU INSTALLATION ON WINDOWS 48 UBUNTU INSTALLATION ON WINDOWS: 48 I Download and install Xming and WSL2: 48 II Install Ubuntu on Windows: .48 III Some basic commands in Linux 51 B INSTALL QUARTUS 13.0SP1 53 APPENDIX 2: DIGITAL CIRCUIT DESIGN FLOW USING SYSTEMVERILOG 54 A DESIGN FLOW 54 B COMBINATIONAL LOGIC MODELING 55 I Problem: 55 Electronics Department Ho Chi Minh City University of Technology, Vietnam II Design: 55 C SEQUENTIAL LOGIC/FSM MODELING 69 I Problem: 69 II Problem analysis: 69 III Design: 70 Electronics Department Ho Chi Minh City University of Technology, Vietnam ABOUT THE MANUAL This document is intended to serve as a lab manual for students enrolled in Introduction to Computing Lab at HCMC University of Technology All the Lab Experiment is designed for students to: - Implement combinational and sequential systems on testboard, using digital ICs - Implement digital systems on FPGA, using SystemVerilog There are labs: Lab – Implementation of Boolean function on breadboard with Logic Gates and Functional ICs Lab – Implementation of Boolean function on FPGA with Logic Gates and Functional Digital ICs Lab – Implement Arithmetic Circuits and Sequential Circuit on breadboard Lab – Implement Arithmetic Circuits and Sequential Circuit on FPGA In order to complete the lab on time, all students are required to prelabs before each class Electronics Department Ho Chi Minh City University of Technology, Vietnam Lab 1: Implementation of Boolean function on breadboard with logic gates and functional ICs LAB 1:IMPLEMENTATION OF BOOLEAN FUNCTION ON BREADBOARD WITH LOGIC GATES AND FUNCTIONAL ICS Student’s name: Class: Student ID: Date: A PRELAB I IMPLEMENTATION OF DIGITAL CIRCUIT ON BREADBOARD Breadboard is the component on which the circuits can be set up and external experiments can be done The information about usage is given in Figure 1.1 Figure 1.1: Breadboard connections ❖ Remember these points when implement digital circuits on breadboard: - Inserting a DIP – Dual Inline Package: Before you insert a DIP into the breadboard, make sure all pins are straight When you insert a DIP in the breadboard, make sure that the pins on one side of the DIP are not connected to the pins on the other side of the DIP This means that the DIP must straddle one of the long gaps that divide the breadboard into separate sections - Providing access to the DIP: Electronics Department Ho Chi Minh City University of Technology, Vietnam Lab 1: Implementation of Boolean function on breadboard with logic gates and functional ICs As you wire your circuit, be sure to leave yourself easy access to the DIP's pins so that you can touch them with a probe and so that you can replace the DIP without disconnecting any wires In particular:  Never pass a wire over a DIP Instead, route the wires around the DIP  When you run wires to a DIP, use the breadboard holes farther away from the DIP before you use the holes that are closer - Removing a DIP: Do not use your fingers to remove a DIP from the breadboard It's too easy for your fingers to slip, causing the DIP to twist This results in bent pins Instead, use a chip puller to gently pull the chip up from the board - Input and output connections: There are two logic levels of input data: HIGH (1) level and LOW (0) level In this course, almost digital ICs are TTL, in which HIGH level and LOW level are prescribed as below: Input: the signal is called HIGH when the voltage is between 2V and 5V, and LOW when the voltage is from to 0.8V Output: the signal is called HIGH when the voltage is between 2.7V and 5V, and LOW when the voltage is from to 0.5V We usually apply 5V to implement HIGH level signal and 0V for LOW level signal In this lab, DIP switches are used to supply input signal Several ways of input connections are shown in Figure 1.2; resistors in these circuits are usually chosen 10 Kohm It is recommended that students implement input circuit as in Figure 1.2 (c), in which the signal equal when the switch is at upper position and vice versa (a) (b) (c) Figure 1.2: Input connections Electronics Department Ho Chi Minh City University of Technology, Vietnam Lab 1: Implementation of Boolean function on breadboard with logic gates and functional ICs Outputs are commonly displayed in LEDs, bar-LEDs, 7-segment LEDs,… Figure 1.3 shows how to connect the output to LED; LEDs in the left circuit will be on when the signal is while level signal turn off the lights in the right circuit Resistors in output circuits are usually chosen Kohm Figure 1.3: Output connections Example: Implement function 𝑓(𝑎, 𝑏) = 𝑎 + 𝑏 - Inputs: a,b - Outputs: f - ICs : 74HC32 Figure 1.4: Implementation of Boolean function F(a,b) = a + b Electronics Department Ho Chi Minh City University of Technology, Vietnam Lab 1: Implementation of Boolean function on breadboard with logic gates and functional ICs Figure 1.5: Implementation of Boolean function F(a,b) = a + b – application circuit Electronics Department Ho Chi Minh City University of Technology, Vietnam Lab 1: Implementation of Boolean function on breadboard with logic gates and functional ICs II QUESTIONS: What is numbering principle in DIP IC? Identify X, Y, Z, W in four circuits below: If f1,f2,f3,f4 are respectively 0,1,1,0 Indentify status of each LEDs in below figure Hoàn thành bảng sau (xem datasheet chúng) IC 74LS00 Pins Definition cổng NAND 14-VCC; 7-GND; = nand 2; = nand 5; …… Electronics Department Ho Chi Minh City University of Technology, Vietnam Lab 1: Implementation of Boolean function on breadboard with logic gates and functional ICs 74LS02 74LS04 74LS08 74LS32 74LS86 74LS125 74LS126 74LS138 74LS151 Compare IC 74LS125 and IC 74LS126 Explain the difference between these ICs Implement boolean function 𝑓(𝑥, 𝑦, 𝑧) = 𝑥 𝑦 + 𝑦𝑧: ICs and quantity: Circuit implementation (remember to note pin numbers on ICs) Electronics Department Ho Chi Minh City University of Technology, Vietnam Appendix 2: Sample lab Figure Appendix 2.4 Kết mơ sau hồn tất bước Verification Step 5: Done Implementation Set Up Step 1: Create wrapper.sv file The wrapper file will call design_1 like top.sv , but the input and output will be from the following file: https://www.terasic.com.tw/cgi-bin/page/archive.pl?CategoryNo=53&No=30&PartNo=4 (download file DE2_UserManual_1.6 or DE2 Pin Table ) input has data0_i , data1_i , and sel_i , uses switches as input, pin name as shown in table 4.1 in above file There are bits in total, assign data0_i as SW 2, SW 1, and SW 0, data1_i as SW 5, SW 4, and SW 3, and sel_i as SW and SW So input will be declared as line and assigned as lines 9, 10, 11 Output has only result_o and has bits, used as output, table 4.3 in the file above mentions led Select red LEDR 2, LEDR 1, and LEDR So the output will be declared as line and assigned as line 12 quartus/wrapper.sv module wrapper ( // input input logic [7:0] SW, // output output logic [2:0] LEDR ); design_1 dut ( Electronics Department Ho Chi Minh City University of Technology, Vietnam 63 Appendix 2: Sample lab 10 11 12 13 14 15 data0_i (SW[2:0] ), data1_i (SW[5:3] ), sel_i (SW[7:6] ), result_o(LEDR[2:0]) ); endmodule : wrapper Step : Create a project in Quartus Open Quartus Choose File → New Project Wizard a To directory quartus in ex01 Figure Appendix 2.5 Project directory Electronics Department Ho Chi Minh City University of Technology, Vietnam 64 Appendix 2: Sample lab b Name the project wrapper Since the actual project is the ex01 directory , it needs to be named exactly like the file name of the file, wrapper.sv Figure Appendix 2.6 Directory, Name, Top-Level Entity settings c Next to continue Select … to get the source code a Point to directory wrapper.sv which is quartus, select all files → Open → Add b Point to the directory containing the source code as src, select all files → Open → Add c Make sure the Type column is SystemVerilog HDL File d Next to continue For DE2 a Device family selects Cyclone II b Available devices select EP2C35F672C6 Electronics Department Ho Chi Minh City University of Technology, Vietnam 65 Appendix 2: Sample lab c Finish to complete Figure Appendix 2.7 Family and device settings Step 3: Import pin assignment of DE2 Choose Assignments➔ ➔Import Assignments Select … , point to quartus and select de2_pin_assign.qsf➔ ➔Open➔OK Step 4: Compilation Ctrl+L or Processing → Start Compilation Electronics Department Ho Chi Minh City University of Technology, Vietnam 66 Appendix 2: Sample lab Figure Appendix 2.8 Compilation resultsf Check the message window has no errors → proceed to upload to KIT Programmers Connect the DE2 using the USB cord at the Blaster port Figure Appendix 2.9 DE2 connection Electronics Department Ho Chi Minh City University of Technology, Vietnam 67 Appendix 2: Sample lab Choose Tools → Programmers Figure Appendix 2.10 Programmer Check connected: USB-Blaster X, if No Hardware is displayed, click Hardware Setup and select USB-Blaster X → Close Select Start to start loading Check in the box Progress is 100% (successful), ie successfully loaded Electronics Department Ho Chi Minh City University of Technology, Vietnam 68 Appendix 2: Sample lab Figure Appendix 2.11 Nạp kit thành công C SEQUENTIAL LOGIC/FSM MODELING I Problem: Design a circuit to count the number of button presses, if pressed and held, it is still counted as a press, and a 7-segment LED display shows the number of presses II Problem analysis: The system receives input from a push button (when the button is pressed, the system receives bit 1, otherwise, the system receives bit 0) and displays the output on a 7-segment LED (output less than or equal to 9) In addition, the sequential system has clock and reset inputs (selective active low reset) When the push button is pressed, the sequencer receives signal for only cycle The circuit includes a counter, the state of the counter increments by when receiving an input signal of In addition, the system needs a circuit that converts BCD to 7-segment LED, displays the status of the counter on LED paragraph The button block is an FSM (Finite State Machine) with states: IDLE (waiting to receive), PRESS (when the button is pressed in the first cycle), HOLD (the state is holding the button) Electronics Department Ho Chi Minh City University of Technology, Vietnam 69 Appendix 2: Sample lab Figure Appendix 2.12 Block diagram Figure Appendix 2.13 Button block – state diagram III Design: Create Project Source template from GitHub to use, name it ex02 gettemplate ex02 Code Create a design file named button.sv Electronics Department Ho Chi Minh City University of Technology, Vietnam 70 Appendix 2: Sample lab src/button.sv module button ( // input input logic clk_i, input logic rst_ni, input logic button_i, // output output logic stable_o 10 ); 11 12 // local declaration 13 typedef enum logic [1:0] { 14 IDLE, 15 PRESS, 16 HOLD 17 } state_e; 18 19 state_e state_d; 20 state_e state_q; 21 22 always_comb begin : proc_next_state 23 case (state_q) 24 IDLE: state_d = button_i ? PRESS : IDLE; 25 PRESS: state_d = button_i ? PRESS : IDLE; 26 HOLD: state_d = button_i ? HOLD : IDLE; 27 default: state_d = IDLE; 28 endcase 29 end 30 31 always_ff @(posedge clk_i) begin : proc_state_register 32 if (!rst_ni) 33 state_q button_i = (rand()%8 > 2); the value of button_i will be the result of rand()%8 , i.e get a random number from to 7, then compare it with 2, which means button_i will be equal to when the random number is divided remainder is to 7, and zero in the other case Thus, we have the probability: P(button_i = 1) = 5/8 = 62.5%, P(button_i = 0) = 3/8 = 37.5% This makes the probability of button_i getting of consecutive cycles higher, or the case of holding down is higher d Note 3: dut->rst_ni = (sim_unit > 4) && (rand()%30 != 0); the value of rst_ni will be always zero, i.e reset, when sim_unit