IEC TR 63094 Edition 1 0 201 7 06 TECHNICAL REPORT Multimedia systems and equipment – Multimedia signal transmission – Dependable l ine code with error correction IE C T R 6 3 0 9 4 2 0 1 7 0 6 (e n )[.]
I E C TR 63 ® Edition 201 7-06 TE C H N I C AL RE P ORT colour i n sid e M u l ti m e d i a s ys te m s an d e q u i pm en t – M u l ti m ed i a si g n al tran sm i s s i on – IEC TR 63094:201 7-06(en) D e pe n d abl e l i n e cod e wi th e rror correcti on T H I S P U B L I C AT I O N I S C O P YRI G H T P RO T E C T E D C o p yri g h t © I E C , G e n e v a , S wi tz e rl a n d All rights reserved Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from either IEC or IEC's member National Committee in the country of the requester If you have any questions about I EC copyright or have an enquiry about obtaining additional rights to this publication, please contact the address below or your local I EC member National Committee for further information IEC Central Office 3, rue de Varembé CH-1 21 Geneva 20 Switzerland Tel.: +41 22 91 02 1 Fax: +41 22 91 03 00 info@iec.ch www.iec.ch Ab ou t th e I E C The I nternational Electrotechnical Commission (I EC) is the leading global organization that prepares and publishes I nternational Standards for all electrical, electronic and related technologies Ab o u t I E C p u b l i ca ti o n s The technical content of IEC publications is kept under constant review by the IEC Please make sure that you have the latest edition, a corrigenda or an amendment might have been published colour I E C Catal og u e - webstore i ec ch /catal og u e The stand-alone application for consulting the entire bibliographical information on IEC International Standards, Technical Specifications, Technical Reports and other documents Available for PC, Mac OS, Android Tablets and iPad I E C pu bl i cati on s s earch - www i ec ch /search pu b The advanced search enables to find IEC publications by a variety of criteria (reference number, text, technical committee,…) It also gives information on projects, replaced and withdrawn publications E l ectroped i a - www el ectroped i a org i n sid e The world's leading online dictionary of electronic and electrical terms containing 20 000 terms and definitions in English and French, with equivalent terms in additional languages Also known as the International Electrotechnical Vocabulary (IEV) online I E C G l os sary - s td i ec ch /g l oss ary 65 000 electrotechnical terminology entries in English and French extracted from the Terms and Definitions clause of IEC publications issued since 2002 Some entries have been collected from earlier publications of IEC TC 37, 77, 86 and CISPR I E C J u st Pu bl i s h ed - webstore i ec ch /j u stpu bl i sh ed Stay up to date on all new IEC publications Just Published details all new publications released Available online and also once a month by email I E C C u stom er S ervi ce C en tre - webstore i ec ch /csc If you wish to give us your feedback on this publication or need further assistance, please contact the Customer Service Centre: csc@iec.ch I E C TR 63 ® Edition 201 7-06 TE C H N I C AL RE P ORT colour i n sid e M u l ti m ed i a s ys te m s an d e q u i pm en t – M u l ti m ed i a si g n al tran sm i s s i on – D epe n d abl e l i n e cod e wi th e rror correcti on INTERNATIONAL ELECTROTECHNICAL COMMISSION ICS 33.1 60.60; 35.1 ISBN 978-2-8322-4337-4 Warn i n g ! M ake s u re th a t you ob tai n ed th i s p u b l i cati on from an au th ori zed d i stri b u tor ® Registered trademark of the International Electrotechnical Commission –2– I EC TR 63094: 201 © I EC 201 CONTENTS FOREWORD I NTRODUCTI ON Scope Norm ative references Terms, definitions and abbreviated term s Terms and definitions Abbreviated terms 4b/1 0b line code Overview Forward error correction (FEC) Embedded clock 4 DC balance 4b/1 0b data encoding Frame form at Fram e Setup command I dle command 1 Encoding 1 Decoding 1 Error handling 1 1 -bit error 1 2-bit error Over 3-bit error Annex A (informative) Real-time scheduling Annex B (informative) Characteristics of em bedded clock Annex C (inform ative) Characteristics of DC balance Annex D (inform ative) I mplem entation of a decoder Bibliograph y Figure – A humanoid robot Figure A – EDF scheduling Table Table Table Table Table Table – The 4b/1 0b data transform – Setup comm and – I dle command 1 – The 4b/1 0b look-up 1 B – The length of successive or in case of -bit error C – An example of the isomery of and in a successive 0-bit window I EC TR 63094:201 © I EC 201 –3– INTERNATI ONAL ELECTROTECHNI CAL COMMISSI ON M U L T I M E D I A S YS T E M S AN D E Q U I P M E N T – M U L T I M E D I A S I G N AL T R AN S M I S S I O N – D E P E N D AB L E L I N E C O D E WI T H E R RO R C O RRE C T I O N FOREWORD ) The I nternati on al Electrotechni cal Comm ission (I EC) is a worl d wid e organization for stan dardization com prisin g all n ation al el ectrotechnical comm ittees (I EC National Comm ittees) The object of I EC is to prom ote internati onal co-operation on all questions concerni ng stand ardi zati on in the el ectrical an d electronic fields To this end and in additi on to other acti vities, I EC publish es I nternational Stan dards, Techn ical Specifications, Technical Reports, Publicl y Avail abl e Specificati ons (PAS) an d Gu ides (h ereafter referred to as “I EC Publication(s)”) Thei r preparation is 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technical com m ittees and I EC Nati on al Com m ittees for any person al i njury, property d am age or other dam age of any nature whatsoever, wheth er di rect or indirect, or for costs (includ i ng leg al fees) and expenses arisi ng out of the publ ication, use of, or relian ce upon, this I EC Publicati on or any other I EC Publications 8) Attention is drawn to th e N orm ative references cited in th is publ ication Use of the referenced publ ications is indispensable for the correct applicati on of this publication 9) Attention is drawn to the possibility that som e of the elem ents of this I EC Publication m ay be the su bject of patent rig hts I EC shall not be held responsibl e for identifyi ng any or all such patent ri ghts The m ain task of I EC technical com mittees is to prepare I nternational Standards H owever, a technical committee m ay propose the publication of a technical report when it has collected data of a different kind from that which is normally published as an I nternational Standard, for exam ple "state of the art" I EC TR 63094, which is a technical report, has been prepared by I EC technical committee 00: Audio, video and multimedia systems and equipm ent The text of this technical report is based on the following documents: Enqui ry draft Report on votin g 00/2823A/DTR 00/2871 /RVDTR Full information on the voting for the approval of this technical report can be found in th e report on voting indicated in the above table –4– I EC TR 63094: 201 © I EC 201 This docum ent has been drafted in accordance with the I SO/I EC Directives, Part The com mittee has decided that the contents of this document will remain unchanged until the stability date indicated on the I EC website under "http://webstore iec ch" in the data related to the specific document At this date, the document will be • • • • reconfirmed, withdrawn, replaced by a revised edition, or am ended A bilingual version of this publication m ay be issued at a later date I M P O R T AN T – T h e ' c o l o u r i n s i d e ' th at it tai n s u n d e rs t a n d i n g c o l o u r p ri n t e r of c o l o u rs i ts wh i c h c o n te n ts l og o a re U s e rs on th e co ve r p ag e o f th i s c o n s i d e re d sh ou l d to t h e re fo re be p u b l i cati o n u s e fu l p ri n t th i s fo r i n d i c ate s th e d o cu m en t c o rre c t u sin g a I EC TR 63094:201 © I EC 201 –5– INTRODUCTION This document defines a line code that incorporates error correction capability to communicate reliabl y among multimedia components, I /O peripherals and computers A number of complex multim edia machines, in particular robots, automobiles, and network routers, have a growing dem and for distributed processing I n addition, modernization of facilities such as factories, offices, schools, and homes is creating a ubiquitous and multimedia computing environm ent U nlike conventional PC applications for documentation and I nternet applications that exchange texts without hard time constraints, these types of cooperative com puting require reliable real-tim e responses to ph ysical events occurring in the real world I n order for distributed nodes to cooperate in real-time, an interconnecting network shall realize real-tim e and dependable comm unication without re-sending on noisy environm ents The 4b/1 0b provides a dependable line code for such real-tim e comm unications between multimedia com ponents, I /O peripherals and/or com puters by providing embedded clock, DC balance, error detection and error correction features The real-tim e aspect means that the exactness of the system including operations and comm unications depends not onl y on the result, but also on the time it took to achieve the result I n the narrow sense, the real-time aspect m eans that the tim e constraint, including deadlines or cycles, m ust be m et Real-tim e tasks with the tim e constraints are generall y scheduled and executed by a real-tim e scheduler and a real-time operating system Most real-time scheduling algorithms assume that the WCET (worst-case execution time) of each task is given A real-tim e scheduling algorithm converts a time constraint of each real-time task to a priority Most real-tim e operating system s based on such real-tim e schedulers pre-em pt and execute tasks in order of priority at every tick to meet the tim e constraint As real-tim e scheduling algorithm s, the earliest deadline first (EDF) scheduler, the rate monotonic (RM) scheduler, and their variations have been established, as explained in Annex A These algorithm s comm onl y schedule tasks based on priorities determ ined by the time constraints Most real-tim e scheduling algorithm s assum e that the WCRT (worst-case response time) of each communication packet is given in case of communication I n order to appl y real -time scheduling algorithm s to real-time comm unications, pre-emptive communication, which is achieved by Responsive Link (I SO/I EC 24740), and the error correction capability to prevent the re-sending a broken packet are required A line code is a lowest-level communication protocol on a comm unication line Most current line codes have a few typical functions including em bedded clock, DC balance and basic error detection features The 8b/1 0b codec is a major exam ple, which is used for PCI Express, U SB 0, SATA, I EEE1 394b, and 0GbE But no conventional line code has an error correction capability When an encoded code (a 0b code) is broken during comm unication, the multi-bits of the decoded code (the 8b code) are corrupted I n other words, when a single bit error occurs in an encoded 0-bit code, the decoded 8-bit code (a byte) is com pletel y broken When an error is detected on the decoder, the broken data is normall y re-transmitted under an upper-level comm unication protocol H owever, re-transm ission is not allowed in order to realize real-tim e comm unication I t is hard for a bit-level error correction code that includes the H amm ing code and the BCH code to incorporate error correction capability, because multi-bits of the decoded code are broken even if a single-bit error occurs on the encoded code –6– I EC TR 63094: 201 © I EC 201 In order to incorporate error correction capability on the 8b/1 0b codec, a block-level error correction including RS (Reed-Solom on) is required as a large packet-level error correction But the block-level error correction is not suitable for real-time com munication, because the communication latency becomes longer as it is im possible to correct the corrupted data until all corresponding packets are received The line code 4b/1 0b has the following distinctive features for real-time comm unications: a) b) c) d) embedded clock; DC balance; error detection; error correction No conventional line code supports the above features at one time For example, the industrywide standard 8b/1 0b codec can be easil y replaced with the 4b/1 0b line code for highl y reliable comm unications Figure shows a distributed control configuration of a humanoid robot as one of the typical applications of the 4b/1 0b line code The electronic control part of the humanoid robot consists of several control nodes with local sensing and actuating devices The distributed controllers are connected to each other by Responsive Link I n this figure, rectangles represent node controllers, and dotted lines show comm unication links such as the Responsive Link that is a point-to-point serial link IEC Figure – A humanoid robot For a hum anoid robot to walk stabl y, a servo loop of ms or shorter is needed I n this configuration, the farthest two nodes can exchange a 6-byte packet within μ s Si n ce th e tim e is guaranteed not to fluctuate, the distributed control of a hum anoid is considered to be sufficientl y possible Since man y actuators that generate noises are em bedded inside the robot, the line code is required for noise tolerance The 4b/1 0b is the line code that has error correction capability Currentl y m an y I /O interfaces and comm unication standards, including PCI Express (PCI e), USB 0, SATA, I EEE 394b, and 0GbE use the 8b/1 0b codec as a line code The 8b/1 0b has a lot of functions and its code rate is relativel y high (about 80 %) H owever if one bit error occurs in an encoded data (1 0b), the decoded data (8b) will be broken com pletel y Therefore when the 8b/1 0b codec is used on noisy environment such as inside the robot, an upper-level error correction code is required For error correction, it is hard to appl y an y bit-level error codec including the H amm ing code and the BCH code, because multiple decoded bits (1 -byte) will be broken even if an encoded bit is inverted So, block-level error correction including I EC TR 63094: 201 © I EC 201 –7– Reed-Solomon, which is long latency ECC that is not suitable for real-tim e applications, is required H ence, a reliable line code with ECC is required for such applications Patent The I nternational Electrotechnical Comm ission (I EC) draws attention to the fact that it is claim ed that compliance with this docum ent may involve the use of patents as listed below: PATENT No 5900850 (J apan) I EC takes no position concerning the evidence, validity and scope of these patent rights The holder of these patent rights has assured the I EC that he/she is willing to negotiate licences either free of charge or under reasonable and non-discriminatory terms and conditions with applicants throughout the world I n this respect, the statem ent of the holder of these patent rights is registered with I EC I nform ation m ay be obtained from : Headquarters for Research Coordination and Administration 2-1 5-45 Mita, Minato-ku, Tokyo 08-8345 J apan Attention is drawn to the possibility that some of the elements of this docum ent may be the subj ect of patent rights other than those identified above I EC shall not be held responsible for identifying an y or all such patent rights I SO (www iso org/patents) and I EC (http://patents iec ch) maintain on-line data bases of patents relevant to their standards Users are encouraged to consult the data bases for the m ost up to data inform ation concerning patents –8– I EC TR 63094:201 © I EC 201 M U L T I M E D I A S YS T E M S AN D E Q U I P M E N T – M U L T I M E D I A S I G N AL T R AN S M I S S I O N – D E P E N D AB L E L I N E C O D E WI T H E R RO R C O RRE C T I O N S cop e This docum ent specifies the line code 4b/1 0b for dependable m ultimedia signal transmission required for com plex m achines, such as robots and autom obiles This docum ent corresponds to the functions specified in layer to layer of the OSI reference m odel (I SO/I EC 7498) The purpose of this document is to facilitate the developm ent and use of the 4b/1 0b in dependable system s by providing a line code protocol This docum ent provides a line code protocol for interconnections am on g distributed real-tim e system s, including em bedded system s, control system s, amusem ent systems, robot system s, and intelligent buildings The 4b/1 0b can achieve the line code with ECC (error code correction) The 4b/1 0b is the line code that realizes em bedded clock, DC balance, error detection and error correction at a time; it is not possible to satisfy these functions in one codec by conventional schemes, and the 4b/1 0b line code can achieve highl y reliable and dependable digital comm unications N o rm a t i ve re fe re n c e s There are no normative references in this docum ent T e rm s , d e fi n i t i o n s a n d a b b re vi a t e d t e rm s For the purposes of this docum ent, the followi ng terms and definitions apply I SO and I EC m aintain term inological databases for use in standardization at the following addresses: • • I EC Electropedia: available at http://www electropedia org/ I SO Online browsing platform: available at http://www iso org/obp T e rm s a n d d e fi n i t i o n s b yt e B group of eight bits h a l f b yte HB unit for transmitting, the size of which is bits 4b original half byte (4-bit) data 0b encoded 0-bit data for transm itting I EC TR 63094:201 © I EC 201 –9– 3.1 symbol unit for encoding, the size of which is bits 3.1 frame unit for transmitting, the size of which is bits 3.2 Abbreviated terms ECC error correction code DC direct current WCET worst case execution time WCRT worst case response time 4.1 4b/1 0b line code Overview The line code 4b/1 0b handles a 0-bit frame encoded by 4-bit digits The original bits of inform ation digits are encoded into a 0-bit frame by the look-up table shown in Table A byte (8 bits) is divided into two half bytes (4b) A half byte (4b) is encoded to a sym bol (1 0b) A frame consists of a symbol and is transm itted to the communication line Since four bits are encoded to ten bits by the 4b/1 0b line code, the communication speed at 000 MH z is approximatel y equal to 400 Mbit/s 4.2 Forward error correction (FEC) The line code 4b/1 0b should provide error-free transmission for reliable real-time control Error correction should be perform ed by hardware The 4b/1 0b perform s line-code-level error correction Original four-bit data (4b) are encoded to 0-bit transmitting data with embedded clock, DC balance, 2-bit error detection, and -bit error correction for a half byte of data (4 bits of inform ation digits) The H amming distance of an y digits in a sym bol (1 0b code) is longer than or equals for -bit error correction and 2-bit error detection 4.3 Embedded clock The line code 4b/1 0b ensures that successive bits or bits are within five bits, even if a bit error/symbol occurs Characteristics of the embedded clock are shown in Annex B In the case of inside sym bol digits, successive bits or bits are within five bits In the case of inter-sym bol digits, successive bits or bits are within five bits When each sym bol has -bit error, if the distance of error bits is greater than four-bit, the successive or bits are within five bits In the case of two-bit errors, discontinuity of digits is not guaranteed 4.4 DC balance In order for the line code 4b/1 0b not to allow a current to flow in the communication cable, the numbers of and in a sym bol are sam e for DC balance But DC balance between successive symbols is not necessary Characteristics of the DC balance are shown in Annex C – 10 – I EC TR 63094:201 © I EC 201 If an error occurs, bit-level DC balance is not guaranteed among nearest neighbour error sym bols 4.5 4b/1 0b data encodin g In the case of encoding, the look-up table that satisfies the three above conditions including em bedded clock, DC balance, and error detection and correction, is used as shown in Table Original 4-bit digits (4b) are encoded to 0-bit digits (1 0b) Table – The 4b/1 0b data transform 4.6 4.6 4b 0b 0000 1 001 01 00 0001 01 001 00 001 1 001 001 001 01 001 1 00 01 00 01 1 01 0001 01 01 1 0001 001 01 01 01 1 01 00 01 1 1 01 0001 01 000 001 1 0001 001 01 1 0001 1 01 01 01 01 00 01 1 01 001 01 1 00 01 01 001 1 01 001 001 1110 01 01 01 001 1111 01 01 01 01 Frame format Frame A frame consists of bits, including inform ation bits and redundant bits implicitl y, as shown in Table 4.6.2 Setup comm and After the power is first applied, or after an unexpected burst link error occurs, the synchronization between the sender and the receiver can be lost I n such a situation, the link is initialized explicitl y The encoder in the initial mode sends the setup pattern shown in Table The decoder can distinguish the pattern from normal frames and thus switches to the initial m ode The initialized decoder interprets the first receiving frame after the initialization as the start frame of a new fram e sequence Table – Setup com mand Setup pattern 01 01 001 01 I EC TR 63094:201 © I EC 201 – 11 – I d l e co m m an d When an encoder has no actual comm unication data, the encoder sends the idle pattern shown in Table in order to m aintain the fram e synchronization of the link Tab l e – I d l e co m m an d I dle pattern 01 01 01 001 E n cod i n g The look-up table that satisfies embedded clock, DC balance, error detection and correction, and control com mands including setup and idle command is shown in Table I n the case of encoding, the 4b/1 0b look-up table is directl y used T a b l e – T h e b / b l o o k- u p 4b 0b 0000 1 001 01 00 0001 01 001 00 001 1 001 001 001 01 001 1 00 01 00 01 1 01 0001 01 01 1 0001 001 01 01 01 1 01 00 01 1 1 01 0001 01 000 001 1 0001 001 01 1 0001 1 01 01 01 01 00 01 1 01 001 01 1 00 01 01 001 1 01 001 001 1110 01 01 01 001 1111 01 01 01 01 setup 01 01 001 01 idle 01 01 01 001 D e co d i n g Decoding is based on the shortest distance decoding on the H amming distance An implementation of a decoder is illustrated in Annex D 9 E rro r h a n d l i n g - b i t e rro r The encoding scheme of the 4b/1 0b can autom aticall y detect and correct an y -bit error in a frame H owever, when errors of greater than bits are present in a fram e, the error correction mechanism does not work I n such a situation, the calculation of the syndrom e results in the case described in or the case described in – 12 – I EC TR 63094:201 © I EC 201 2-bi t error In this case, the decoder can detect an unrecoverable fatal error I f a fatal error is detected in a fram e, then the decoder sh ould not try to correct digits in the received fram e and should interrupt the controller (processor) Over 3-bit error Although the probability of this case is very low, the decoder cannot detect the occurrence of the fatal error in this case Since this error is indistinguishable from other correctable -bit errors, the received fram e is inadequatel y modified by the decoder This situation allows transm ission of an incorrect packet and is highly undesirable Therefore, when simple -bit errors are corrected in two successive frames, the decoder considers this to be a fatal error that cannot be corrected, and so handles the frame in the manner described in 9.2 I EC TR 63094:201 © I EC 201 – 13 – Annex A (informative) Real-time scheduling There are several real-time scheduling algorithm s, including earliest deadline first (EDF), which is an optim al d yn amic scheduling algorithm , and rate monotonic (RM), which is an optim al static scheduling algorithm The EDF algorithm translates the deadlin e to a priority The priority of the task with the earliest deadline becomes the highest The RM algorithm translates the cycle tim e to a priority The task with the shortest cycle is assigned to have the highest priority Man y other real-time scheduling algorithms also translate the tim e constraint to a priority Figure A shows an exam ple of EDF scheduling Priority-based scheduling is performed at every clock tick and at timings when tasks are released (invoked), as well as at execution finish J1 J2 J3 J4 J5 Release tim e 10 Deadlin e IEC Figu re A.1 – EDF scheduling This real-time task scheduling process can be regarded as an overtaking process, i e tasks with higher priorities are executed earlier than tasks with lower priorities I n order to implem ent this idea in a distributed real-tim e system , comm unication of higher priority tasks should be able to overtake other com munication The Responsive Link (I SO/I EC 24740) does this at every node The Responsive Link covers the functionality of layer to layer of the OSI reference m odel (I SO/I EC 7498) – 14 – I EC TR 63094:201 © I EC 201 Annex B (informative) Characteristics of embedded clock The line code 4b/1 0b ensures that successive bits or bits are within five bits, even if a bit error/sym bol occurs In the case of inside sym bol digits, successive bits or bits are within five bits For exam ple, if a -bit error occurs on the 1 001 001 sym bol, successive bits or bits are within five bits as shown in Table B Table B.1 – The length of successive or in case of -bit error The number of errors Line code The length of successive or (origi nal ) 1 001 001 01 001 001 1 0001 001 1 1 01 001 1 01 1 001 1 0001 001 1 001 0001 1 001 1 01 1 001 01 1 001 0000 1 001 001 I n case of inter-symbol digits, successive bits or bits are within five bits For exam ple, inter-symbol successive bits or bits of the 1 001 001 and 001 1 0001 symbols are within five bits When each sym bol has a -bit error, if the distance of error bits is greater than four bits, the successive bits or bits are within five bits as follows • • 1 001 001 001 1 0001 : original 1 001 0000 0001 0001 : -bit error/sym bol I n the case of two-bit errors, discontinuity of digits is not guaranteed I EC TR 63094:201 © I EC 201 – 15 – Annex C (informative) Characteristics of DC balance I n order for the line code 4b/1 0b not to allow a current to flow in the communication cable, the numbers of and in a sym bol are same for DC balance But DC balance between successive sym bols is not necessary I n other words, the isom ery of and inside a symbol is guaranteed But the isom ery of and in an y connecting 0-bit window is not guaranteed, as shown in Table C Table C.1 – An example of the isomery of and in a successive 0-bit window Window number 0-bi t window The number of s 1 001 01 00 01 1 01 0001 1 001 01 00 01 1 01 0001 1 001 01 00 01 1 01 0001 1 001 01 00 01 1 01 0001 1 001 01 00 01 1 01 0001 1 001 01 00 01 1 01 0001 1 001 01 00 01 1 01 0001 1 001 01 00 01 1 01 0001 1 001 01 00 01 1 01 0001 1 001 01 00 01 1 01 0001 I f an error occurs, bit-level DC balance is not guaranteed among nearest neighbour error sym bols – 16 – I EC TR 63094:201 © I EC 201 An n e x D (informative) I m p l e m e n ta ti o n o f a d e c o d e r Each Ham ming distance HD i between a received fram e (1 0b) and each symbol Ci as shown in Table is calculated I n the expressions below, k is a 4-bit binary shown in the left colum n in Table and Ck is a 0-bit binary in the right column in Table Minimum value of the Hamm ing distance HD m in is calculated by the following equation: HD m in = m in{ HD i } When HD k is equal to HD m in , the 0b Ck is decoded to the 4b k • I f HD m in is equal to 0, the 0b Ck is decoded to the 4b k without error I f HD m in is equal to , the 0b Ck is decoded to the 4b k I n this case, the -bit error is corrected, and the corrected error should be informed to the upper layer I f HD m in is greater than , the 0b Ck is decoded to all 0s I n this case, a multiple-bit error is detected, and the error should be inform ed to the upper layer The decoded 4b k (all 0s) is broken The 0b symbol Ck and corresponding decoded 4b k are determ ined I EC TR 63094:201 © I EC 201 – 17 – Bibliography I SO/I EC 7498 (all parts), In form a tion tech n olo gy – Ope n Syste m In tercon n ection – Ba sic re feren ce m ode l I SO/I EC 24740, In form a tion techn o logy – Resp on sive L in k (RL ) Albert X Widmer, 8b /1 0b report, 2004-1 -03 e n codin g a n d decodin g for h igh spe e d a p p lica tion s , I BM research PCI Express base specification, PCI -SI G http: //pcisig.com/ Universal Serial Bus Revision 3.0 Specification, U SB I mplem enters Forum http://www usb.org/ Serial I /O interface for hard drive, SSD, and optical drive, Serial ATA working group http://www sata-io.org/ _