Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 BSI Standards Publication Plasma display panels — Part 3-2: Interface — Electrical interface NO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAW raising standards worldwide™ BRITISH STANDARD Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 National foreword This British Standard is the UK implementation of EN 61988-3-2:2009 It is identical to IEC 61988-3-2:2009 The UK participation in its preparation was entrusted to Technical Committee EPL/47, Semiconductors A list of organizations represented on this committee can be obtained on request to its secretary This publication does not purport to include all the necessary provisions of a contract Users are responsible for its correct application © BSI 2010 ISBN 978 580 60350 ICS 31.260 Compliance with a British Standard cannot confer immunity from legal obligations This British Standard was published under the authority of the Standards Policy and Strategy Committee on 31 January 2010 Amendments issued since publication Amd No Date 标准分享网 www.bzfxw.com 免费下载 Text affected Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 EUROPEAN STANDARD EN 61988-3-2 NORME EUROPÉENNE EUROPÄISCHE NORM November 2009 ICS 31.260 English version Plasma display panels Part 3-2: Interface Electrical interface (IEC 61988-3-2:2009) Panneaux d'affichage plasma Partie 3-2: Interface Interface électrique (CEI 61988-3-2:2009) Plasmabildschirme Teil 3-2: Schnittstelle Elektrische Schnittstelle (IEC 61988-3-2:2009) This European Standard was approved by CENELEC on 2009-09-01 CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Central Secretariat or to any CENELEC member This European Standard exists in three official versions (English, French, German) A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same status as the official versions CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Cyprus, the Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland and the United Kingdom CENELEC European Committee for Electrotechnical Standardization Comité Européen de Normalisation Electrotechnique Europäisches Komitee für Elektrotechnische Normung Central Secretariat: Avenue Marnix 17, B - 1000 Brussels © 2009 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members Ref No EN 61988-3-2:2009 E Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 EN 61988-3-2:2009 -2- Foreword The text of document 110/181/FDIS, future edition of IEC 61988-3-2, prepared by IEC TC 110, Flat panel display devices, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 61988-3-2 on 2009-09-01 The following dates were fixed: – latest date by which the EN has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2010-06-01 – latest date by which the national standards conflicting with the EN have to be withdrawn (dow) 2012-09-01 Annex ZA has been added by CENELEC Endorsement notice The text of the International Standard IEC 61988-3-2:2009 was approved by CENELEC as a European Standard without any modification In the official version, for Bibliography, the following notes have to be added for the standards indicated: IEC 60068-1 NOTE Harmonized as EN 60068-1:1994 (not modified) ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ IEC 60107-1 NOTE Harmonized as EN 60107-1:1997 (not modified) 标准分享网 www.bzfxw.com 免费下载 Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 -3- EN 61988-3-2:2009 Annex ZA (normative) Normative references to international publications with their corresponding European publications The following referenced documents are indispensable for the application of this document For dated references, only the edition cited applies For undated references, the latest edition of the referenced document (including any amendments) applies NOTE When an international publication has been modified by common modifications, indicated by (mod), the relevant EN/HD applies Publication Year Title EN/HD Year Plasma display panels Part 1: Terminology and letter symbols EN 61988-1 2003 2) IEC 61988-1 - 1) IEC 61988-2-1 - 1) Plasma display panels Part 2-1: Measuring methods - Optical EN 61988-2-1 2002 2) IEC 61988-2-2 - 1) Plasma display panels EN 61988-2-2 Part 2-2: Measuring methods - Optoelectrical 2003 2) ANSI TIA/ EIA-644-A - 1) Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits - JEIDA-59 1999 Digital Interface Standards for Monitor - - ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ 1) Undated reference 2) Valid edition at date of issue Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 –2– 61988-3-2 © IEC:2009 CONTENTS Scope .5 Normative references .5 Terms, definitions and abbreviations 3.1 Terms and definitions 3.2 Abbreviations Electrical interface requirements Electrical interface of digital signal 5.1 5.2 5.3 5.4 5.5 Annex A Basic configuration Interface input signal definition Pin assignment Input signal timing 10 Power requirement 10 (informative) LVDS, TTL and TMDS 11 Bibliography 24 Figure – Block diagram of an example interface of data signal Figure A.1 – Interface configuration 11 Figure A.2 – Timing chart for resolution 1024 x 768 14 Figure A.3 – Logic power and LVDS signals sequencing diagram 15 ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ Figure A.4 – Data enable timing parameters 16 Figure A.5 – Interface configuration 17 Figure A.6 – Interface configuration 20 Table – Example of interface signal function Table – Example of connector pin assignments Table A.1 – Signal definition and function 12 Table A.2 – Connector pin assignment 13 Table A.3 – Input signal timing specification for resolution 1024x768 15 Table A.4 – Input signal specifications 18 Table A.5 – Connector pin assignments 19 Table A.6 – Input signal specifications 21 Table A.7 – Example of pin assignment of connector 21 Table A.8 –Limiting values (Absolute maximum rating system) 22 Table A.9 – Electrical characteristics 23 标准分享网 www.bzfxw.com 免费下载 Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 61988-3-2 © IEC:2009 –5– PLASMA DISPLAY PANELS – Part 3-2: Interface – Electrical interface Scope This part of IEC 61988 defines the electrical interface of digital video data signals, synchronization signals and functional signals between the image processing board of the PDP set and the control board of the PDP module, and defines the description of the pin assignment of the connectors Normative references The following referenced documents are indispensable for the application of this document For dated references, only the edition cited applies For undated references, the latest edition of the referenced document (including any amendments) applies IEC 61988-1, Plasma display panels – Part 1: Terminology and letter symbols IEC 61988-2-1, Plasma display panels – Part 2-1: Measuring methods – Optical IEC 61988-2-2, Plasma display panels – Part 2-2: Measuring methods – Optoelectrical ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ TIA/EIA-644A, Electrical characteristics of low voltage differential signaling (LVDS) interface circuits JEIDA-59-1999, Digital interface standards for monitor (only available in English) Terms, definitions and abbreviations 3.1 Terms and definitions For the purposes of this document, the terms and definitions given in IEC 61988-1, IEC 60068-1 and IEC 60107-1 as well as the following apply 3.1.1 image processing board circuit board including A/D converter, scaler and video decoder, deinterlacing for image signal from input device such as TV-tuner, PC, DVD, etc 3.2 Abbreviations NOTE The following are acronyms for reference TTL Transistor-transistor logic LVDS Low voltage differential signalling TMDS Transition minimized differential signalling HS Horizontal synchronization VS Vertical synchronization DE Data enable DCLK Data clock APC Auto power control Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 –6– 61988-3-2 © IEC:2009 Electrical interface requirements The electrical interface of PDP module is a power sequence and a digital interface of PDP module The power sequence of PDP module is power on- and off-sequence of all power supplies in and to PDP module The power on- and off-sequence of PDP module shall be fully described in each relevant specification The digital signal interface is either an LVDS, a TTL or a TMDS interface, whose signal encodes the digital video data and function control signals Function control signal, which is the additional signal, except digital video signal, to control the functions such as APC, shall be fully described in each detail specification The interface configuration, input signal definition, pin assignment, input signal timing and power requirement shall be described in each detail specification 5.1 Electrical interface of digital signal Basic configuration The basic configuration of electrical interface of digital signal is shown in Figure as one of examples Examples of LVDS, TTL and TMDS are explained in Annex A ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ 标准分享网 www.bzfxw.com 免费下载 Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 61988-3-2 © IEC:2009 –7– Image processing board PDP module Electrical interface signal (Display data signal and control signal) R0 – Rn–1 R0 – Rn–1 G0 – Gn–1 G0 – Gn–1 B0 – Bn–1 B0 – Bn–1 LVDS TTL TMDS VS VS HS HS DE DE DCLK DCLK Function control signals Function control signals ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ IEC 1348/09 NOTE The image processing board includes A/D converter, scaler and video decoder for image signal from input device such as TV-tuner, PC, DVD, etc NOTE Ri, Gi and Bi: ith bit data for n-bit digital video signal of red, green and blue, respectively (i=0 to n-1) Figure – Block diagram of an example interface of data signal 5.2 Interface input signal definition The example of interface signal definition and function is as follows in Table Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 61988-3-2 © IEC:2009 –8– Table – Example of interface signal function Symbol Rx IN0+ (or RA+) Rx IN0 (or RA-) Rx IN1+ (or RB+) Rx IN1 (or RB-) Rx IN2+ (or RC+) Rx IN2 (or RC-) Rx IN3+ (or RD+) Rx IN3 (or RD-) Rx IN4+ (or RE+) Rx IN4- I I I I I Rx CLKIN+ (or CLK+) Rx CLKIN(or CLK-) Function Display data signal: R0, R1, R2, R 3, R4, R5, G0 Display data signal: G1, G2, G3, G4, G5, B0, B1 Display data signal: Description LVDS differential data (+) LVDS differential data (-) LVDS differential data (+) LVDS differential data (-) LVDS differential data (+) B , B , B , B , HS, I I I VS, DE Display data signal and control signal: R , R , G , G , B , B , RES LVDS differential data (-) LVDS differential data (+) LVDS differential data (-) ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ I I (or RE-) NOTE I/O I Display data signal and control signal: B , B , G , G , R , R , RES Data clock signal: LVDS differential data (+) LVDS differential data (-) LVDS differential clock (+) DCLK LVDS differential clock (-) I This example shows the case of LVDS with 10-bit video signal 标准分享网 www.bzfxw.com 免费下载 Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 61988-3-2 © IEC:2009 – 12 – A.1.1.2 Interface input signal specification The input signal (display data signal and control signal) is converted from parallel data to serial data with the LVDS transmitter and further converted into six sets of differential signals before input to the PDP module The LVDS signal definition and function is as follows in Table A.1 Table A.1 – Signal definition and function Symbol I/O Rx IN0+ (or RA+) I Rx IN0- (or RA-) I Rx IN1+ (or RB+) I Rx IN1- (or RB-) I Rx IN2+ (or RC+) I Rx IN2- (or RC-) I Rx IN3+ (or RD+) I Rx IN3- (or RD-) Function Display data signal: R0, R1, R2, R 3, R4, R5, G0 Display data signal: G1, G2, G3, G4, G5, B0, B1 Display data signal: B , B , B , B , HS, VS, DE Display data signal and control signal: R , R , G , G , B , B , RES Description LVDS differential data (+) LVDS differential data (-) LVDS differential data (+) LVDS differential data (-) LVDS differential data (+) LVDS differential data (-) LVDS differential data (+) ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ I Rx IN4+ (or RE+) I Rx IN4- (or RE-) I Rx CLKIN+ (or DCLK+) I Rx CLKIN(or DCLK-) I Display data signal and control signal: B , B , G , G , R , R , RES LVDS differential data (-) LVDS differential data (+) LVDS differential data (-) LVDS differential clock (+) Data clock signal: DCLK LVDS differential clock (-) 标准分享网 www.bzfxw.com 免费下载 Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 61988-3-2 © IEC:2009 A.1.1.3 – 13 – Pin assignment The pin names may be given in the form of Table A.2 Table A.2 – Connector pin assignment Pin no Pin name GND GND Rx IN0- Rx IN0+ GND GND Rx IN1- Rx IN1+ GND 10 GND 11 Rx IN2- 12 Rx IN2+ 13 GND 14 GND ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ 15 Rx CLKIN- 16 Rx CLKIN+ 17 GND 18 GND 19 Rx IN3- 20 Rx IN3+ 21 GND 22 GND 23 GND 24 GND 25 RX IN4- 26 RX IN4+ 27 GND 28 GND 29 GND 30 GND 31 GND Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 61988-3-2 © IEC:2009 – 14 – A.1.1.4 Input signal timing chart Figure A.2 is an example of input signal timing chart tvsync VS tvw tvbp tvfp HS Line number 768 - - 767 768 - - 767 768 - thsync HS thw thbp DCLK tdclk thfp 024 DE (Period of valid data) Data Shaded area ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ D1 D2 D3 D1 024 : Invalid data IEC 1350/09 Figure A.2 – Timing chart for resolution 024 x 768 标准分享网 www.bzfxw.com 免费下载 Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 61988-3-2 © IEC:2009 A.1.1.5 – 15 – Input signal timing specification Table A.3 is an example of input signal timing specification Table A.3 – Input signal timing specification for resolution 1024 x 768 No Symbol Typical value Unit t vsync 16,667 ms 60 Hz, 806 lines t vw 0,12 ms lines t vbp 0,60 ms 29 lines t vfp 0,06 ms lines t hsync 20,667 μs 344 dots t hw 2,09 μs 136 dots t hbp 2,46 μs 160 dots t hfp 0,36 μs 24 dots t dclk 15,385 ns 64,999 MHz A.1.1.6 Remark ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ Power sequencing requirements The LVDS interface requires the logic power and data/control signal sequencing and the data enable timing of Figure A.3 and Figure A.4 t1 Power Supply VDD 0,9 VDD 0V 0,9 VDD 0,1 VDD 0,1 VDD t2 t3 t4 Valid data LVDS interface 0,5 ms ≤ t1 ≤ 10 ms ≤ t2 ≤ 50 ms ≤ t3 ≤ 50 ms 500 ms ≤ t4 IEC 1351/09 Figure A.3 – Logic power and LVDS signals sequencing diagram Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 61988-3-2 © IEC:2009 – 16 – thsync HS thbp DE thw thfp tha (horizontal active) tvsync VS tvbp DE tvw tvfp tva (vertical active) DE-only timing mode tha or tva tdeb tha or tva ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ DE IEC 1352/09 Figure A.4 – Data enable timing parameters 标准分享网 www.bzfxw.com 免费下载 Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 61988-3-2 © IEC:2009 A.1.2 A.1.2.1 – 17 – TTL Basic configuration Figure A.5 shows an example of interface configuration of TTL Image processing board R0 ∼ Rn–1 G0 ∼ Gn–1 B0 ∼ Bn–1 PDP module R0 ∼ Rn–1 n bits G0 ∼ Gn–1 n bits n bits B0 ∼ Bn–1 VS VS HS HS DE DE DCLK DCLK ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ Function control signals m bits Function control signals Figure A.5 – Interface configuration IEC 1353/09 Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 61988-3-2 © IEC:2009 – 18 – A.1.2.2 Interface input signal specification Table A.4 is an example of input signal specification Table A.4 – Input signal specifications Symbol Function R ~R n-1 n bits red video signal G ~G n-1 n bits green video signal B ~B n-1 n bits blue video signal Remarks Display data signal: R n-1 : MSB*, R : LSB** Display data signal: G n-1 : MSB*, G : LSB** Display data signal: B n-1 : MSB*, B : LSB** This signal specifies the data period for HS Horizontal synchronous signal one horizontal line Control of the next line begins at the rising edge of HS ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ Timing signal that controls the start of VS Vertical synchronous signal the screen Control of the next screen begins at the rising edge of VS When DE signal is high, data is valid DE Data enable DCLK Clock for video signal When DE signal is low, data is invalid Latch the video signal at falling edge * MSB: Most significant bit (the highest intensity bit) ** LSB: Least significant bit (the lowest intensity bit) 标准分享网 www.bzfxw.com 免费下载 Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 61988-3-2 © IEC:2009 A.1.2.3 – 19 – Pin assignment Table A.5 shows an example of the pin assignments of TTL Table A.5 – Connector pin assignments Pin Pin no Pin name Pin no Pin name Pin no GND 24 B2 47 GND NC 25 GND 48 G5 GND 26 B3 49 GND NC 27 GND 50 G6 GND 28 B4 51 GND NC 29 GND 52 G7 GND 30 B5 53 GND NC 31 GND 54 R0 GND 32 B6 55 GND 10 NC 33 GND 56 R1 11 GND 34 B7 57 GND name ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ A.1.2.4 12 DCLK 35 GND 58 R2 13 GND 36 NC 59 GND 14 DE 37 GND 60 R3 15 CTRL1 38 G0 61 GND 16 DHS 39 GND 62 R4 17 CTRL2 40 G1 63 GND 18 DVS 41 GND 64 R5 19 RESET 42 G2 65 GND 20 B0 43 GND 66 R6 21 GND 44 G3 67 GND 22 B1 45 GND 68 R7 23 GND 46 G4 Input signal timing chart Description of input signal timing chart is basically same as that of LVDS (See Figure A.2.) A.1.2.5 Input signal timing specification Description of input signal timing specification is basically same as that of LVDS (See Table A.3.) Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 61988-3-2 © IEC:2009 – 20 – A.1.3 TMDS A.1.3.1 Basic configuration Figure A.6 shows an example of interface configuration of TMDS Image processing board PDP module TX2 (Red) R0 – Rn–1 R0 – Rn–1 TX1 (Green) G0 – Gn–1 B0 – Bn–1 VS TMDS transmitter (Parallel / Serial) TX0 (Blue) G0 – Gn–1 TMDS receiver (Serial / Parallel) B0 – Bn–1 VS HS HS DCLK DE DE DCLK DCLK ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ Function control signals m bits Function control signals IEC 1354/09 Figure A.6 – Interface configuration 标准分享网 www.bzfxw.com 免费下载 Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 61988-3-2 © IEC:2009 A.1.3.2 – 21 – Interface input signal specification Table A.6 is an example of input signal specification Table A.6 – Input signal specifications Symbol I/O Function Description TX0+ I Display data signal: TMDS differential data (+) TX0- I B , B , B , B , B , B , B , B , HS, VS TMDS differential data (-) TX1+ I Display data signal: TMDS differential data (+) TX1- I G ,G , G , G , G , G ,G , G , PLL SYNC TMDS differential data (-) TX2+ I Display data signal: TMDS differential data (+) TX2- I R0, R1, R2, R 3, R4, R5, R 6, R7 TMDS differential data (-) TXC+ I Data clock signal: TMDS differential clock (+) TXC- I DCLK TMDS differential clock (-) A.1.3.3 Pin assignment Table A.7 shows an example of the pin assignments of TMDS ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ Table A.7 – Example of pin assignment of connector NOTE Pin no Pin name TX1 + TX1 - TX1 SHELD TXC SHELD TXC + TXC - GND +5VDC RES 10 RES 11 TX2 + 12 TX2 - 13 TX2 SHELD 14 TX0 SHELD 15 TX0 + 16 TX0 - 17 RES 18 SENS 19 DDC/SDA 20 DDC/SCL SDA is the abbreviation for ‘Serial data’, and SCL for ‘Serial clock’ Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 61988-3-2 © IEC:2009 – 22 – A.1.3.4 Input signal timing chart Description of input signal timing chart is basically same as that of LVDS (See Figure A.2.) A.1.3.5 Input signal timing specification Description of input signal timing specification is basically same as that of LVDS (See Table A.3.) A.2 Function control signal Function control signal is the additional signal, except digital video signal, to control the functions such as APC, SDA and SCL A.3 A.3.1 Electrical characteristics Limiting values (Absolute maximum rating system ) Limiting values (Absolute maximum rating system ) are those values beyond which the safety of the device cannot be guaranteed Table A.8 shows an example of Limiting values (Absolute maximum rating system ) Table A.8 –Limiting values (Absolute maximum rating system ) Subclause ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ Limiting values Symbol Value Min Max Unit Supply voltage range of LVDS V CC –0,3 V A.1.2 Supply voltage range of TTL V CC –0,5 V A.1.3 Supply voltage range of TMDS V CC –0,3 V A.1.1 标准分享网 www.bzfxw.com 免费下载 Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 61988-3-2 © IEC:2009 A.3.2 – 23 – Signal voltage and current Table A.9 shows an example of the electrical characteristics of LVDS, TMDS and TTL Table A.9 – Electrical characteristics Signal Parameter Common mode Voltage Differential input high LVDS Threshold Receiver Differential input low Symbol V OC V TH V TL Threshold Input Current Differential input I IN V idiff Conditions V CC = 3,3 V Min Typ Max Unit 1,125 1,25 1,375 mV 100 mV V OC = +1,2 V V CC = 3,3 V V OC = +1,2 V V CC = 3,3 V –100 mV V IN = +2,4 V / V V CC = 3,6 V V CC = 3,3 V 150 ±10 μA 1200 mV Voltage Input ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ TMDS common Receiver Mode V icm V CC = 3,3 V V CC – 300 V CC – 37 mV V I(OC) V CC = 3,3 V V CC – 10 V CC – 10 mV Voltage Open circuit Input Voltage High–level input V IH V CC = V V IL V CC = V 0,8 V I IK V CC = V –18 mA 20 μA –0,6 mA V Voltage Low-level input Voltage TTL Input clamp Current High-level input I IH Current Low-level input Current NOTE I IL Common condition: Ta = 25 °C V CC = 5,5 V V IN = 2,7 V V CC = 5,5 V V IN = 0,5 V Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI BS EN 61988-3-2:2009 – 24 – 61988-3-2 © IEC:2009 Bibliography IEC 60068-1, Environmental testing – Part 1: General and guidance IEC 60107-1, Methods of measurement on receivers for television broadcast transmissions – Part 1: General considerations – Measurements at radio and video frequencies _ ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ 标准分享网 www.bzfxw.com 免费下载 Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ This page deliberately left blank Licensed Copy: athen reading, Reading University Library, 24/01/2010 10:28, Uncontrolled Copy, (c) BSI British Standards Institution (BSI) BSI is the independent national body responsible for preparing British Standards and other standards-related publications, information and services It presents the UK view on standards in Europe and at the international level It is incorporated by Royal Charter Revisions Information on standards British Standards are updated by amendment or revision Users of British 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