Bsi bs en 61189 5 1 2016

BS EN 61189-5-1:2016 BSI Standards Publication Test methods for electrical materials, printed boards and other interconnection structures and assemblies Part 5-1: General test methods for materials and assemblies — Guidance for printed board assemblies BRITISH STANDARD BS EN 61189-5-1:2016 National foreword This British Standard is the UK implementation of EN 61189-5-1:2016 It is identical to IEC 61189-5-1:2016 The UK participation in its preparation was entrusted to Technical Committee EPL/501, Electronic Assembly Technology A list of organizations represented on this committee can be obtained on request to its secretary This publication does not purport to include all the necessary provisions of a contract Users are responsible for its correct application © The British Standards Institution 2016 Published by BSI Standards Limited 2016 ISBN 978 580 87381 ICS 31.180 Compliance with a British Standard cannot confer immunity from legal obligations This British Standard was published under the authority of the Standards Policy and Strategy Committee on 31 October 2016 Amendments/corrigenda issued since publication Date Text affected BS EN 61189-5-1:2016 EUROPEAN STANDARD EN 61189-5-1 NORME EUROPÉENNE EUROPÄISCHE NORM September 2016 ICS 31.180 English Version Test methods for electrical materials, printed boards and other interconnection structures and assemblies - Part 5-1: General test methods for materials and assemblies - Guidance for printed board assemblies (IEC 61189-5-1:2016) Méthodes d'essai pour les matériaux électriques, les cartes imprimées et autres structures d'interconnexion et ensembles - Partie 5-1: Méthodes d'essai générales pour les matériaux et assemblages - Lignes directrices pour les assemblages de cartes circuit imprimé (IEC 61189-5-1:2016) Prüfverfahren für Elektromaterialien, Leiterplatten und andere Verbindungsstrukturen und Baugruppen - Teil 5-1: Allgemeine Prüfverfahren für Materialien und Baugruppen Leitfaden für Baugruppen von Leiterplatten (IEC 61189-5-1:2016) This European Standard was approved by CENELEC on 2016-08-09 CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC Management Centre or to any CENELEC member This European Standard exists in three official versions (English, French, German) A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the same status as the official versions CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and the United Kingdom European Committee for Electrotechnical Standardization Comité Européen de Normalisation Electrotechnique Europäisches Komitee für Elektrotechnische Normung CEN-CENELEC Management Centre: Avenue Marnix 17, B-1000 Brussels © 2016 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC Members Ref No EN 61189-5-1:2016 E BS EN 61189-5-1:2016 EN 61189-5-1:2016 European foreword The text of document 91/1273/CDV, future edition of IEC 61189-5-1, prepared by IEC/TC 91 "Electronics assembly technology" was submitted to the IEC-CENELEC parallel vote and approved by CENELEC as EN 61189-5-1:2016 The following dates are fixed: • latest date by which the document has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2017-05-09 • latest date by which the national standards conflicting with the document have to be withdrawn (dow) 2019-08-09 Attention is drawn to the possibility that some of the elements of this document may be the subject of patent rights CENELEC [and/or CEN] shall not be held responsible for identifying any or all such patent rights Endorsement notice The text of the International Standard IEC 61189-5-1:2016 was approved by CENELEC as a European Standard without any modification In the official version, for Bibliography, the following notes have to be added for the standards indicated: IEC 60068 (series) NOTE Harmonized as EN 60068 (series) IEC 60068-1:2013 NOTE Harmonized as EN 60068-1:2014 IEC 60068-2-20 NOTE Harmonized as EN 60068-2-20 IEC 60068-2-58:2015 NOTE Harmonized as EN 60068-2-58:2015 IEC 61189-1 NOTE Harmonized as EN 61189-1 IEC 61189-5 (series) NOTE Harmonized as EN 61189-5 (series) IEC 61189-5 NOTE Harmonized as EN 61189-5 IEC 61189-5-1:2016 NOTE Harmonized as EN 61189-5-1:2016 IEC 61189-5-2:2015 NOTE Harmonized as EN 61189-5-2:2015 IEC 61189-5-3:2015 NOTE Harmonized as EN 61189-5-3:2015 IEC 61189-5-4:2015 NOTE Harmonized as EN 61189-5-4:2015 IEC 61189-6 NOTE Harmonized as EN 61189-6 IEC 61190-1-1 NOTE Harmonized as EN 61190-1-1 IEC 61190-1-2 NOTE Harmonized as EN 61190-1-2 IEC 61190-1-3 NOTE Harmonized as EN 61190-1-3 BS EN 61189-5-1:2016 EN 61189-5-1:2016 IEC 61249-2-7 NOTE Harmonized as EN 61249-2-7 IEC 62137:2004 NOTE Harmonized as EN 62137:2004 ISO 9001 NOTE Harmonized as EN ISO 9001 ISO 9455-1 NOTE Harmonized as EN 29455-1 ISO 9455-2 NOTE Harmonized as EN 29455-2 –2– BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 CONTENTS FOREWORD INTRODUCTION Scope Normative references Accuracy, precision and resolution 3.1 General 3.2 Accuracy 3.3 Precision 3.4 Resolution 10 3.5 Report 10 3.6 Student’s t distribution 10 3.7 Suggested uncertainty limits 11 Catalogue of approved test methods 12 List of contents of the IEC 61189-5 series 12 Annex A (informative) Tests 13 Annex B (informative) Guidance documents and handbooks 15 B.1 B.2 B.3 B.4 B.5 B.6 B.7 B.8 B.9 B.10 B.11 B.12 B.13 B.14 B.15 B.16 B.17 B.18 B.19 B.20 B.21 General 15 Handbook and guide to supplement IPC-J-STD-001 15 Guidelines for Electrically Conductive Surface Mount Adhesives (IPC-3406) 15 Users Guide for Cleanliness of Unpopulated Printed Boards (IPC-5701) 15 Guidelines for OEM’s in Determining Acceptable Levels of Cleanliness of Unpopulated Printed Boards (IPC-5702) 15 Surface Insulation Resistance Handbook (IPC-9201) 16 Material and Process Characterisation / Qualification Test Protocol for Assessing Electrochemical Performance (IPC-9202) 16 User Guide for the IPC/IEC B52 Process Qualification Test Vehicle (IPC-9203) 16 PWB Assembly Soldering Process Guideline for Electronic Components (IPC-9502) 16 Aqueous Post Solder Cleaning Handbook (IPC-AC-62A) 17 Guidelines for Cleaning of Printed Boards and Assemblies (IPC-CH-65A) 17 Handbook (IPC-J-STD-005) 17 Acceptability of Electronic Assemblies (IPC-HDBK-610) 18 Guidelines for Design, Selection and Application of Conformal Coatings (IPC-HDBK-830) 18 Solder mask Handbook (IPC-HDBK-840) 18 Guidelines and Requirements for Electrical Testing of Unpopulated Printed Boards (IPC-9252) 19 In-Process DPMO and Estimated Yield for PCAs (IPC-9261A) 19 Assembly Soldering Process Guideline for Electronic Components (IPC-9502 PWB) 20 Users Guide for IPC-TM-650, Method 2.6.27, Thermal Stress, Convection Reflow Assembly Simulation (IPC-9631) 20 High Temperature Printed Board Flatness Guideline (IPC-9641) 20 User Guide for the IPC-TM-650, Method 2.6.25, Conductive Anodic Filament (CAF) Resistance Test (Electrochemical Migration Testing) (IPC-9691A) 21 BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 –3– B.22 Mechanical Shock Test Guidelines for Solder Joint Reliability (IPC-JEDEC9703) 21 B.23 Printed Circuit Assembly Strain Gage Test Guideline (IPC-JEDEC-9704A) 22 Bibliography 23 Table – Student’s t distribution 11 Table A.1 – General test methods for materials and assemblies 13 BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 –4– INTERNATIONAL ELECTROTECHNICAL COMMISSION TEST METHODS FOR ELECTRICAL MATERIALS, PRINTED BOARDS AND OTHER INTERCONNECTION STRUCTURES AND ASSEMBLIES – Part 5-1: General test methods for materials and assemblies – Guidance for printed board assemblies FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC National Committees) The object of IEC is to promote international co-operation on all questions concerning standardization in the electrical and electronic fields To this end and in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC Publication(s)”) Their preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with may participate in this preparatory work International, governmental and nongovernmental organizations liaising with the IEC also participate in this preparation IEC collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions determined by agreement between the two organizations 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international consensus of opinion on the relevant subjects since each technical committee has representation from all interested IEC National Committees 3) IEC Publications have the form of recommendations for international use and are accepted by IEC National Committees in that sense While all reasonable efforts are made to ensure that the technical content of IEC Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any misinterpretation by any end user 4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications transparently to the maximum extent possible in their national and regional publications Any divergence between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter 5) IEC itself does not provide any attestation of conformity Independent certification bodies provide conformity assessment services and, in some areas, access to IEC marks of conformity IEC is not responsible for any services carried out by independent certification bodies 6) All users should ensure that they have the latest edition of this publication 7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and members of its technical committees and IEC National Committees for any personal injury, property damage or other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC Publications 8) Attention is drawn to the Normative references cited in this publication Use of the referenced publications is indispensable for the correct application of this publication 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights IEC shall not be held responsible for identifying any or all such patent rights International Standard IEC 61189-5-1 has been prepared by IEC technical committee 91: Electronics assembly technology The text of this standard is based on the following documents: CDV Report on voting 91/1273/CDV 91/1354/RVC Full information on the voting for the approval of this standard can be found in the report on voting indicated in the above table This publication has been drafted in accordance with the ISO/IEC Directives, Part BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 –5– A list of all parts in the IEC 61189 series, published under the general title Test methods for electrical materials, printed boards and other interconnection structures and assemblies, can be found on the IEC website The committee has decided that the contents of this publication will remain unchanged until the stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to the specific publication At this date, the publication will be • reconfirmed, • withdrawn, • replaced by a revised edition, or • amended –6– BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 INTRODUCTION IEC 61189 relates to test methods for printed boards and printed board assemblies, as well as related materials or component robustness, irrespective of their method of manufacture The standard is divided into separate parts, covering information for the designer and the test methodology engineer or technician Each part has a specific focus Methods are grouped according to their application and numbered sequentially as they are developed and released In some instances test methods developed by other technical committees (for example, TC 104) have been reproduced from existing IEC standards in order to provide the reader with a comprehensive set of test methods When this situation occurs, it will be noted on the specific test method If the test method is reproduced with minor revisions, those paragraphs that are different are identified This part of IEC 61189 contains test methods for evaluating printed board assemblies as well as materials used in the manufacture of electronic assemblies The methods are selfcontained, with sufficient detail and description so as to achieve uniformity and reproducibility in the procedures and test methodologies It was decided by TC 91 that the contents of IEC 61189-5 and IEC 61189-6 be merged into a series of documents in the following way: IEC 61189-5-1, Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 5-1: General test methods for materials and assemblies – Guidance for printed board assemblies IEC 61189-5-2:2015, Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 5-2: General test methods for materials and assemblies – Soldering flux for printed board assemblies IEC 61189-5-3:2015, Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 5-3: General test methods for materials and assemblies – Soldering paste for printed board assemblies IEC 61189-5-4:2015, Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 5-4: General test methods for materials and assemblies – Solder alloys and fluxed and non-fluxed solid wire for printed board assemblies IEC 61189-5-501:—, Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 5-501: General test methods for materials and assemblies – Surface insulation resistance (SIR) testing of solder fluxes IEC 61189-5-502:—, Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 5-502: General test methods for materials and assemblies – SIR testing of assemblies IEC 61189-5-503:—, Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 5-503: General test methods for materials and assemblies – Conductive Anodic Filaments (CAF) testing of circuit boards IEC 61189-5-504:—, Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 5-504: General test methods for materials and assemblies – Process ionic contamination testing Under consideration – 14 – IEC standard IEC 61189-5-4 Designation BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 Test C: Chemical test methods 5-4C01 Determination of the percentage of flux on/in flux-coated and/or flux-cored solder X: Mechanical test methods 5-4X01 Spread test, extracted cored wires or preforms 5-4X02 Spitting test of flux-cored wire solder 5-4X03 Solder pool test IEC 61189-5-501 Under consideration IEC 61189-5-502 Under consideration IEC 61189-5-503 Under consideration IEC 61189-5-504 Under consideration BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 – 15 – Annex B (informative) Guidance documents and handbooks B.1 General The documents listed in Clauses B.2 to B.23 relate to the specific soldering materials or test methods employed B.2 Handbook and guide to supplement IPC-J-STD-001 IPC-J-STD-001 and IPC-HDBK-001 not exclude any acceptable process used to make the electrical connections, as long as the methods used will produce completed solder joints conforming to the acceptability requirements of the IPC-J-STD-001 This handbook describes materials, methods, and verification criteria that, when applied as recommended or required, will produce quality soldered electrical and electronic assemblies The intent of this handbook is to explain the ‘‘how-to,’’ the ‘‘why,’’ and fundamentals for these processes, in addition to implementing control over processes rather than depending on enditem inspection to determine product quality B.3 Guidelines for Electrically Conductive Surface Mount Adhesives (IPC-3406) This document covers guidelines for selecting electrically conductive adhesives for use in assembly of components to printed circuit boards (PCB) or similar wiring inter-connect systems The focus is on the use of adhesives as solder alternatives The process discussion attempts to stay within the bounds of the existing solder assembly infrastructure as much as possible Both major types of adhesives, isotropic (conducting equally in all directions) and anisotropic (unidirectional conductivity), are covered The two major divisions of polymer adhesives, thermosets and thermoplastics, are described B.4 Users Guide for Cleanliness of Unpopulated Printed Boards (IPC-5701) If you are in the electronics industry, sooner or later you have to, will, or should deal with the issue of the cleanliness of the unpopulated printed circuit boards (bare boards) Residues on circuit boards are directly related to the reliability of the produced hardware and can result in serious failures if not monitored and controlled This document is the product of the IPC Bare Board Cleanliness Assessment Task Group and was drafted to provide individuals who deal with these issues some guidance on how the issues should be approached and specified in purchase documents B.5 Guidelines for OEM’s in Determining Acceptable Levels of Cleanliness of Unpopulated Printed Boards (IPC-5702) Every electronics manufacturer, whether an original equipment manufacturer (OEM) or contract manufacturer (CM), will be faced with determining if the unpopulated printed boards used in the finished assembly have an adequate level of cleanliness The question of ‘‘how clean is clean enough’’ has been asked repeatedly in the last decade in many IPC committees This is a very complex topic, with many critical considerations For this reason there is not an unique methodology that determines acceptability This document was developed as guidance for the individual(s) responsible for determining these criteria for their company – 16 – BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 IPC-5701 covers many aspects of how cleanliness is measured on printed boards, as well as many critical factors to consider when specifying board cleanliness in purchasing documents This reference, and associated technical papers, show the many inadequacies of current test methodologies, as well as explaining why there are no ‘‘golden numbers’’ for cleanliness What is acceptably clean for one segment of the industry may be unacceptable for more demanding segments of the industry (e.g., medical or aerospace) B.6 Surface Insulation Resistance Handbook (IPC-9201) This document is intended to cover the broad spectrum of temperature-humidity (TH) testing, associated terminology, and suggested techniques for proper surface insulation resistance testing as defined in IEC 61189-5-5, Test Methods 5E01 and 5E02 B.7 Material and Process Characterisation / Qualification Test Protocol for Assessing Electrochemical Performance (IPC-9202) This material and process characterization/qualification test records changes in surface insulation resistance (SIR) on a representative sample of a printed circuit assembly (PCA) It quantifies any deleterious effects that might arise from solder flux or other process residues left on external surfaces after soldering, which can cause unwanted electro-chemical reactions that grossly affect reliability It uses test vehicles that are intended to be representative of the electronic circuits that are in production It is a test yielding both quantitative and qualitative data This test may be used for Process Qualification, demonstrating that a proposed manufacturing process or process change can produce hardware with acceptable end-item performance related to cleanliness Changes may involve any assembly process step, or a change in the printed board supplier, solder mask or metallization, soldering material supplier, conformal coating, etc The test vehicle construction will vary depending upon the type of change being evaluated B.8 User Guide for the IPC/IEC B52 Process Qualification Test Vehicle (IPC-9203) The electronics manufacturing process is often very complex, with dozens of variables that impact the quality and reliability of the manufactured assemblies in the end use environment Two of the important variables for consideration are the kinds of residues that remain on the electronic assembly and the effects that these residues have on reliability These two variables are most often referred to in discussions on assembly “cleanliness” Whilst there are several different ways to measure residues and their effects on electrical performance, the two most common approaches in the industry are ionic cleanliness testing, for determination of ionic residues, and surface insulation resistance (SIR) testing, for the evaluation of electrochemical failures in humid environments This document focuses on the IPC-B-52 standard test assembly and how it is used as an evaluation tool for electronics manufacturing processes from a “cleanliness” perspective B.9 PWB Assembly Soldering Process Guideline for Electronic Components (IPC-9502) This document describes manufacturing solder process limits that components subjected to IPC-9501, IPC-9503, IPC-9504 and J-STD-020 would survive It does not include optimum conditions for assembly, but rather guides to assure components are not damaged BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 – 17 – This document applies to both surface-mount (SM) and through-hole (TH) components that are wave soldered, reflowed or hand soldered This document is intended to complement other industry documents, listed in applicable documents B.10 Aqueous Post Solder Cleaning Handbook (IPC-AC-62A) This handbook addresses aqueous cleaning of electrical/electronic parts and application tools after soldering The content of the text is intended to provide a basic understanding of the subject and to serve as a guide to users or prospective users of aqueous cleaning technology, allowing selection or improvement of aqueous cleaning processes B.11 Guidelines for Cleaning of Printed Boards and Assemblies (IPC-CH-65A) This manual is a road map for current and developing cleaning issues, rather than to function as a highly detailed document for all areas touched upon In areas of cleaning where recent detailed IPC manuals already exist, the relevant sections in IPC-CH-65A will contain only sufficient information to make the reader reasonably knowledgeable This guideline manual refers the reader to appropriate existing IPC documents (where they exist) for in-depth information on the particular subject An example of such a reference IPC manual is IPC-AC62, Aqueous Cleaning Handbook It is only where existing IPC documents are not available that IPC-CH-65A will expand information beyond the basics in order to cover what is currently known about the subject A benefit of this approach is that the manual does not become unwieldy and tends to foster a user-friendly environment Both bare board fabrication and assembly cleanliness issues are addressed The fabrication and assembly sections are separated for ease of access In the original IPC-CH-65, these sections were very much intertwined However, it was recognized that for a subject such as the required cleanliness of finished bare boards, basically redundant teachings are required for both the fabrication and assembly sections B.12 Handbook (IPC-J-STD-005) This handbook is a companion to the solder paste standard J-STD-005 and should be considered to be a guide to help assess the applicability of a solder paste for its use in surface-mount technology (SMT) processes This document also suggests some test methods that can help with designing and testing solder pastes It is intended for use by both vendors and users of solder paste Solder pastes are unique materials, whose performance in a surface-mount process depends on a variety of variables, many of them interacting J-STD-005 provides test methods for classification of solder paste based on the use of a variety of testing techniques However, these solder paste classifications not have a direct correlation to identify the type and characteristics of a specific solder paste that is needed in any given SMT assembly process This document has been written as a guide to assess the applicability of a solder paste for a specific process, given the tremendous number of permutations of different materials, atmospheres and process variables currently available Where appropriate, references are given to papers and documents with further information Due to the sheer number of possible interacting factors, specific solder paste selection criteria cannot be given The solder paste selected and the assembly process used will need to form solder connections that meet the requirements of industry standards such as J-STD-001 and/or IPC-A-610 – 18 – BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 B.13 Acceptability of Electronic Assemblies (IPC-HDBK-610) This handbook is a companion reference to IPC-A-610C and IPC-A-610C Amendment and was prepared using them The amendment provides additional criteria and clarification statements The amendment is included with this handbook following Appendix C and can be downloaded free of charge from the IPC website at the following link: http://www.ipc.org/TOC/IPC-HDBK-610-w-Amend-1.pdf The intent of this handbook is to explain the technical rationale for selected acceptability, process indicator and defect criteria and to provide information regarding assembly technology Additional information is provided to give a broader understanding of the process considerations needed for the production of acceptable hardware B.14 Guidelines for Design, Selection and Application of Conformal Coatings (IPC-HDBK-830) Conformal coatings are used in conjunction with printed circuit assemblies (PCAs) The designer and the users of conformal coatings for electronics applications should be aware of the properties of various types of conformal coatings and their interactions with PCAs to protect the PCAs in the end-use environment for the design-life of the PCA (or beyond) This document has been written to assist the designers and users of conformal coatings in understanding the characteristics of various coating types, as well as the factors that can modify those properties when the coatings are applied Understanding and accounting for these materials can ensure the reliability and function of electronics The purpose of this handbook is to assist the individuals who either make choices regarding conformal coating or who work in coating operations This handbook represents the compiled knowledge and experience of the IPC Conformal Coating Handbook Task Group It is not enough to understand the properties of the various conformal coatings The user needs to understand what is to be achieved by applying the conformal coating and how to verify that the desired results have been realized B.15 Solder mask Handbook (IPC-HDBK-840) Solder masks are permanent protective coatings that perform a number of functions during the fabrication, assembly and end use of printed circuits One of the main purposes of solder mask is to protect the circuitry from interacting with solder during the assembly process A solder mask’s job isn’t solely restricted to the solder operation however, as it also helps to protect the laminate, holes and traces from collecting contaminants and from degrading during the service life of the circuit It also acts as an insulator of known dielectric property between components and traces The main requirements of the solder mask (as a material qualification) are tested within the IPC-SM-840 However, increasing technical diversification created further testing needs Not every technical requirement is relevant for every application and thus these requirements will not be part of a general material qualification These properties are usually required for specific original equipment manufacturer’s (OEM) approvals This solder mask handbook provides the reader with the background knowledge to make an educated decision if specific properties are required and how to test them It also provides significant educational information about process influences The purpose of this handbook is to provide additional supporting information for IPC-SM-840 regarding solder mask types, processes, characteristics and properties in order to assist with the correct selection and use of the most appropriate material for the intended application It should be read in conjunction with the solder mask manufacturer’s technical information and other solder mask specification documents, which may be relevant, such as those listed in Section of IPC-HDBK-840 BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 – 19 – B.16 Guidelines and Requirements for Electrical Testing of Unpopulated Printed Boards (IPC-9252) This document is presented to assist in selecting the test analyzer, test parameters, test data, and fixturing required to perform electrical test(s) on all unpopulated printed boards without embedded components (i.e., resistors, capacitors, etc.) The users shall determine the test parameters and fixturing requirements to test for continuity (open), isolation (leakage/short), and other special characteristics (i.e., impedance, hipot, capacitance, current carrying capacity, etc.) that will satisfactorily evaluate the critical electrical characteristics of specific printed boards The testing levels listed in this document define some of these parameters Electrical testing verifies that the printed networks on the boards are interconnected according to design requirements Electrical test does not ensure that the board can be assembled or that the board meets all of the customer’s requirements Many physical characteristics of the conductors (dimensional accuracy, solder mask, conductor geometry and nomenclature registration, presence of holes, etc.) can’t be determined by electrical test Other checks should be employed to confirm these characteristics B.17 In-Process DPMO and Estimated Yield for PCAs (IPC-9261A) This document defines standard methodologies for calculating defects per million opportunities (DPMO) metrics related to electronic printed board assembly processes It is intended for use in measuring in-process assembly steps rather than end product determination Calculation of completed item DPMO is addressed in IPC-7912 Additionally, a guide to defect categorization is provided that when used with J-STD-001 and IPC-A-610 can serve as a base for summarizing and reporting in-process defects Note that this document does not dictate the number of assemblies or data points needed to calculate DPMO metrics The purpose of this document is to define consistent methodologies for computation of inprocess DPMO metrics for any defect evaluation stage in the assembly process This objective anticipates the following conditions in defect reporting and analysis • To facilitate process improvement, defects discovered at any stated inspection or test point should be assigned to their appropriate process step • All defects shall be reported at the inspection point they are found, even though one undetected previous defect may have caused the subsequent defects • Regardless of how these defects are assigned, the defect shall be attributed to either a component, placement, termination or assembly defect • The assumption is that each printed board assembly that is inspected will be 100 % inspected for all defects • The assumption of 100 % inspection efficiency is made Care should be taken when comparing processes using manual inspection to those using automated vision inspection • When using a sampling inspection plan, the number of PCAs inspected determines the opportunity count, not the number processed – 20 – BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 B.18 Assembly Soldering Process Guideline for Electronic Components (IPC-9502 PWB) This document describes manufacturing solder process limits that components subjected to IPC-9501, IPC-9503, IPC-9504 and J-STD-020 would survive It does not include optimum conditions for assembly, but rather guides to ensure components are not damaged This document applies to both surface-mount (SM) and through-hole (TH) components that are wave soldered, reflowed or hand soldered This document is intended to complement other industry documents, listed in applicable documents B.19 Users Guide for IPC-TM-650, Method 2.6.27, Thermal Stress, Convection Reflow Assembly Simulation (IPC-9631) The intention of this document is to aid users of IPC-TM-650, Method 2.6.27, Thermal Stress, Convection Reflow Assembly Simulation This test method has been developed because IPC-TM-650, Method 2.6.8, Thermal Stress, Plated-Through Holes (thermal stress by solder float) is no longer considered adequate for simulating the assembly process and stresses that many products now have to support Over many years the assembly process has continued to diverge from wave soldering, with the addition of top, and then bottom, surface-mount devices, large BGA packages where solder joints are hidden, an ever increasing density of devices which increase the thermal mass and thermal stress needed to melt solder, and more recently the switch to higher melt temperature, lead-free solders In summary, adding more and more cycles of the Method 2.6.8 solder float was no longer sufficient to screen out printed boards that would then fail during assembly due to the very different thermal stresses encountered This document was developed by the IPC D-32, Thermal Stress Test Method Subcommittee, that developed IPC-TM-650, Method 2.6.27, with the understanding that the test method will require special equipment and the proper set-up and calibration of that equipment The IPC-TM-650, Method 2.6.27, is intended to establish a relative ability of printed boards, or representative coupons, to survive the thermal excursions associated with assembly and rework in a tin/lead or lead-free application using a convection oven, or alternate equipment with the capability to match the reflow profile of a convection oven The test embraces relative robustness of the copper interconnection and dielectric materials subjected to the strain and resulting stress associated with a standardized thermal profile The purpose is to establish an objective measurement of relative robustness ranking or comparing variables, or establishing minimum reliability requirements for copper interconnections and dielectric material in a printed board The purpose of the test method is to provide the procedure for conditioning and reflowing of the test specimen prior to evaluation for compliance to the applicable performance specification, i.e., IPC-6012, IPC-6013, IPC-6018, etc The primary purpose of this document is to address concerns and considerations related to IPC-TM-650, Method 2.6.27 This document embraces how this test method was intended for use and the rationale behind some of the protocols and requirements This document provides an adjunct document that improves the understanding, application, and the implication of results from using this test method B.20 High Temperature Printed Board Flatness Guideline (IPC-9641) During the surface mount assembly process of an electronic package to a printed board through a reflow temperature profile, the flatness behavior of both the package and printed board are critical for the integrity of solder joint formation and reliability While the deviation of the package from planarity during this process is critical, controlling the printed board flatness is equally important for preventing subsequent assembly-related issues, including open or bridging joints, which ultimately cause product failure Board flatness is largely driven by a change in intrinsic properties through exposure to changes in temperature, with the final flatness state becoming a function of the entire temperature history or reflow profile and support boundary conditions It is also driven by copper symmetry stack-up and metal pattern BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 – 21 – balancing The worst-case deviation of the printed board from flatness may be at room temperature, peak temperature during reflow, or at any temperature in between Therefore, printed board flatness shall be characterized during the entire reflow thermal cycle, and not solely at room temperature at the beginning and end of the process This document aims to provide guidance on methods and procedures for critically evaluating printed board flatness during a simulated temperature reflow cycle The purpose of this test method is to measure the shape and relative change in shape of a local area of interest (e.g., flip-chip ball grid array (FCBGA) land area) of printed boards through a range of temperatures typical during surface-mount and through-hole builds of integrated circuit packages to printed boards The use of shape measurements and relative changes in shape will depend on the specific application and interest of the user performing the measurement This guideline differs from and does not supersede IPC-TM-650, Method 2.4.22, which is used for inspection of bow and/or twist of bare printed boards at room temperature B.21 User Guide for the IPC-TM-650, Method 2.6.25, Conductive Anodic Filament (CAF) Resistance Test (Electrochemical Migration Testing) (IPC9691A) This document is the product of the IPC Electrochemical Migration (ECM) Task Group It was drafted to provide guidance regarding how the IPC-TM-650, Method 2.6.25, Conductive Anodic Filament (CAF) Resistance test can best be used for evaluating the effects of mechanical stress, laminate material fracturing, ionic contamination, moisture content prior to press lamination, and other material processing characteristics on conductive anodic filament (CAF) resistance test method results This CAF test method provides a proven standard for determining the risk of temperature, humidity and bias (THB) failure within rather than on the surface of printed circuit boards (PCBs), typically filament formation along the boundary between the resin and laminate reinforcement B.22 Mechanical Shock Test Guidelines for Solder Joint Reliability (IPC-JEDEC9703) With the growth of electronics and the increased accessibility and portability, drop shock and other mechanical impacts are increasingly a concern This document attempts to improve past mechanical shock test methods, and ties test conditions back to the use-conditions A method is proposed such that regardless of what level (system, board assembly, simplified single component board testing, etc.) of testing is conducted, there should be a correlation back to the use-condition In order to fulfill this goal, additional metrologies are introduced to aid in these correlations Following the requisite introductory sections, the concept of use-conditions is introduced and suggestions are made on how use-condition data may be acquired and applied Next, the testing methods for fully assembled systems are introduced Options for test conditions are discussed and the data that should be collected is outlined Testing of subassemblies and components imitate actual use configurations less than the testing of fully assembled systems However, the next two document sections outline considerations to ensure that testing carried out at these levels remains relevant to the intended use-condition Specific metrics to aid in correlations are outlined in Section The informative annexes that close the document discuss the common considerations of all mechanical shock testing methods These include a sample reporting format for test data, use and application of strain gauges, accelerometers, and high speed photography A section on failure analysis is given Finally, a review of finite element methods that may be applied to mechanical shock analysis is given to aid in more in-depth study of shock problems – 22 – BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 This document establishes mechanical shock test guidelines to assess solder joint reliability of printed circuits The three main categories discussed within are the following: • methods to define mechanical shock use-conditions; • methods to define system level, system board level and component test board level testing that correlate to the use-conditions; • guidance on the use of experimental metrologies for mechanical shock tests B.23 Printed Circuit Assembly Strain Gage Test Guideline (IPC-JEDEC-9704A) This document is meant to be used as a methodology for strain gauge placement and subsequent testing of printed circuit assemblies (PCAs) using strain gauges The method describes specific guidelines for strain gage testing of PCAs during the printed board manufacturing process, including assembly, test, system integration, and other types of operations that may induce board flexure The suggested procedure enables printed board assemblers to conduct strain gauge testing independently, and provides a quantitative method for measuring board flexure, and assessing risk levels The topics covered include: • test setup and equipment requirements; • strain measurement; • report format This document assumes the methodology is being used to test a surface-mount device such as ball grid array (BGA), small outline package (SOP), chip scale (size) package (CSP), and area-array surface-mount (SMT) connectors/sockets In certain cases, the described test approach may be used for non-area-array discrete (SMT) devices such as capacitors or resistors BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 – 23 – Bibliography International Standards IEC 60068 (all parts), IEC 60068-1:2013, Environmental testing Environmental testing – Part 1: General and guidance IEC 60068-2-20, Environmental testing – Part 2-20: Tests – Test T: Test methods for solderability and resistance to soldering heat of devices with leads IEC 60068-2-58:2015, Environmental testing – Part 2-58: Tests – Test Td: Test methods for solderability, resistance to dissolution of metallization and to soldering heat of surface mounting devices (SMD) IEC 61189-1, Test methods for electrical materials, interconnection assemblies – Part 1: General test methods and methodology IEC 61189-5 (all parts), assemblies structures and Test methods for electrical materials, interconnection structures and IEC 61189-5, Test methods for electrical materials, interconnection assemblies – Part 5: Test methods for printed board assemblies structures and IEC 61189-5-1:2016, Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 5-1: General test methods for materials and assemblies – Guidance for printed board assemblies (this document) IEC 61189-5-2:2015, Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 5-2: General test methods for materials and assemblies – Soldering flux for printed board assemblies IEC 61189-5-3:2015, Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 5-3: General test methods for materials and assemblies – Soldering paste for printed board assemblies IEC 61189-5-4:2015, Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 5-4: General test methods for materials and assemblies – Solder alloys and fluxed and non-fluxed solid wire for printed board assemblies IEC 61189-5-5:—, Test methods for electrical materials, interconnection structures and assemblies – Part 5-5: XXX printed boards and other IEC 61189-5-501:—, Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 5-501: General test methods for materials and assemblies – Surface insulation resistance (SIR) testing of solder fluxes IEC 61189-5-502:—, Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 5-502: General test methods for materials and assemblies – SIR testing of assemblies Under consideration – 24 – BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 IEC 61189-5-503:—, Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 5-503: General test methods for materials and assemblies – Conductive Anodic Filaments (CAF) testing of circuit boards IEC 61189-5-504:—, Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 5-504: General test methods for materials and assemblies – Process ionic contamination testing IEC 61189-6 Test methods for electrical materials, interconnection structures and assemblies – Part 6: Test methods for materials used in manufacturing electronic assemblies IEC 61190-1-1, Attachment materials for electronic assembly – Part 1-1: Requirements for soldering fluxes for high-quality interconnections in electronics assembly IEC 61190-1-2, Attachment materials for electronic assembly – Part 1-2: Requirements for solder pastes for high-quality interconnections in electronics assembly IEC 61190-1-3, Attachment materials for electronic assembly – Part 1-3: Requirements for electronic grade solder alloys and fluxed and non-fluxed solid solders for electronic soldering applications IEC 61249-2-7, Materials for printed boards and other interconnecting structures – Part 2-7: Reinforced base materials clad and unclad – Epoxide woven E-glass laminated sheet of defined flammability (vertical burning test), copper-clad IEC 62137:2004, Environmental and endurance testing – Test methods for surface-mount boards of area array type packages FBGA, BGA, FLGA, LGA, SON and QFN ISO 5725-2, Accuracy (trueness and precision) of measurement methods and results – Part 2: Basic method for the determination of repeatability and reproducibility of a standard measurement method ISO 9001, Quality management systems – Requirements ISO 9455-1, Soft soldering fluxes – Test methods – Part 1: Determination of non-volatile matter, gravimetric method ISO 9455-2, Soft soldering fluxes –Test methods – Part 2: Determination of non-volatile matter, ebulliometric method Under consideration BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 – 25 – IPC documents IPC-J-STD-001, Requirements for Soldered Electrical and Electronic Assemblies Training and Certification Program IPC-J-STD-005, Requirements for Soldering Pastes IPC-J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices IPC-JEDEC-9703, IPC-JEDEC-9704A, Mechanical Shock Test Guidelines for Solder Joint Reliability Printed Circuit Assembly Strain Gage Test Guideline IPC-HDBK-001, Handbook and Guide to Supplement J-STD-001 IPC-HDBK-610, Acceptability of Electronic Assemblies IPC-HDBK-830, Guidelines for Design, Selection and Application of Conformal Coatings IPC-HDBK-840, Solder Mask Handbook IPC-A-610, Acceptability of Electronics Assemblies Training and Certification Program IPC-A-610C, Daco Class Electronics Assembly IPC-AC-62A, Aqueous Post Solder Cleaning Handbook IPC-CH-65A, Guidelines for Cleaning of Printed Boards and Assemblies IPC-SM-840, Qualification and Performance Specification of Permanent Solder Mask IPC-TM-650, Test Methods Manual IPC-3406, Guidelines for Electrically Conductive Surface Mount Adhesives IPC-5701, Users Guide for Cleanliness of Unpopulated Printed Boards IPC-5702, Guidelines for OEM’s in Determining Acceptable Levels of Cleanliness of Unpopulated Printed Board IPC-6012, Qualification and Performance Specification for Rigid Printed Boards IPC-6013, Qualification and Performance Specification for Flexible Printed Boards IPC-6018, Qualification and Performance Specification for High Frequency (Microwave) Printed Boards IPC-7912, Calculation of DPMO and Manufacturing Indices for Printed Board Assemblies IPC-9201, Surface Insulation Resistance Handbook IPC-9202, Material and Process Characterisation / Qualification Test Protocol for Assessing Electrochemical Performanc – 26 – BS EN 61189-5-1:2016 IEC 61189-5-1:2016 © IEC 2016 IPC-9203, Users Guide to IPC-9202 and the IPC-B-52 Standard Test Vehicle IPC-9252, Boards Guidelines and Requirements for Electrical Testing of Unpopulated Printed IPC-9261A, IPC-B-52, In-process DPMO and estimated yield for PCAs IPC-9501, PWB Assembly Process Simulation for Evaluation of Electronic Components IPC-9502, PWB Assembly Soldering Process Guideline for Electronic Components IPC-9503, Moisture Sensitivity Classification for Non-IC Components IPC-9504, Assembly Process Simulation for Evaluation of Non IC Components IPC-9631, Users Guide for IPC-TM-650, Method 2.6.27, Thermal Stress, Convection Reflow Assembly Simulation IPC-9641, High Temperature Printed Board Flatness Guideline IPC-9691A, User Guide for the IPC-TM-650, Method 2.6.25, Conductive Anodic Filament (CAF) Resistance Test (Electrochemical Migration Testing) All IPC documents are available from IPC at 3000 Lakeside Drive, Suite 309 S, Bannockburn, IL 60015-1249 Tel 847-615-7100 or from the IPC web site: www.ipc.org _ This page deliberately left blank NO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAW British Standards Institution (BSI) BSI is the national body responsible for preparing British Standards and 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