BS EN 6602-70-1 2:201 BSI Standards Publication Space product assurance — Design rules for printed circuit boards BS EN 6602-70-1 2:201 BRITISH STANDARD National foreword This British Standard is the UK implementation of EN 6602-70-1 2:201 The UK participation in its preparation was entrusted to Technical Committee ACE/68, Space systems and operations A list of organizations represented on this committee can be obtained on request to its secretary This publication does not purport to include all the necessary provisions of a contract Users are responsible for its correct application © The British Standards Institution 201 Published by BSI Standards Limited 201 ISBN 978 580 931 36 ICS 31 80; 49.1 40 Compliance with a British Standard cannot confer immunity from legal obligations This British Standard was published under the authority of the Standards Policy and Strategy Committee on 31 October 201 Amendments /corri genda issued since publication Date Text affected BS EN 6602-70-1 2:201 EN 16602-70-12 EUROPEAN STANDARD NORME EUROPÉENNE EUROPÄISCHE NORM October 2016 ICS 31.180; 49.140 English version Space product assurance - Design rules for printed circuit boards Assurance produit des projets spatiaux - Règles de conception des circuits imprimés Raumfahrtproduktsicherung - Designregeln für Leiterplatten This European Standard was approved by CEN on 22 May 2016 CEN and CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC Management Centre or to any CEN and CENELEC member This European Standard exists in three official versions (English, French, German) A version in any other language made by translation under the responsibility of a CEN and CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the same status as the official versions CEN and CENELEC members are the national standards bodies and national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and United Kingdom CEN-CENELEC Management Centre: Avenue Marnix 17, B-1000 Brussels © 2016 CEN/CENELEC All rights of exploitation in any form and by any means reserved worldwide for CEN national Members and for CENELEC Members Ref No EN 16602-70-12:2016 E BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) Table of contents European foreword Introduction Scope Normative references Terms, definitions and abbreviated terms 3.1 Terms from other standards 3.2 Terms specific to the present standard 3.3 Abbreviated terms 24 Principles 26 4.1 Qualified PCBs 26 4.2 Manufacturing tolerances 26 4.3 Reliability of design 26 Design review and MRR 28 5.1 Overview 28 5.2 Documentation 28 General design and production requirements 30 6.1 Reliability of design 30 6.2 Choice of materials and build-up 30 6.2.1 Overview 30 6.2.2 Material selection 33 6.3 Selection of the PCB manufacturer 33 6.4 Traceability and marking 33 Rigid PCBs 34 7.1 7.2 PCB build-up 34 7.1 General 34 7.1 Copper styles 34 7.1 Dielectric thickness 36 PCB dimension 39 BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) 7.3 7.4 7.5 Thickness of PCB 39 7.3.1 General 39 7.3.2 Polyimide PCB 40 7.3.3 Epoxy PCB 40 7.3.4 Number of copper layers in PCB 40 7.3.5 Aspect ratio of vias 40 Track width and spacing 41 7.4.1 General 41 7.4.2 Manufacturing tolerances for width and spacing 41 7.4.3 External layers 42 7.4.4 Normal pitch tracks on internal layers 43 7.4.5 Fine pitch tracks on internal layers 44 7.4.6 Routing to AAD footprint on internal layers 45 Pad design 46 7.5.1 Non-functional pad removal 46 7.5.2 Pad dimensions 46 7.5.3 Non-circular external pads 48 7.6 Copper planes in rigid PCB 49 7.7 Design considerations for the prevention of sliver and peelable 50 7.8 PCB surface finish 50 7.8.1 Metallization 50 7.8.2 Solder mask 51 Flex PCBs 52 8.1 Overview 52 8.2 Dynamic applications 52 8.3 PCB build-up 52 8.3.1 General 52 8.3.2 Dielectric materials 52 8.3.3 Copper cladding 53 8.3.4 Copper planes in flex PCB 53 8.4 Track design 54 8.5 Through holes 55 8.6 8.5.1 Annular ring 55 8.5.2 Vias and pads 56 8.5.3 Tear drop pad for flex PCB 56 Bending radius 57 8.6.1 Overview 57 BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) 8.6.2 8.7 General 57 Sculptured flex PCB 58 8.7.1 Overview 58 8.7.2 General 58 8.7.3 Copper foil dimensions for build-up 58 8.7.4 Connection finger 59 8.7.5 Through-holes 60 8.7.6 Bending radius 61 Rigid-flex PCBs 62 9.1 Overview 62 9.2 General 62 9.3 Build-up 63 9.4 Cover layer 64 9.5 Interface of rigid part and flexible part 64 9.6 Pads 64 Thermal rules and heat sinks 65 0.1 Overview 65 0.2 General requirements 65 0.3 Specific requirements for external heat sink 65 0.3.1 Overview 65 0.3.2 Construction of the interface between PCB and heat sink 65 0.3.3 Dimensional requirements 66 0.4 Specific requirements for internal heat sink 68 0.4.1 General 68 0.4.2 Cu thickness and type 68 0.4.3 CIC and Molybdenum inserts 69 0.4.4 Dimensional requirements 69 1 HDI PCBs 71 1 Overview 71 1 Justification 71 1 Microvia technology 71 1 Microvias 72 1 4.1 Build-up of microvia layers 72 1 4.2 Design of microvias 74 1 4.3 Pad design for microvia 74 1 4.4 Annular ring for microvias 75 BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) 1 Core PCB for HDI 75 1 5.1 General build-up 75 1 5.2 Annular ring on vias for fine pitch footprint 76 1 5.3 Track width and spacing on external layers 77 1 5.4 Track width and spacing on internal layers for impedance control and routing to AAD 77 1 5.5 Track width and spacing on internal layers for differential pair routing within the footprint of ,0 mm pitch AAD 78 1 5.6 Aspect ratio of vias for footprint of AAD with mm pitch 79 PCBs for high frequency applications 81 2.1 Material selection 81 2.2 Build-up of RF PCB 81 2.3 Embedded film resistors 81 2.4 Thickness of RF PCB 83 2.5 Track width and spacing 83 2.5.1 External layers 83 2.5.2 Internal Layers 84 2.6 Pad design 84 2.6.1 Pad dimensions 84 2.6.2 Non-functional pads 84 2.7 Surface finish 84 2.8 Profiled layers and vias 84 Electrical requirements for PCB design 86 3.1 Overview 86 3.2 General 87 3.3 PCB drying 87 3.4 Electrical characteristics 87 3.5 Floating metal 88 3.6 Current rating 88 3.6.1 Overview 88 3.6.2 Requirements for temperature increment 89 3.6.3 Requirements for the model IPC-21 52 for current rating 89 3.6.4 Amendments to the model from IPC-21 52 90 3.7 Provisions to prevent open circuit failure on critical tracks 91 3.7.1 Overview 91 3.7.2 Routing 92 3.8 Voltage rating 92 BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) 3.8.1 Overview 92 3.8.2 General requirements 92 3.8.3 Spacing on flex and rigid-flex laminate 94 3.8.4 Conformal coating 95 3.9 Double insulation design rules for critical tracks 96 3.9.1 Overview 96 3.9.2 Critical nets 96 3.9.3 Prevention of short circuit 96 3.1 Insulation distance of combined requirements on rigid PCB 01 3.1 Controlled impedance tracks 06 3.1 1 Definitions specific to controlled impedance 06 3.1 General rules 06 3.1 Microstrip and stripline 06 3.1 Line impedance termination for end-to-end configuration 07 3.1 Line impedance termination for multidrop configuration 07 3.1 Digital PCB 08 3.1 2.1 Overview 08 3.1 2.2 Zone management and routing 08 3.1 2.3 Criticality of digital signals 09 3.1 Analog PCB 1 3.1 3.1 Overview 1 3.1 3.2 Criticality of analog signals 1 3.1 3.3 Routing and shielding 1 1 3.1 Mixed analog-digital PCB 1 Design for assembly 1 4.1 Overview 1 4.2 General 1 4.3 Placement requirements 1 4.3.1 Conductive patterns 1 4.3.2 Components 1 4.3.3 Component pads 1 4.3.4 Fan out of SMT pads 1 4.3.5 Fan out of PTH 20 4.4 Specific requirements for fused tin-lead finish 21 4.5 Dimensional requirements for SMT foot print 21 4.5.1 Overview 21 4.5.2 General 22 BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) 4.5.3 Bipolar components 23 4.5.4 SOIC components 24 4.5.5 J-leaded components 25 4.5.6 LCC components 26 4.5.7 Flat pack components 28 4.5.8 AAD components 29 Design of test coupon 30 5.1 Design rules for test coupon 30 5.2 Test coupon design 30 Annex A (normative) PCB definition dossier - DRD 33 A.1 A.2 DRD identification 33 A.1 Requirement identification and source document 33 A.1 Purpose and objective 33 Expected response 33 A.2.1 Scope and content 33 A.2.2 Special remarks 39 A.2.3 Example figures 39 Annex B (normative) PCB manufacturing dossier – DRD 44 B.1 B.2 DRD identification 44 B.1 Requirement identification and source document 44 B.1 Purpose and objective 44 Expected response 44 B.2.1 Scope and content 44 B.2.2 Special remarks 45 Annex C (informative) Example of capability list of PID 46 Annex D (informative) Track current rating computation methodology 48 D.1 Introduction of the three models 48 D.1 Overview 48 D.1 Formulae for the three models 49 D.1 Example of current rating 50 D.2 Track current rating computation based on IPC-21 52 50 D.3 Track current rating computation based on CNES/QFT/IN.01 54 D.4 Track current rating computation based on IPC-2221 A 58 Annex E (informative) Example of calculation of PTH pad dimensions 62 Annex F (informative) Prevention of resin starvation and cracks 64 BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) F.1 Prevention of resin cracks 64 F.2 Prevention of resin starvation 64 Annex G (informative) Example of MRR checklist 66 Bibliography 70 Figures Figure 3-1 : Simplified build-up of HDI PCB 20 Figure 3-2: Projected peak-to-peak insulation distance 23 Figure 7-1 : Example of automated fine pitch routing and possible improvements 45 Figure 7-2: Comparison between circular and oblong pads showing annular ring and the centre of the hole misregistered with the centre of the pad 48 Figure 7-3: Grid copper plane with openings 49 Figure 7-4: Example of peelable (left) and sliver (right) 50 Figure 8-1 : Clearance of tracks on flex PCBs 54 Figure 8-2: Tracks on flex, defining termination and bending zones 55 Figure 8-3: Teardrop reinforcement of terminal pads in flex PCB 56 Figure 8-4: Bending radius of assembled flex 57 Figure 8-5: Sculptured flex circuit 58 Figure 8-6: Build-up of sculptured flex circuit 59 Figure 8-7: Connection finger of sculptured flex circuit 60 Figure 8-8 Side view of a component hole for sculptured flex 61 Figure 9-1 Example of a build-up of a layer symmetric rigid-flex 62 Figure 0-1 : Lay out of heat sink and PCB 67 Figure 0-2: drilling holes and slots in internal heat sink 70 Figure 0-3: Angle of intersection of overlapping holes 70 Figure 1 -1 : Build-up of HDI PCBs with staggered (left) and stacked (right) microvia 72 Figure 1 -2: Dimple on a microvia 74 Figure 1 -3: Tear drop pad design 76 Figure 1 -4: Example of routing two differential pair tracks between vias in a footprint of an AAD with ,27 mm pitch 78 Figure 1 -5: Example of routing two differential pair tracks between vias in a footprint of an AAD with mm pitch 80 Figure 3-1 : Cross section of PCB with insulation distances 87 Figure 3-2: Example of double insulation by increasing distance in X,Y and by not superimposing copper on adjacent layers 00 Figure 3-3: Example of double insulation by increasing distances in X,Y and by using two insulators in Z direction 00 Figure 3-4: Edge coupled differential striplines 07 BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) Current [A] vs Cross Sectional Area [m m ^2] 30, 000 25, 000 20, 000 00°C 75°C Current [A] 60°C 45°C 30°C 5, 000 20°C 0°C 5°C 2°C °C 0, 000 5, 000 0, 000 0, 000 0, 00 0, 200 0, 300 0, 400 0, 500 0, 600 0, 700 Cross Sectional area [mm^2] Figure D-16 : IPC-2221A: Current rating based on Figure D-14, range 0-25 A Current [A] vs Cross Sectional Area [m m ^2] 0, 000 9, 000 8, 000 7, 000 00°C 75°C Current [A] 6, 000 60°C 45°C 30°C 5, 000 20°C 0°C 5°C 4, 000 2°C °C 3, 000 2, 000 , 000 0, 000 0, 000 0, 00 0, 200 0, 300 0, 400 0, 500 0, 600 0, 700 Cross Sectional area [mm^2] Figure D-17: IPC-2221A: Current rating based on Figure D-14, range 0-10 A 60 BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) Current [A] vs Cross Sectional Area [m m ^2] 5, 000 4, 000 00°C 75°C 3, 000 60°C Current [A] 45°C 30°C 20°C 0°C 5°C 2, 000 2°C °C , 000 0, 000 0, 000 0, 01 0, 020 0, 030 0, 040 0, 050 Cross Sectional area [mm^2] Figure D-18 : IPC-2221A: Current rating based on Figure D-14, range 0-5 A Current [A] vs Cross Sectional Area [mm^2] 2, 000 Current [A] , 500 0°C 5°C , 000 2°C °C 0, 500 0, 000 0, 000 0, 01 0, 020 0, 030 0, 040 0, 050 Cross Sectional area [mm^2] Figure D-19 : IPC-2221A: Current rating based on Figure D-14, range 0-2 A 61 BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) Annex E (informative) Example of calculation of PTH pad dimensions Two examples of calculations of PTH pad dimensions are shown below These calculations shown in Figure E-1 and Figure E-2 are specific for the PCB manufacturer as specified in the PID and depend on the complexity of the PCB designs Figure E-1 : PCB manufacturing tolerances for registration and annular ring for HDI PCB 62 BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) Figure E-2: PCB manufacturing tolerances for registration and annular ring for rigid-flex sequential PCB 63 BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) Annex F (informative) Prevention of resin starvation and cracks F.1 Prevention of resin cracks Under some conditions, cracks can develop in the laminate resin They are more likely to appear: a In brittle resin types; b In locations with only resin and no reinforcement, such as openings in thick ground planes; c If the resin is mechanically stressed by drilling or routing The cause for the cracking can be mechanical impact or volume shrinkage during curing of the prepreg Once a crack is formed, it can propagate into the laminate The board manufacturing process can influence the formation of cracks Design precautions to reduce the risk of crack formation include the following measures: a Avoid large volumes of resin without prepreg reinforcement NOTE b Avoid low pressure areas due to opposite openings in superimposed copper layers c Keep non-functional pads in planes d Review the selection of material with PCB manufacturer NOTE F.2 Heat sinks often include large volumes of resin that can increase the risk of cracks To avoid this, prepreg inserts in openings can be used Prepreg with filled resin can provide improved mechanical properties Prevention of resin starvation Resin starvation is defined as a condition of insufficient resin to completely wet the glass reinforcement and fill the space between fibres To reduce the risk for resin starvation the following can be done: a 64 Allow sufficient prepreg thickness to fill the space between the copper pattern High profile copper features throughout the PCB layers, such as a pad stack or superimposed tracks, can cause high pressure during lamination and can squeeze resin locally out of the prepreg if insufficient BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) resin is available The PCB manufacturer can implement additional prepreg between 70 µm copper layers compared to 35 µm copper layers Removal of non-functional pads can reduce the risk of resin starvation (see requirement 7.5.1b.2) b Fill open areas in thick copper layers with a non-functional-copper pattern to reduce the amount of resin required for filling This can also help improve the thickness uniformity of the board See IPC-2222A Subclause 9.1.4 which mentions resin starvation and cracks in a discussion of removal of non-functional pads 65 BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) Annex G (informative) Example of MRR checklist The following is an example of “MRR checklist” document Supplier Specification: (To be completed by supplier procurement with additional information where applicable from the responsible design authority ) PCB Manufacturer Project Supplier Article or Reference No: Issue/revision Article title: Issue/revision Supplier purchase order No: purchase order Date Feature Set Is this a new or a recurring design? If recurring please define all changes made to data set since the last purchase or state none If recurring please reference ALL occurrence reports raised against previous procurements of this or state none Is the design fully compliant with ECSS-Q-ST-70-12? If the design is not compliant to ECSS-Q-ST-70-12 please list all deviations Has method and position of identification marking been defined? Printed Circuit Board Manufacturer Declaration: (To be completed by the PCB manufacturer) Supplier work order No: If this is a recurring design please define all changes made to tooling or processing since the last purchase or state none 66 work order date BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) Manufacturer’s PID (Process Identification Document): Approved PID Reference including issue and revision Deviations to the Approved PID List all modifications changes and nonconformances relative to the approved PID or state none Contract Review: Please confirm contract review has taken place and reference controlling procedure(s) used Please list any anomalies or deviations arising from the contract review or state none Design: Have any changes to the provided data been requested following design rule checking (DRC)? Please list all changes and provide references below Reference of requesting e-mail (date, from, to) Reference of supplier’s agreement (date, from, to) Comments Actions arising Have all non-functional pads been kept? Has coupon sample data been included in the data pack? Has IST coupon sample data been included in the data pack? Has the position and quantity of coupon sample been agreed with supplier? Technical Review: (Where there is the risk of deviation to the requirements of ECSS-Q-ST-70-1 or a risk of an identified undesirable artefact occurring this is recorded at the end of this section) Please advise the base laminate and prepreg references to be used in fulfilment of this order Is there an extended lead time in procuring these materials? Has this combination of materials been utilised on supplier’s flight product previously? Is the stack-up of materials symmetrical for each pressing cycle? How many press cycles lamination – drilling cycles will be required in the manufacture of this design? Is the copper weight even on both sides of the laminate? 67 BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) Are the copper weights with the range previously supplied for supplier’s flight products? Are there two plies of glass present between every conductive layer – laminate and prepreg? Where prepreg is intended to be used to backfill vias, is the resin content and board geometry suitable to support this? For flex rigid only, is the process open or closed window? How many flexible laminate layers are included in the design? Risks identified from the technical review Risk Rating (1 Low, High) Risk Parameters requiring control Additional risks: Have any additional risks to the manufacture of this product been identified Additional risk identified Risk Rating (1 Low, High) Risk Parameters requiring control Manufacturer Completing Signature: Please ensure that copies of the PCB construction and a screen dump of the approved panel layout are attached to this MRR before signature Position Print Name; Sign and Date Supplier Technical Authority review: Is the supplier technical authority in agreement with the risks identified and the rating applied by the manufacturer? If no provide details of dis-agreement Have any additional risks been identified by the TA as a result of this review? If yes give details 68 BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) Supplier Technical Authority Recommendations: Recommendation Print Name, Sign and Date Low to intermediate levels of risk - 2, manufacture may continue without project counter-signature Medium levels of risk - 4, risks to be entered in project risk register Project manager responsible countersignature required to confirm acceptance and recording of risk before manufacture may commence High risk 5, continuation against recommendation of supplier technical authority To be subject IRB with inclusion in project risk register Project manager responsible countersignature required to confirm acceptance and recording of risk before manufacture may commence Authorising Signatures: Entity Print Name, Sign and Date Supplier Technical Authority Supplier project manager (medium and high risk only) 69 BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) Bibliography 70 EN reference Reference in text Title EN 16601-00 ECSS-S-ST-00 ECSS system – Description, implementation and general requirements EN 16602-70-28 ECSS-Q-ST-70-28 Space product assurance - Repair and modification of printed circuits board assemblies for space use ASTM-B386-03, 2011 Standard Specification for Molybdenum and Molybdenum Alloy Plate, Sheet, Strip, and Foil IPC-2141, Mar 2004 Design Guide for High Speed Controlled Impedance Circuit Boards IPC-2221A, May 2003 Generic standard on printed board design IPC-2221B, Nov 2012 Generic standard on printed board design IPC-2222A, Dec 2010 Sectional design standard for rigid organic printed boards IPC-2223C, Nov 2011 Sectional design standard for flexible printed boards IPC-2226, Apr 2003 Sectional design standard for high density interconnect boards IPC-2251, Nov 2003 Design guide for the packaging of high speed electronic IPC-2315, Jun 2000 Design guide for high density interconnects (HDI) and microvias IPC-4104, May 1999 Specification for high density interconnect (HDI) and microvias materials IPC-4121, Jan 2000 Guidelines for selecting core constructions for multilayer printed wiring board applications IPC-4202A, Apr 2010 Flexible base dielectrics for use in flexible printed circuitry IPC-4204A, Oct 2013 Flexible metal clad dielectrics for use in fabrication of flexible printed circuitry IPC-7095C, Jan 2013 Design and assembly process implementation for BGAs IPC-7351B, Jun 2010 Land pattern and calculator IPC-CF-152B, Dec 1997 Composite Metallic Material Specification for Printed Wiring Boards BS EN 6602-70-1 2:201 EN 16602-70-12:2016 (E) NOTE IPC-T-50K, 2013 Terms and definitions for Interconnecting and packaging electronic circuits RNC-CNES-Q-ST-70101, version 8, Apr 2009 Spécifications de conception des cartes imprimées CNES/QFT/IN.0113 rev 1, issue June 2000 Intensités admissibles en environnement spatial D Cullen, G O’Brien, Proc APEX 2004 “Implementation of Immersion Silver PCB Surface Finish In Compliance With Underwriters Laboratories” See also Clause for referenced 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