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4/1 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Course contents • Digital design • Combinatorial circuits: without status • Sequential circuits: with status FSMD design: hardwired processors • Language based HW design: VHDL 4/2 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL FSMD design FSMDs • Models • Synthesis techniques 4/3 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL FSMD • FSMD: Finite State Machine with Datapath • FSMD = hardcoded processor Consists of a datapath that performs the computations and a controller which indicates to the datapath which operations have to be carried out on which data The controller always executes the same algorithm: hardcoded • A traditional ASIC consists of multiple interconnected FSMDs 4/4 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL FSMD Datapath Controller Control signals Status signals Data inputs Data outputs Control inputs Control outputs 4/5 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL FSMD design • FSMDs Datapath design Controller design • Models • Synthesis techniques 4/6 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL FSMD design • FSMDs Datapath design Controller design • Models • Synthesis techniques 4/7 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Datapath design • Datapath Temporary storage: registers, register files, FIFO’s, … Functional units: arithmetic and logic units, shifters Connections: busses, multiplexors, tri-state bus drivers 4/8 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Datapath design ∑ = = 2 1i i xsum Task: sum = 0 FOR i = 1 TO 2 sum = sum + x i ENDFOR y = sum Algorithm: Processing Control Datapath construction rules: • each variable and constant corresponds to a register • each operator corresponds to a functional unit • connect outputs of registers to input of functional units; when multiple outputs connect to the same input: MUX or bus with tristate drivers • connect output of functional units to input of registers; when multiple outputs connect to the same input: MUX or bus with tristate drivers 4/9 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Datapath design sum = 0 FOR i = 1 TO 2 sum = sum + x i ENDFOR y = sum Algorithm: Variables: sum Reset Load Clk Register SUM 0 1 2 Wait 100 Add Operators: add x i Connections Add2 010 Output 001 Add1 010 Start=1 y 0 Start Output order: ‘Reset’,’Load’, ’Out’ 210 4/10 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Datapath design Task: count the number of ‘1’s in a word Data = Inport || OCnt = 0 || Mask = 1 WHILE Data <> 0 DO Temp = Data AND Mask OCnt = OCnt + Temp || Data = Data >> 1 ENDWHILE Outport = OCnt Algorithm: All instructions on a single line are executed concurrently: maximum speed, but highest cost Trading-off speed for area is explained in the section on ‘Synthesis techniques’ All hardware components work in parallel. Implementing hardware is hence not writing a sequential software program and implementing this directly in hardware. Above algorithm is a ‘concurrent’ description! [...]... Inport Wait x01x00 s s=1 Load 111x00 FSMD design 5 Comp x00000 VHDL z=0 Temp x00010 Update 010100 4/ 11 Output order: 543 210 1 0 Data 0 4 3R OCnt 2 AND Mask 1 Temp z=1 Out x00001 Add >>1 0 zero Outport © R.Lauwereins Imec 2001 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 4/ 12 Datapath design • Possible optimisations: When the life time of 2 variables is nonoverlapping,... R.Lauwereins Imec 2001 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL Controller design • Modification 3 Often the state diagram contains a part that is repeated several times ⇒ subroutine s0 s0 s1 s3 s2 s4 s3 s4 s1 s5 s6 4/ 28 7 states s2 5 states Only at run-time it is known which will be the next state following the end of a subroutine ⇒ stack © R.Lauwereins Imec 2001 Digital design... 2001 Digital design Combinatorial circuits Sequential circuits FSMD design Datapath design Instruction format 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RF RA2RA1RA0RE2 R L ROE F2 F1 F0 AOESH2SH1SH0 D SOEOOE OE2 Register File Read Port 2 Register ALU Barrel shifter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 RF R L C COE S WA2 WA1 WA0 WE RA2RA1RA0RE1 OE1 VHDL Counter Register File Write Port Register File... less degrees of freedom, since the hardware is fixed 4/ 18 © R.Lauwereins Imec 2001 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 4/ 19 FSMD design • FSMDs Datapath design Controller design • Models • Synthesis techniques © R.Lauwereins Imec 2001 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 4/ 20 Controller design • The controller has been designed... logic VHDL R L Counter C COE State Reg Out- CS put Current logic CO State CI 4/ 23 S1 SS Comparator > = < 0 WA WE Register RA1 RE1 File 23 RA2 RE2 RFOE1 RFOE2 F ALU AOE R L Register ROE Sh D Barrel shifter SOE OOE Outport © R.Lauwereins Imec 2001 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 4/ 24 Controller design Modification 1 One-hot State reg CS CI Properties: * simple... Add2 010 Output 001 4/ 25 © R.Lauwereins Imec 2001 Digital design Combinatorial circuits Sequential circuits FSMD design Controller design Modification 2 Next State Logic CS Next State SS CI Next state logic CI MUX VHDL CO State Reg INC Current State Out- CS put logic CO CI 4/ 26 SS SS © R.Lauwereins Imec 2001 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 4/ 27 Controller design... switching network Functional units Result switching network 4/ 13 External output © R.Lauwereins Imec 2001 Digital design Datapath design • Typical datapath: Inport S 1 Combinatorial circuits Sequential circuits FSMD design WA WE R L C RA1 RE1 Counter 0 Register File 23 RA2 RE2 RFOE1 RFOE2 COE R Register L ROE VHDL Comparator > = ALU F < AOE Sh D SOE OOE 4/ 14 Outport Barrel shifter © R.Lauwereins Imec 2001 Digital... Sum=? sum C=1 s1 LA=1 RS=0 LS=1 C=0 4/ 34 Comp C=1 when A1 C=0 C=1 C=? Add 8 7 5 ? © R.Lauwereins Imec 2001 Digital design Combinatorial circuits Sequential circuits Controller design Can the controller be input based? Example: ReadFromExternal(A); || sum := 0; WHILE A 1 sum := sum + A; || ReadFromExternal(A); FSMD design s0 LA=1 RS=1 LS=0 VHDL C=0 LA=0 LS=0 4/ 35 s1 RS=0 LA LA C=1 LA=1 LS=1 Animate... shifter © R.Lauwereins Imec 2001 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 4/ 15 Datapath design • In the datapath of previous slide a few decisions have been taken: Only 1 i.o 2 result busses ⇒ ALU and Barrel shifter cannot be used concurrently Only 2 i.o 4 operand busses ⇒ e.g Compare and ALU work on the same set of data 9 registers with only 2 write ports and... S*=F(S,I) Next State Combinatorial Logic D Q Clk D Clk 4/ 21 Q O=H(S,I) Output Combinatorial Logic Q © R.Lauwereins Imec 2001 Digital design Controller design Redrawn Control Signals (CS) Next State Combinatorial circuits CI Control Input (CI) VHDL Size State Reg: log2n for n states for straightforward and minimum-bit-change; n for n states for one-hot 4/ 22 SS Next state logic Sequential circuits FSMD . RA2WEWA0WA2SCOECL Register File Read Port 1 Register File Write Port Counter 012 345 678910111213 141 51617 181920212223 242 5262728293031 32-bit instruction word For reasons of simplicity, clarity and. the same algorithm: hardcoded • A traditional ASIC consists of multiple interconnected FSMDs 4/ 4 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL FSMD Datapath Controller Control signals Status signals Data inputs Data outputs Control inputs Control outputs 4/ 5 ©. Data AND Mask OCnt = OCnt + Temp; Data = Data >> 1 ENDWHILE Outport = OCnt Output order: 543 210 4/ 12 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Datapath