semiconductor devices physics and technology

Solutions Manual to Accompany SEMICONDUCTOR DEVICES Physics and Technology rd Edition S M SZE Etron Chair Professor College of Electrical and Computer Engineering National Chaio Tung University Hsinchu, Taiwan M K LEE Department of Electrical Engineering National Sun Yat-sen University Kaohsiung, Taiwan John Wiley and Sons, Inc New York Chicester / Weinheim / Brisband / Singapore / Toronto Contents Ch.0 Introduction Ch.1 Energy Bands and Carrier Concentration in Thermal Equilibrium Ch.2 Carrier Transport Phenomena - Ch.3 p-n Junction -18 Ch.4 Bipolar Transistor and Related Devices -35 Ch.5 MOS Capacitor and MOSFET 52 Ch.6 Advanced MOSFET and Related Devices 62 Ch.7 MESFET and Related Devices -68 Ch.8 Microwave Diode, Quantum-Effect and Hot-Electron Devices 76 Ch.9 Light Emitting Diodes and Lasers -81 Ch.10 Photodetectors and Solar Cells -88 Ch.11 Crystal Growth and Epitaxy -96 Ch.12 Film Formation 105 Ch.13 Lithography and Etching -112 Ch.14 Impurity Doping -118 Ch.15 Integrated Devices -126 CHAPTER 1 (a) From Fig 11a, the atom at the center of the cube is surround by four equidistant nearest neighbors that lie at the corners of a tetrahedron Therefore the distance between nearest neighbors in silicon (a = 5.43 Å) is 1/2 [(a/2)2 + ( 2a /2)2]1/2 = 3a /4 = 2.35 Å (b) For the (100) plane, there are two atoms (one central atom and corner atoms each contributing 1/4 of an atom for a total of two atoms as shown in Fig 4a) for an area of a2, therefore we have 2/ a2 = 2/ (5.43 × 10-8)2 = 6.78 × 1014 atoms / cm2 Similarly we have for (110) plane (Fig 4a and Fig 6) (2 + ×1/2 + ×1/4) / 2a = 9.6 × 1015 atoms / cm2, and for (111) plane (Fig 4a and Fig 6) ⎛3⎞ ⎝2⎠ (3 × 1/2 + × 1/6) / 1/2( 2a )( ⎜ ⎟ a ) = ⎛ ⎜ ⎜ ⎝ 3⎞ ⎟a ⎟ ⎠ = 7.83 × 1014 atoms / cm2 The heights at X, Y, and Z point are 4, 4, and (a) For the simple cubic, a unit cell contains 1/8 of a sphere at each of the eight corners for a total of one sphere ∴ Maximum fraction of cell filled = no of sphere × volume of each sphere / unit cell volume = × 4π(a/2)3 / a3 = 52 % (b) For a face-centered cubic, a unit cell contains 1/8 of a sphere at each of the eight corners for a total of one sphere The fcc also contains half a sphere at each of the six faces for a total of three spheres The nearest neighbor distance is 1/2(a ) Therefore the radius of each sphere is 1/4 (a ) ∴ Maximum fraction of cell filled = (1 + 3) {4π[(a/2) / ]3 / 3} / a3 = 74 % (c) For a diamond lattice, a unit cell contains 1/8 of a sphere at each of the eight corners for a total of one sphere, 1/2 of a sphere at each of the six faces for a total of three spheres, and spheres inside the cell The diagonal distance between (1/2, 0, 0) and (1/4, 1/4, 1/4) shown in Fig 9a is 2 ⎛a⎞ ⎛a⎞ ⎛a⎞ ⎜ ⎟ +⎜ ⎟ +⎜ ⎟ ⎝2⎠ ⎝2⎠ ⎝2⎠ = a The radius of the sphere is D/2 = a D= ∴ Maximum fraction of cell filled ⎡ 4π ⎣ = (1 + + 4) ⎢ ⎛a ⎞⎤ 3 ⎟⎥ / a ⎜ ⎝ ⎠⎦ = π / 16 = 34 % This is a relatively low percentage compared to other lattice structures = d2 = d3 = d4 = d d1 d1 + d + d + d = d1 • ( d1 + d + d + d ) = d1 • = d + d1 • d + d1 • d + d1 • d = ∴d2+ d2 cosθ12 + d2cosθ13 + d2cosθ14 = d2 +3 d2 cosθ= ∴ cosθ = θ= cos-1 ( −1 −1 ) = 109.470 Taking the reciprocals of these intercepts we get 1/2, 1/3 and 1/4 three integers having the same ratio are 6, 4, and The smallest The plane is referred to as (643) plane (a) The lattice constant for GaAs is 5.65 Å, and the atomic weights of Ga and As are 69.72 and 74.92 g/mole, respectively There are four gallium atoms and four arsenic atoms per unit cell, therefore 4/a3 = 4/ (5.65 × 10-8)3 = 2.22 × 1022 Ga or As atoms/cm2, Density = (no of atoms/cm3 × atomic weight) / Avogadro constant = 2.22 × 1022(69.72 + 74.92) / 6.02 × 1023 = 5.33 g / cm3 (b) If GaAs is doped with Sn and Sn atoms displace Ga atoms, donors are formed, because Sn has four valence electrons while Ga has only three The resulting semiconductor is n-type Eg (T) = 1.17 – 4.73x10 −4 T for Si (T + 636) ∴ Eg ( 100 K) = 1.163 eV , and Eg (600 K) = 1.032 eV Eg(T) = 1.519 – 5.405x10 −4 T for GaAs (T + 204) ∴Eg( 100 K) = 1.501 eV, and Eg (600 K) = 1.277 eV The density of holes in the valence band is given by integrating the product N(E)[1-F(E)]dE from top of the valence band ( EV taken to be E = 0) to the bottom of the valence band Ebottom: p= ∫ { [ where –F(E) = − / E bottom + e N(E)[1 – F(E)]dE (E − E F )/kT ]} = [1 + e (1) ] ( E − E F ) / kT −1 If EF – E >> kT then – F(E) ~ exp [− (E F − E ) kT ] (2) Then from Appendix H and , Eqs and we obtain p = 4π[2mp / h2]3/2 ∫ E bottom E1/2 exp [-(EF – E) / kT ]dE Let x ≣ E / kT , and let Ebottom = − ∞ , Eq becomes p = 4π(2mp / h2)3/2 (kT)3/2 exp [-(EF / kT)] ∫ −∞ where the integral on the right is of the standard form and equals ∴ x1/2exdx π / p = 2[2πmp kT / h2]3/2 exp [-(EF / kT)] By referring to the top of the valence band as EV instead of E = we have, p = 2(2πmp kT / h2)3/2 exp [-(EF – EV) / kT ] (3) or p = NV exp [-(EF –EV) / kT ] NV = (2πmp kT / h2)3 where From Eq 18 NV = 2(2πmp kT / h2)3/2 The effective mass of holes in Si is mp = (NV / 2) 2/3 ( h2 / 2πkT ) ⎛ 2.66 × 1019 × 10 m − ⎞ ⎟ = ⎜ ⎝ ⎠ (6.625 × 10 ) 2π (1.38 × 10 )(300 ) −34 − 23 = 9.4 × 10-31 kg = 1.03 m0 Similarly, we have for GaAs mp = 3.9 × 10-31 kg = 0.43 m0 10 Using Eq 19 ( )ln (N E i = ( E C + EV ) + kT V NC ) = (EC+ EV)/ + (3kT / 4) ln ⎡( m p m n )(6) ⎤ ⎢ ⎣ ⎥ ⎦ (1) At 77 K Ei = (1.16/2) + (3 × 1.38 × 10-23T) / (4 × 1.6 × 10-19) ln(1.0/0.62) = 0.58 + 3.29 × 10-5 T = 0.58 + 2.54 × 10-3 = 0.583 eV At 300 K Ei = (1.12/2) + (3.29 × 10-5)(300) = 0.56 + 0.009 = 0.569 eV At 373 K Ei = (1.09/2) + (3.29 × 10-5)(373) = 0.545 + 0.012 = 0.557 eV Because the second term on the right-hand side of the Eq.1 is much smaller compared to the first term, over the above temperature range, it is reasonable to assume that Ei is in the center of the forbidden gap ∫ (E − E ) E − E E−E e ∫ E top 11 KE = C EC E top EC C C e − ( E − E F )/kT dE − ( E − E F ) / kT dE x ≡ ( E − EC ) ∫ = kT ∫ ∞ ∞ x e − x dx x e − x dx = ⎛5⎞ Γ⎜ ⎟ 1.5 × 0.5 × π = kT ⎝ ⎠ = kT ⎛3⎞ 0.5 π Γ⎜ ⎟ 2⎠ ⎝ kT 12 (a) p = mv = 9.109 × 10-31 ×105 = 9.109 × 10-26 kg–m/s λ = (b) λ n = 6.626 × 10 −34 h = 7.27 × 10-9 m = 72.7 Å = − 26 p 9.109 × 10 m0 × 72.7 = 1154 Å λ = 0.063 mp 13 From Fig 22 when ni = 1015 cm-3, the corresponding temperature is 1000 / T = 1.8 So that T = 1000/1.8 = 555 K or 282 ℃ 14 From Ec – EF = kT ln [NC / (ND – NA)] which can be rewritten as ND – NA = NC exp [–(EC – EF) / kT ] Then ND – NA = 2.86 × 1019 exp(–0.20 / 0.0259) = 1.26 × 1016 cm-3 or ND= 1.26 × 1016 + NA = 2.26 × 1016 cm-3 A compensated semiconductor can be fabricated to provide a specific Fermi energy level 15 From Fig 28a we can draw the following energy-band diagrams: AT 77K - Ec(0.59eV) EF(0.53) ·- ·- ·- ·- ·- · -· - ·- · - · Ej(O) Ev(- 0.59) AT 300K Ec(0.56 eV ) EF(0.38) Ej (0 ) ;·I - - - - - - Ev(-O.SS) AT 600K -·-·- 16 Ec(0.50 eV) - ·- ·- ·- ·- ·-·- · EF: Ej(O) - - - - - - - - - Ev(-0.50) (a) The ionization energy for boron in Si is 0.045 eV impurities are ionized Thus pp = NA = 1015 cm-3 np = 11?I nA = (9.65 x At 300 K, all boron 109i I 1015 = 9.3 x 104 cm-3 The Fe1 i level measured from the top of the valence band is given by: m Ep - Ev = kTln(NvfND) = 0.0259 ln (2.66 x 1019 I 10 15) = 0.26 eV (b) The boron atoms compensate the arsenic atoins; we have PP = NA - ND= x 1016 - 2.9 x 10 16 = 1015 cm-3 Since pP is the same as given in (a), the values for np and Ep are the same as in (a) However, the mobilities and resistivities for these two samples are different 17 Since ND >> n;, we can approximate no = ND and Po = n? I no= 9.3 x 10 19 I 1017 = 9.3 From no = n;exp E F ( x 102 cm- -E) kT i , we have Ep - E; = kT ln (n 1n;) =0.0259ln(10 11 19.65 x 109)= 0.42eV The resulting flat band diagram is : 0.42eV - 1.12eV - - Ej t -~, 18 ' Ev -:' From Eq 28 n = l /2[Nn - NA +~(ND - NA) +4n/ J =112[ 2.5 x1013 +~(2.5x10 13 ) +4(2.5x1013 / J = 4.04x1013 20 Assuming complete ionization, the Fenni level measm ed from the intrinsic Fenni level is 0.35 eV for 1015 cm-3 , 0.45 eV for 1017 cm-3 , and 0.54 eV for 1019 The number of electrons that are ionized is given by Using the Fenni levels given above, we obtain the number of ionized donors as n = 10 15 cm-3 for ND = 1015 cm-3 n = 0.93 x 10 17 cm-3 for ND = 1017 cm-3 n = 0.27 x 10 19 cm-3 Therefore, the assumption of complete ionization is valid only for the case of 1015 cm-3 21 ND+ = = 1016 + e −( ED − EF ) / kT = 1016 + e −0.135 1016 = 5.33 × 1015 cm-3 1+ 1.145 The neutral donor = 1016 – 5.33 ×1015 cm-3 = 4.67 × 1015 cm-3 O ND 4.76 ∴ The ratio of = = 0.876 + 5.33 ND CHAPTER15 Each U-shape section (refer to the figure) has an area of2500 ~m x ~m = x 104 ~2 Therefore, there are (2500)2/2 x 104 = 312.5 U-shaped section Each section contains long lines with 1248 squares each, comer squares, bottom square, and half squares at the top Therefore the resistance for each section is k:Q I[] (1248 x2 + 4x0.65 +2) = 2500.6 k:Q The maximum resistance is then 312.5 x2500.6 = 7.81 X 108 Q = 781 MQ The area required on the chip is 126 = 4.35 × 103 μm2 = 66 × 66 μm Refer to Fig.4a and using negative photoresist of all levels (a) Ion implantation mask (for p+ implantation and gate oxide) (b) Contact windows (2×10 μm) (c) Metallization mask (using Al to form ohmic contact in the contact window and form the MOS capacitor) Because of the registration errors, an additional μm is incorporated in all critical dimensions 127 ( 0) (b) (c ) 73 If the space between lines is Jlm, then there is Jlm for each tum (i.e., 2xn, for one tum) Assume there are n tmns, from Eq.6, L ~ jl()n2r ~ 1.2 x 10-6n2r, where r can be replaced by x n Then, we can obtain that n is 13 128 (a) Metal 1, (b) contact hole, (c) Metal (a) Metal 1, (b) contact hole, (c) Metal 129 The circuit diagram and device cross-section of a d amped transistor are shown in (a) and (b), respectively SCHOTTKY DIODE BASE (0) COL L ECTOR~ ~-J SCHOTTKY DIODE -o EMITTER B E (b) p- SUBSTRATE OHMIC CONTACT (a) The undoped polysilicon is used for isolation (b) The polysilicon is used as a solid-phase diffusion somce to f01m the extrinsic base region and the base electrode (c) The polysilicon is used as a solid-phase diffusion som ce to fonn the emitter region and the emitter electrode (a) For 30 keV boron, Rp = 100 nm and Mp = 34 nm Assmni.ng that Rp and Mp 130 for boron are the same in Si and SiO2 the peak concentration is given by S 2π ΔR p × 1011 = 2π (34 × 10 ) −7 = 9.4 × 1016 cm −3 The amount of boron ions in the silicon is ⎡ (x − R p )2 ∞ Q S =∫ exp ⎢ − d q ΔR p 2π ΔR p ⎢ ⎣ = ⎛ Rp − d S⎡ ⎢2 − erfc⎜ ⎜ ΔR 2⎢ p ⎝ ⎣ = × 1011 ⎤ ⎥dx ⎥ ⎦ ⎞⎤ ⎟⎥ ⎟⎥ ⎠⎦ ⎡ ⎛ 750 ⎞⎤ ⎟⎥ ⎢2 − erfc⎜ ⎝ × 340 ⎠⎦ ⎣ = 7.88 × 1011 cm − Assume that the implanted boron ions form a negative sheet charge near the Si-SiO2 interface, then ⎛Q ⎞ 1.6 × 10 −19 × (7.88 × 1011 ) = 0.91 V ΔVT = q⎜ ⎟ / C ox = 3.9 × 8.85 × 10 −14 / (25 × 10 − ) ⎝q⎠ (b) For 80 keV arsenic implantation, Rp = 49 nm and Δ Rp = 18 nm The peak arsenic concentration is S 2π ΔR p = 1016 π × (18 × 10 ) 131 −7 = 2.21 × 10 21 cm − Rp =490 A(As) ~ I ' /L 2~p\ I \ARSENIC (UPPER SCALE) I \ \ \ \ \ \ \ \ \ Rp=1000 A (B) 1015~~ ~~l~ ~~c=~~1on=-=c=m==~ = d -!Si0 21 250 A 3000 X(Al - FOR CHANNEL REGION (a) Because (100)-oriented silicon has lower (~ one tenth) interface-trapped charge and a lower fixed oxide charge (b) If the field oxide is too thin, it may not provide a large enough threshold voltage for adequate isolation between neighboring MOSFETs (c) The typical sheet resistance of heavily doped polysilicon gate is 20 to 30 n /0 , which is adequate for MOSFETs with gate lengths larger than Jlm For sh01t er gates, the sheet resistance of polysilicon is too high and will cause 132 large RC delays We can use refractory metals (e.g., Mo) or silicides as the gate material to reduce the sheet resistance to about Ω /□ (d) A self-aligned gate can be obtained by first defining the MOS gate structure, then using the gate electrode as a mask for the source/drain implantation The self-aligned gate can minimize parasitic capacitance caused by the source/drain regions extending underneath the gate electrode (due to diffusion or misalignment) (e) P-glass can be used for insulation between conducting layers, for diffusion and ion implantation masks, and for passivation to protect devices from impurities, moisture, and scratches The lower insulator has a dielectric constant ε1/ε0 = and a thickness d1= 10 nm The upper insulator has a dielectric constant ε2/ε0 = 10 and a thickness d2 = 100 nm Upon application of a positive voltage VG to the external gate, electric field E1 and E2 are established in the d1 and d2 respectively We have, from Gauss’ law, that ε1E1 = ε2E2 +Q and VG = E1d1 + E2d2 where Q is the stored charge on the floating gate From these above two equations, we obtain E= VG Q + d1 + d (ε / ε ) ε + ε (d1 / d ) 133 ⎧ ⎪ ⎪ 10 × 10 J = σE = 10 −7 ⎨ + ⎛4⎞ ⎪10 + 100⎜ ⎟ ⎪ ⎝ 10 ⎠ ⎩ (a) ⎫ ⎪ Q ⎪ ⎬ = 0.2 − 2.26 × 10 Q ⎡ ⎛ 10 ⎞⎤ −14 ⎪ ⎢4 + 10⎜ 100 ⎟⎥ × 8.85 × 10 ⎪ ⎝ ⎠⎦ ⎣ ⎭ If the stored charge does not reduce E1 by a significant amount (i.e., 0.2 >> 2.26×105 ⎥Q⎥, we can write Q = ∫ σE dt ' ≈ 0.2Δt = 0.2 × (0.25 × 10 − ) = × 10 −8 C t ΔVT = (b) Q × 10 −8 = 0.565 V = C2 10 × 8.85 × 10 −14 / 100 × 10 −7 ( )( ) when t → ∞, J → we have Q → 0.2 / 2.26 × 10 ≅ 8.84×10-7 C Then ΔVT = Q 8.84 × 10 −7 = 9.98 V = C2 10 × 8.85 × 10 −14 / 10 −5 ( ) 10 134 + + (o) p- TUB + + + + (b) POLYSILICON GATE + + + + (c) n-TYPE DIFFUSION - - - -_ _ _ _ L + + 135 + + (d) p-TYPE DtFFUSION D + + + + D D D (e ) CONTACT WINDOWS 0 D + + + {f) METALLIZATION 11 The oxide capacitance per unit area is given by and the maximum cunent supplied by the device is I DS z !_ W C (V -V )2 = SJ.Im 3.5x 10- (V - V ) z5mA L J1 ox G T 0.5J111l G T 136 and the maximum allowable wire resistance is 0.1 V/5 mA, or 20Ω Then, the length of the wire must be L≤ R × Area ρ = 20Ω × 10 −8 cm = 0.074 cm 2.7 × 10 −8 Ω − cm or 740 μm This is a long distance compared to most device spacing When driving signals between widely spaced logic blocks however, minimum feature sized lines would not be appropriate 12 137 X p X l ~~TUB ( 0) v-EPITAXY B SiOz (b) -p-TUB I n-TUB ' t ',._. _ _ v (c) ~ J j FIELD OXIDE (d) -RESIST (e) -II p-~ASS , _n _-_ru_e , _ n.- T.1JB : P _ - - - .-II 138 (f ) 13 To solve the short-channel effect of devices 14 The device performance will be degraded from the boron penetration There are methods to reduce this effect: (1) using rapid thermal annealing to reduce the time at high temperatures, consequently reduces the diffusion of boron, (2) using nitrided oxide to suppress the boron penetration, since boron can easily combine with nitrogen and becomes less mobile, (3) making a multi-layer of polysilicon to trap the boron atoms at the interface of each layer 15 Total capacitance of the stacked gate structure is : C= ε1 d1 × ε2 d2 ⎛ ε1 ε ⎞ 25 ⎛ 25 ⎞ ⎜ + ⎟ = × + ⎟ = 2.12 ⎜ 0.5 10 ⎝ 0.5 10 ⎠ ⎝ d1 d ⎠ 3.9 = 2.12 d ∴d = 3.9 =1.84 nm 2.12 16 Disadvantages of LOCOS: (1) high temperature and long oxidation time cause VT shift, (2) bird’s beak, (3) not a planar surface, (4) exhibits oxide thinning effect Advantages of shallow trench isolation: (1) planar surface, (2) no high temperature processing and long oxidation time, (3) no oxide thinning effect, (4) no bird’s beak 17 For isolation between the metal and the substrate 18 GaAs lacks of high-quality insulating film 139 19 (a) A⎞ ⎛ ⎛ L ⎞⎛ RC = ⎜ ρ ⎟ ε ox ⎟ = ⎜10 −5 × d⎠ ⎝ × 0.5 × 10 −8 ⎝ A ⎠⎝ × (1 × 10 −4 )⎤ ⎞⎡ −14 ⎟ ⎢3.9 × 8.85 × 10 × ⎥ 0.5 × 10 − ⎦ ⎠⎣ = 2000 × (69.03 × 10 −14 ) = 1.38 × 10 − s = 1.38 ns (b) For a polysilicon runner L ⎞⎛ A⎞ ⎛ RC = ⎜ Rsquare ⎟⎜ ε ox ⎟ W ⎠⎝ d⎠ ⎝ ⎛ ⎞ = 30⎜ − ⎟ 69.03 × 10 −14 = 2.07 × 10 −7 s ⎝ 10 ⎠ = 207 ns ( ) Therefore the polysilicon runner’s RC time constant is 150 times larger than the aluminum runner 22 When we combine the logic circuits and memory on the chip, we need multiple supply voltages For reliability issue, different oxide thicknesses are needed for different supply voltages 21 (a) C total = hence EOT C Ta O5 3.9 + = 75 25 C nitride + 10 = 17.3 Å (b) EOT = 16.7 Å 140 ... Transistor and Related Devices -35 Ch.5 MOS Capacitor and MOSFET 52 Ch.6 Advanced MOSFET and Related Devices 62 Ch.7 MESFET and Related... 62 Ch.7 MESFET and Related Devices -68 Ch.8 Microwave Diode, Quantum-Effect and Hot-Electron Devices 76 Ch.9 Light Emitting Diodes and Lasers ... 1/3 and 1/4 three integers having the same ratio are 6, 4, and The smallest The plane is referred to as (643) plane (a) The lattice constant for GaAs is 5.65 Å, and the atomic weights of Ga and