2021 8th NAFOSTED Conference on Information and Computer Science (NICS) Design of a High-speed 8-bit Flash ADC using Double-Tail Comparator on 180nm CMOS Process Hong-Hai Thai1, Cong-Kha Pham2, Duc-Hung Le1* The University of Science, Vietnam National University Ho Chi Minh City, Vietnam The University of Electro-Communications, Tokyo, Japan * Email: ldhung@hcmus.edu.vn Abstract— This paper presents a high-speed 8-bit Flash ADC The design, which is considered as a mixed-signal type, includes two main blocks – comparator and encoder The comparator block contains a TIQ comparator, a control circuit, and a proposed architecture of a DoubleTail (DT) comparator The advantage of using the DT comparator is to reduce the half number of comparators which helps reduce the design area The comparator is implemented with custom analog design meanwhile, the encoder block is designed with digital design flow This mixed-signal circuit is designed and simulated on 180nm CMOS technology The 8-bit Flash ADC only employs 128 comparators The applied input clock for testing is 50 MHz with the input voltage ranging from 0.6V to 1.8V Comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports LSB bits of the binary code The MSB bit is decided by only one DT comparator Keywords— Flash ADC, Double-Tail, comparator, encoder, CMOS 180nm I INTRODUCTION Designing ADCs (Analog-to-Digital Converter) has always been a topic that never gets old in electrical engineering due to the numerous applications provided by ADCs The main function of ADCs is to convert analog signal, which is continuous-time and infinite, to digital signal, which varies discretely concerning time There are main steps that present the progress of signal conversion in an ADC, which are – Sampling: To sample the analog input signal at fixed value – Quantizing: To convert an infinite, continuous-time (analog) value to finite, discrete-time (digital) value This means quantizing will decide the binary level that appears to be nearest with the sampled input value – Encoding: To convert that level of signal to binary code, or digital value To evaluate how well an ADC can operate, two concepts should be focused on Those are – Sampling rate, which regards how fast can an ADC convert analog to digital – and – Bit resolution, presents how much precision of an ADC conversion [1] There are major types of ADCs in use today [1] Depends on the system specifications or requirements that an ADC will be chosen to apply to the design after considering its features and capabilities SAR (Successive Approximation) ADC is the most balance of speed and resolution Delta-sigma ( ) ADC 978-1-6654-1001-4/21/$31.00 ©2021 IEEE provides high dynamic performance and inherent anti-aliasing protection Dual slope ADC calculates by comparing run-up and run-down time (2 slopes) Pipelined ADC is a modern power-saving and very fast ADC type Flash ADC is the fastest type It provides instant conversion without latency The more resolution required, the bigger and more powerhungry the flash ADC becomes - and the sampling rate must be reduced Various applications regarding flash ADC, which are digital oscilloscopes, microwave measurements, fiber optics, RADAR detection, wideband radio, etc [1] According to the above features, flash ADC has always been the most focused of all research of ADC It is the fastest, contains simple parallelism architecture Those advantages make flash ADC compatible and reliable in most systems and designs The heart of every flash ADC is a comparator circuit There are some noteworthy techniques that have been used in designing this type of circuit For instance, the ContinuousTime comparator in [2] adds an auxiliary branch to the conventional comparator to detect the flip point and compensate for the power loss caused by this point’s tail current The Threshold Inverter Quantization (TIQ) technique is applied in [3] to build a three-bit flash ADC This brings a great advantage in power and space efficiency However, this structure is sensitive to process variation and also increases the design time as feature size variation is a long and repetitive task Another remarkable comparator architecture is the Standard Cell, which is introduced in [4] This research states that basic gates can be used as comparators instead of using power-hungry analog comparators Also, the threshold voltage is internal to the comparator which avoids the use of a resistor ladder On the other hand, the architecture relies less on linear circuits and that migrates the design to the digital domain The proposed flash ADC in this paper comprises two significant parts – Comparator block and Encoder block The Comparator block compares and converts the analog input into thermometer code As mentioned above, there are various types of comparators whose function differs from each other, regarding specifications or design requirements This design applies a Double-Tail comparator architecture which was presented in [5] The target is to reduce half the number of comparators compared to conventional flash ADC The presented design generates the Most Significant Bit (MSB) with a switched reference voltage [5] With just a single comparator, the MSB is decided to depend on the input signal 329 2021 8th NAFOSTED Conference on Information and Computer Science (NICS) To help saving power and make the design less complex, this architecture also implements Threshold Inverter Quantization (TIQ) technique [5] The Encoder block inputs thermometer code, which is sent from the Comparator block, and converts it to digital value as an output signal The block processes in a way that thermometer code becomes Gray code and then Binary code Both blocks will be designed on 180nm CMOS technology This paper includes four main sections The first is this introduction section, which has given some overview regarding the design Section discusses details of every main component that appears in this 8-bit flash ADC After that, simulation results are presented in Section to prove whether the design works fine or not Finally, some evaluation and comments are delivered as conclusions in Section Fig Proposed architecture of N-bit flash ADC presents an example schematic view of this work’s proposed 8-bit flash ADC (referencing the design mentioned in [5]), which contains TIQ Comparator, Control Circuit, a 7bit Conventional Flash ADC, and only one comparator for deciding MSB Fig II DESIGN AND IMPLEMENTATION The overview block diagram of this 8-bit flash ADC is presented in Fig There are two main blocks – Comparator block and Encoder The MSB of the binary output, which is Q[7], is decided right after the analog input VIN passes through the Comparator block The remaining output bits, which are Q[6:0], are decided by the thermometer code T[127:1] that is generated by Comparator block then goes through the Thermo-Gray-Binary EncodWer Fig Block diagram of this 8-bit flash ADC A Comparator block In a flash ADC, the most significant part is the comparator Requirements should be met regarding power and resourcesaving but must make sure the ADC works with high speed After researching various types of comparator architecture, this paper decided to follow the comparator structure presented in [5] A general view of a full N-bit flash ADC was suggested in Fig As we can see, the leverage given by this architecture is saving resources by reducing half the number of comparators For instance, conventional N-bit flash ADC requires − comparators However, the below structure only needs of that This means an 8-bit flash ADC can be deployed with just 128 (2 ) instead of 255 comparators as usual We will take a closer look at the structure to get to know how this reduction is doable Fig Detail structure of this work’s proposed 8-bit flash ADC 1) TIQ comparator The TIQ comparator decides reference voltage for the (N1)-bit flash ADC It outputs one of two values VDD or GND (+Vref or -Vref) and sends that to Control Circuit The structure comprises stages of inverters connected in series as shown in Fig The first inverter (or a single-input NAND gate) quantizes analog input (I_VIN) based on varying threshold voltage that is decided by the W/L ratio of PMOS and NMOS transistors The two following inverters are used for increasing the gain as well as to prevent unbalanced propagation delay Here are the transistor dimensions: Lp = Ln = μm Wp = 19.4 μm; Wn = μm 330 2021 8th NAFOSTED Conference on Information and Computer Science (NICS) Fig TIQ comparator 2) Control circuit The Control circuit, as shown in Fig 5, provides an autoswitched reference voltage to the resistors ladder based on the input signal [5], which is generated by the TIQ comparator The I_VCTRL input is generated from the above TIQ comparator output, which means this input serves only two voltage values – HIGH (VDD) and LOW (GND) The O_VK input is considered as mid-point voltage, which is ) ( ) ( , this voltage can be achieved in different ways In this paper, we pick a simple solution – resistors divider between VDD and GND If I_VIN is lower than O_VK, I_VCTRL will be LOW and it will turn the two PMOS (M1 and M3) on O_VOUT1 charges up to VDD = Vin(max) = 1.8 V and O_VOUT2 charges up to O_VK On the contrary, when I_VIN is higher than O_VK, I_VCTRL will be HIGH and it will turn the two NMOS (M2 and M4) on This makes O_VOUT1 equal to O_VK and O_VOUT2 equal to Vin(min) = 0.6V The transistor sizes are listed below: Inverter pairs: Lp = Ln = μm; Wp = Wn = 50 μm L12 = μm, W12 = 5.26 μm; L14 = μm, W14 = 12 μm performing at high speed Therefore, this paper decides to use the Double-Tail comparator architecture that was suggested in [6] due to its great advantages The proposed Double-Tail (DT) comparator is separated into two stages – first, as shown in Fig 6, is the input stage and second, as described in Fig 7, is the output stage There are a few notes about transistors in the design for a better understanding of function Mc1 and Mc2 are controlling transistors, Msw1 and Msw2 are transistors that act as switches, we will get to know how they operate later M1, M2 are the input transistors, M7, M9, and M8, M10 form the back-to-back inverters which will decide the outputs MR1 and MR2 are for separating stages and discharging output nodes to GND This helps to save a lot of power The transistor sizes in sum are: All the Lengths (L) are μm W1,2 = Wsw1,2 = μm Wc1,2 = WR1,2 = W3,4 = μm Wtail1 = 10 μm; Wtail2 = μm L = μm; W = 50 μm for input signal balancing transistors (Other widths are μm for nMOS and μm for pMOS) Fig Input stage of the proposed DT comparator Fig Control circuit load, which presents the series combination The 100 of the resistors [5], is applied between the two outputs It makes the decided reference voltages vary in an unwanted way For example, the expecting output value is between 1.2 V and 1.8 V but with the load, the value is about 1.23 V to 1.78 V and would affect the comparison step Therefore, the M12 and M14 transistors have come to the rescue as they are used for signal improvement and balance 3) Double-Tail (DT) comparator There are various types of comparator circuits to choose to deploy in the Comparator block As we know, a good flash ADC requires consuming low power, optimizing in area, and Fig Output stage of the proposed DT comparator In the beginning, when the clock input I_CLK is LOW (we can call this the reset phase), both Mtail1 and Mtail2 are OFF, M3 and M4 charges the FP and FN nodes to VDD which makes MR1 and MR2 pull both outputs O_OUTP and O_OUTN to GND In the decision-making phase, as I_CLK is HIGH, both Mtail1 and Mtail2 are ON, M3 and M4 are OFF and the FP, FN nodes begin to drop These nodes control MR1 and MR2 to decide output voltages Suppose that the plus input I_INP is greater than the minus input I_INN (VINP > VINN), M2 conducts at a faster rate compared to M1 Therefore, FN reaches V 331 2021 8th NAFOSTED Conference on Information and Computer Science (NICS) before FP At the time FN drops, it turns Mc1 ON, to pull FP back to VDD, and Msw1 OFF, to stop FP from falling to zero And that is how the design reserves power and reduces the pull-up time of those nodes After FP and FN are decided clearly, they control the intermediate transistors – MR1 and MR2 As FP maintains at HIGH level, MR1 conducts and pulls O_OUTN down to GND This leads to M8 opening and pulling O_OUTP up to VDD Outputs are decided as O_OUTP = 1, O_OUTN = because of the input condition VINP > VINN Here are some advantages from the above design that were also listed in [6] The first thing is ∆ , which is defined as the initial output voltage difference The greater this voltage increases, the sooner the outputs are decided And the (1) equation below presents that ∆ rises by exponential growth: ∆ , =4 , ∙ , ∆ , ( ) (1) Secondly, the output latching delay, (since ∆ until the difference between two outputs are VDD/2), is reduced thanks to the effective transconductance’s increment ( , ), as described in the (2) equation: = , , ∙ ln / ∆ Fig Encoder block (2) III SIMULATION RESULTS Finally, as mentioned before, the power consumed in this architecture is cut down to the least wherever possible Regarding the design issues [6], especially the size of transistors, there are a few notes that should be considered The control transistors (Mc1 and Mc2) must turn on as fast as possible before the regeneration begins This can be achieved by using low-threshold pMOS devices Regarding the nMOS switches (Msw1 and Msw2), we should apply large-size transistors to reduce the effect of voltage headroom limitation The mismatch issue in this design includes threshold voltage mismatch and current factor mismatch Those depend on the ratio of the controlling transistor sizes to the input transistor sizes (Wc1,2/W1,2) This is because of the significant role of the input transistors as they amplify the input differential voltage (VINP – VINN) so that they are usually be deployed in great size, which helps neglect the mismatch of the two controlling transistors B Encoder block The Encoder block is designed in a digital way This block inputs thermometer code, which was previously generated by the Comparator block, and converts it to Gray code before translating into Binary code as final output Fig presents the structure of the Encoder block In this structure, the 127 input bits are named as T[1:127], which represent the thermometer code After passing through multiple NOT, AND, OR logic gates in parallel, the Gray code is generated into a 7-bit signal that is G[0:6] Then with XOR gates deployment, we get the 7-bit Binary code as the final result Fig also proves that each bit of thermometer code can affect only one bit of Gray code This helps a lot in reducing the ability of noise appearance in signal and improving digital output’s accuracy The proposed 8-bit flash ADC architecture is designed by using 180 nm CMOS technology Each minor block should be tested separately before connecting it with other blocks This helps to evaluate and to adjust the specifications of every block in a simple way The input range will be varied from 0.6 VDC to 1.8 VDC The reason it does not start from zero is because of the threshold voltage of transistors on 180nm CMOS technology The 50 MHz square wave clock (I_CLK) will be applied throughout the whole design A Comparator block The TIQ comparator is simulated in DC analysis as the input signal (I_VIN) ranges from 0.6 VDC to 1.8 VDC The output (O_VOUT) results in Fig By adjusting the transistor sizes, the threshold voltage will be decided expectedly The ideal requirement is that the output voltage meets the input at half of the input voltage range, which is 1.2 V Fig TIQ comparator simulation The control circuit uses two similar pairs of inverters Therefore, the threshold level of those inverters must be 332 2021 8th NAFOSTED Conference on Information and Computer Science (NICS) assured as we did previously with the TIQ comparator After connecting them, a 100 resistive load will be added in the presence of Double-Tail comparators, which will be deployed later in the whole system The load narrows the output reference voltages, so additional M12 and M14 devices are added up to pull that range back to normal, as shown in Fig 10 As we can see, the input I_VIN varies from to 1.8 VDC and the output I_VCTRL of the previous TIQ comparator flips at mid-point 1.2 V from 1.8 V down to VDC Therefore, when I_VIN is lower than 1.2 VDC, the [+Vref;-Vref] is [0.6;1.2] volts When I_VIN is higher than 1.2 VDC, the [+Vref;-Vref] is [1.2;1.8] volts Fig 12 Comparator block The simulation results of the whole block are displayed in when the input voltage runs from 0.6 to 1.2 V In this case, the MSB bit (O_B) stays LOW as described by the top green signal In Fig 14, when the input ranges from 1.2 to 1.8 V, the MSB bit is now pulled up to HIGH level Both figures express the same thermometer code result (O_T) as it varies from 127 bits of zero to 127 bits of one Fig 13 Fig 10 Control circuit simulation There is plenty of way for testing the Double-Tail comparator performance In this paper, we apply the two inputs with a small difference in voltage value The plus input (I_INP) is 1.01 V and the minus input (I_INN) is 1.00 V The clock (CLK) frequency is 50 MHz We will observe signals in clock cycles, which is 80 ns, to evaluate the design’s stability The simulation result is shown in Fig 11 Fig 13 Thermometer bits with I_VIN from 0.6 to 1.2V Fig 11 DT comparator simulation The plus output (O_OUTP) is gradually stable after every clock cycle and stays at HIGH level (1.8 V), as we can see at M0, M1, and M2 points On the contrary, the minus output (O_OUTN) stays at LOW voltage (0 V) as it should be With such a close gap between the two differential inputs and the result is acceptable This means the outputs will be decided even earlier and better in other cases when the gap is wider The entire Comparator block is shown in Fig 12 It comprises the above parts (1 TIQ comparator, control circuit, DT comparator for MSB decision O_B, 127 DT comparators for 127-bit thermometer code O_T) Fig 14 Thermometer bits with I_VIN from 1.2 to 1.8V B Encoder block Encoder block is designed in digital method An RTL design is written in Verilog HDL and then simulated, synthesized with Synopsys’s tools The simulation result is presented in Fig 15 As you can see, the 127-bit I_THERMO input is the thermometer code, and it runs from 127 bits to 127 bits Those values are converted to Gray code The final result is exported as 7-bit O_BINARY output, and it ranges from to 127 as expected Each time the clock input I_CLK 333 2021 8th NAFOSTED Conference on Information and Computer Science (NICS) TABLE I SUMMARY OF THE 8-BIT FLASH ADC USING DOUBLE-TAIL COMPARATOR falls from HIGH to LOW (negative edge), the binary output is determined Specifications Power supply Input clock Input voltage Resolution Number of comparators Process Fig 15 Encoder block simulation Value 1.8V 50 MHz 0.6V to 1.8V 8-bit 128 180nm CMOS IV CONCLUSION C Flash ADC (full design) The simulation results of the whole system are shown in Fig 16 and Fig 17 This can be achieved when we connect the two above blocks (Comparator and Encoder) together The inputs condition is the same as what we have served the Comparator block For Fig 16, the MSB bit O_B remains LOW since the input voltage is below the mid-point voltage (1.2 V) On the other hand, when the input voltage is greater than 1.2 V, O_B turns to HIGH in Fig 17 This paper has presented a whole design of a high-speed 8-bit flash ADC with the Double-Tail comparator as the key component The complete 8-bit flash ADC is successfully designed and simulated on 180nm CMOS process The input conditions that are applied for testing to gain the above simulation results are – the input voltage range of I_VIN is [0.6 V; 1.8 V] – the input clock signal I_CLK is 50 MHz square wave The advantage of this design is to reduce the half number of comparators used which has helped a lot in reducing the design area Another point that has been proved is that the encoder block is implemented in a decent way when each bit of the thermometer code can affect only one resulting bit to restrict errors to the least V REFERENCES Fig 16 Output O_B with I_VIN from 0.6 to 1.2V Fig 17 Output O_B with I_VIN from 1.2 to 1.8V The summary specifications of this high-speed 8-bit flash ADC is shown in Table I [1] Grant Maloy Smith, “Types of A/D Converters – The Ultimate Guide”, Jul 2021 [online] [2] Wang, Hongyi, et al., “A Low-power Continuous-time Comparator with Enhanced Bias Current at the Flip Point”, The 11th IEEE, International Conference on ASIC (ASICON), pp 1-4 IEEE, 2015 [3] Talukder, Al-Ahsan, and Md Shamim Sarker, “A Threebit Threshold Inverter Quantization based CMOS Flash ADC”, The 4th IEEE International Conference on Advances in Electrical Engineering (ICAEE), pp 352356 IEEE, 2017 [4] Mayur, S M., et al., “Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp 600-603 IEEE, 2017 [5] Kumar Sumit, and Nagesh Ch., “Design of a Two-Step Low-Power and High-Speed CMOS Flash ADC Architecture”, The 24th IEEE International Symposium on VLSI Design and Test (VDAT), pp 1-6 IEEE, 2020 [6] Babayan-Mashhadi, Samaneh, and Reza Lotfi “Analysis and Design of a Low-voltage Low-power Double-tail Comparator”, IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, Vol.22, No 2, pp 343-352, 2013 334 ... high- speed 8- bit flash ADC with the Double- Tail comparator as the key component The complete 8- bit flash ADC is successfully designed and simulated on 180 nm CMOS process The input conditions that are applied... contains TIQ Comparator, Control Circuit, a 7bit Conventional Flash ADC, and only one comparator for deciding MSB Fig II DESIGN AND IMPLEMENTATION The overview block diagram of this 8- bit flash. .. Block diagram of this 8- bit flash ADC A Comparator block In a flash ADC, the most significant part is the comparator Requirements should be met regarding power and resourcesaving but must make sure