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ĐẠI HỌC QUỐC GIA TP HỒ CHÍ MINH TRƯỜNG ĐẠI HỌC BÁCH KHOA ◄ KHOA ĐIỆN-ĐIỆN TỬ ► BÁO CÁO THỰC HÀNH LAB CHƯƠNG GVHD: Trương Quang Vinh LỚP: L02 Thành Viên: Hoàng Văn Doanh – 1912858 – Người Thực Hiện Nguyễn Tiến Dũng – 1912959 Võ Minh Duy – 1910099 Huỳnh Khả Giang - 1913184 TP.Hồ Chí Minh, 28 tháng 05 năm 2022 Thí Nghiệm Số 4: THIẾT KẾ MẠCH AOI22 Tên người thực PROJECT: HOÀNG VĂN DOANH_1912858 Tổng Quan Lý Thuyết Giới thiệu sơ đồ mạch lý thuyết Hình 1.2 Sơ đồ mạch lý thuyết cho mạch AOI22 Hình 1.2 Sơ đồ cổng Logic AOI22 2.TRUTH TABLE: Thực thiết kế Schematic: 2.1 Mạch thiết kế cấp CMOS PMOS - Chọn NMOS PMOS để thiết kế mạch AOI22 Hình 2.1 Mô mạch Schematic AOI22 với LP/N=180nm WP/N=2um Hình 2.2 Mơ mạch Schematic AOI22 với LP/N=258nm WP/N=5um Hình 2.3 Mơ mạch Schematic Symbol AOI22 với LP/N=180nm WP/N=5um Hình 2.4 Mơ mạch Schematic Symbol AOI22 với LP/N=258nm WP/N=5um 2.2 Thực mơ Transient để khảo sát dạng sóng tín hiệu ngõ thay đổi ngõ vào thay đổi (có tất 16 trường hợp cần khảo sát ngõ vào thay đổi) trường hợp sau: TH1: LP/N = 180nm, WP/N = 2um Cload = 58 fF Mạch mô phỏng, kiểm tra Cung cấp điện áp vào symbol thiết kế, tạo thành sơ đồ mạch testbench mô - Nguồn cấp cho AOI22là DC: 1.8V - Nguồn xung cho tín hiệu xung vng Hình 2.5 Mạch testbench mơ AOI22 TH1 Hình 2.6 Kết dạng sóng ngõ theo Tran TH2: LP/N = 258nm, WP/N = 5um Cload = 58 fF Mạch mô phỏng, kiểm tra Cung cấp điện áp vào symbol thiết kế, tạo thành sơ đồ mạch testbench mô - Nguồn cấp cho AOI22là DC: 1.8V - Nguồn xung cho tín hiệu xung vng Hình 2.7 Mạch testbench mơ AOI22 TH2 Hình 2.8 Kết dạng sóng ngõ theo Tran Thực đo Cell Rise/Fall Delay Rise/Fall transition cho mạch AOI22 trường hợp trên: TH1: LP/N = 180nm, WP/N = 2um Cload = 58 fF - Thay đổi ngõ vào A: Hình 2.9 Mạch thực đo Cell Rise/Fall Delay Rise/Fall transition AOI22 thay đổi ngõ vào A Hình 2.10 Kết đo Cell Rise/Fall Delay Rise/Fall transition AOI22 Sóng ngõ ra: File netlist: // Generated for: spectre // Generated on: May 28 11:43:02 2022 // Design library name: DoanhHoang_1812858 // Design cell name: AOI22_testbench_A_180 // Design view name: schematic simulator lang=spectre global parameters Vin VIN include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfres_sa include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfmvar include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rtmom include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_disres include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfesd include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_mim include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_fmom include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfres_rpo include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_m include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfmim include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_res include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_bip include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_bip3 include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_dio3 include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfmvar include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rtmom include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_disres include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfesd include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_mim include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_fmom include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfres_rpo include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_m include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfmim include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_res include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_bip include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_bip3 46 include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_dio3 include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_3v include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_na include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_dio include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_dio_m include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfind include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_dio_3m include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_bbmvar include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfres_hri include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_3vna include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_dio_dnw include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_3m include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfjvar 47 include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfmos include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfsbd include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfmvar_33 include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfmos33 include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rffmom include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=stat_noise // Library name: DoanhHoang_1812858 // Cell name: AOI22_3 // View name: schematic subckt AOI22_3 A B C D GND OUT VDD M10 (net25 B VDD VDD) pch l=260.0n w=5u m=1 nf=1 sd=540.0n ad=2.4e-12 \ as=2.4e-12 pd=10.96u ps=10.96u nrd=0.054 nrs=0.054 sa=480.0n \ sb=480.0n sca=0 scb=0 scc=0 M8 (OUT D net25 VDD) pch l=260.0n w=5u m=1 nf=1 sd=540.0n ad=2.4e-12 \ as=2.4e-12 pd=10.96u ps=10.96u nrd=0.054 nrs=0.054 sa=480.0n \ sb=480.0n sca=0 scb=0 scc=0 M1 (OUT C net25 VDD) pch l=260.0n w=5u m=1 nf=1 sd=540.0n ad=2.4e-12 \ as=2.4e-12 pd=10.96u ps=10.96u nrd=0.054 nrs=0.054 sa=480.0n \ sb=480.0n sca=0 scb=0 scc=0 M0 (net25 A VDD VDD) pch l=260.0n w=5u m=1 nf=1 sd=540.0n ad=2.4e-12 \ as=2.4e-12 pd=10.96u ps=10.96u nrd=0.054 nrs=0.054 sa=480.0n \ sb=480.0n sca=0 scb=0 scc=0 48 M9 (net27 D GND GND) nch l=260.0n w=5u m=1 nf=1 sd=540.0n ad=2.4e-12 \ as=2.4e-12 pd=10.96u ps=10.96u nrd=0.054 nrs=0.054 sa=480.0n \ sb=480.0n sca=0 scb=0 scc=0 M7 (OUT C net27 GND) nch l=260.0n w=5u m=1 nf=1 sd=540.0n ad=2.4e-12 \ as=2.4e-12 pd=10.96u ps=10.96u nrd=0.054 nrs=0.054 sa=480.0n \ sb=480.0n sca=0 scb=0 scc=0 M3 (net26 B GND GND) nch l=260.0n w=5u m=1 nf=1 sd=540.0n ad=2.4e-12 \ as=2.4e-12 pd=10.96u ps=10.96u nrd=0.054 nrs=0.054 sa=480.0n \ sb=480.0n sca=0 scb=0 scc=0 M2 (OUT A net26 GND) nch l=260.0n w=5u m=1 nf=1 sd=540.0n ad=2.4e-12 \ as=2.4e-12 pd=10.96u ps=10.96u nrd=0.054 nrs=0.054 sa=480.0n \ sb=480.0n sca=0 scb=0 scc=0 ends AOI22_3 // End of subcircuit definition // Library name: DoanhHoang_1812858 // Cell name: AOI22_testbench_C_258 // View name: schematic I7 (net02 INPUT net04 OUTPUT net9) AOI22_3 V20 (net04 0) vsource dc=Vin type=pulse val0=0 val1=VIN period=30n delay=0 \ rise=10p fall=10p width=15n V21 (INPUT 0) vsource dc=Vin type=pulse val0=0 val1=VIN period=30n delay=0 \ rise=10p fall=10p width=15n V22 (net02 0) vsource dc=Vin type=pulse val0=0 val1=VIN period=30n delay=0 \ rise=10p fall=10p width=15n V4 (net9 0) vsource dc=1.8 type=dc C0 (OUTPUT 0) capacitor c=58f simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 sensfile=" /psf/sens.output" \ 49 checklimitdest=psf tran tran stop=100n write="spectre.ic" writefinal="spectre.fc" \ annotate=status maxiters=5 finalTimeOP info what=oppoint where=rawfile modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile saveOptions options save=allpub - Thay đổi ngõ vào D: Hình 2.23 Mạch thực đo Cell Rise/Fall Delay Rise/Fall transition AOI22 thay đổi ngõ vào D Hình 2.24 Kết đo Cell Rise/Fall Delay Rise/Fall transition AOI22 thay đổi ngõ vào D 50 Sóng ngõ ra: File netlist: // Generated for: spectre // Generated on: May 28 12:46:09 2022 // Design library name: DoanhHoang_1812858 // Design cell name: AOI22_testbench_D_258 // Design view name: schematic simulator lang=spectre global parameters Vin VIN include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfres_sa 51 include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfmvar include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rtmom include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_disres include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfesd include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_mim include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_fmom include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfres_rpo include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_m include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfmim include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_res include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_bip include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_bip3 52 include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_dio3 include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_3v include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_na include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_dio include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_dio_m include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfind include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_dio_3m include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_bbmvar include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfres_hri include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_3vna include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_dio_dnw include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_3m include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfjvar 53 include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfmos include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfsbd include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfmvar_33 include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rfmos33 include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=tt_rffmom include "/home/hoangtrang/Thu_vien_PDK/Full_Flow_Lab_Lib_TSMC180_New/tsmc18/ /models/spectre/cr01 8gpii_v1d0.scs" section=stat_noise // Library name: DoanhHoang_1812858 // Cell name: AOI22_3 // View name: schematic subckt AOI22_3 A B C D GND OUT VDD M10 (net25 B VDD VDD) pch l=260.0n w=5u m=1 nf=1 sd=540.0n ad=2.4e-12 \ as=2.4e-12 pd=10.96u ps=10.96u nrd=0.054 nrs=0.054 sa=480.0n \ sb=480.0n sca=0 scb=0 scc=0 M8 (OUT D net25 VDD) pch l=260.0n w=5u m=1 nf=1 sd=540.0n ad=2.4e-12 \ as=2.4e-12 pd=10.96u ps=10.96u nrd=0.054 nrs=0.054 sa=480.0n \ sb=480.0n sca=0 scb=0 scc=0 M1 (OUT C net25 VDD) pch l=260.0n w=5u m=1 nf=1 sd=540.0n ad=2.4e-12 \ as=2.4e-12 pd=10.96u ps=10.96u nrd=0.054 nrs=0.054 sa=480.0n \ sb=480.0n sca=0 scb=0 scc=0 M0 (net25 A VDD VDD) pch l=260.0n w=5u m=1 nf=1 sd=540.0n ad=2.4e-12 \ as=2.4e-12 pd=10.96u ps=10.96u nrd=0.054 nrs=0.054 sa=480.0n \ sb=480.0n sca=0 scb=0 scc=0 54 M9 (net27 D GND GND) nch l=260.0n w=5u m=1 nf=1 sd=540.0n ad=2.4e-12 \ as=2.4e-12 pd=10.96u ps=10.96u nrd=0.054 nrs=0.054 sa=480.0n \ sb=480.0n sca=0 scb=0 scc=0 M7 (OUT C net27 GND) nch l=260.0n w=5u m=1 nf=1 sd=540.0n ad=2.4e-12 \ as=2.4e-12 pd=10.96u ps=10.96u nrd=0.054 nrs=0.054 sa=480.0n \ sb=480.0n sca=0 scb=0 scc=0 M3 (net26 B GND GND) nch l=260.0n w=5u m=1 nf=1 sd=540.0n ad=2.4e-12 \ as=2.4e-12 pd=10.96u ps=10.96u nrd=0.054 nrs=0.054 sa=480.0n \ sb=480.0n sca=0 scb=0 scc=0 M2 (OUT A net26 GND) nch l=260.0n w=5u m=1 nf=1 sd=540.0n ad=2.4e-12 \ as=2.4e-12 pd=10.96u ps=10.96u nrd=0.054 nrs=0.054 sa=480.0n \ sb=480.0n sca=0 scb=0 scc=0 ends AOI22_3 // End of subcircuit definition // Library name: DoanhHoang_1812858 // Cell name: AOI22_testbench_D_258 // View name: schematic I7 (0 net02 INPUT OUTPUT net9) AOI22_3 V20 (INPUT 0) vsource dc=Vin type=pulse val0=0 val1=VIN period=30n delay=0 \ rise=10p fall=10p width=15n V21 (net02 0) vsource dc=Vin type=pulse val0=0 val1=VIN period=30n delay=0 \ rise=10p fall=10p width=15n V4 (net9 0) vsource dc=1.8 type=dc C0 (OUTPUT 0) capacitor c=58f simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 sensfile=" /psf/sens.output" \ checklimitdest=psf tran tran stop=100n write="spectre.ic" writefinal="spectre.fc" \ 55 annotate=status maxiters=5 finalTimeOP info what=oppoint where=rawfile modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile saveOptions options save=allpub ➢ Nhận xét: có chênh lệch giá trị RiseTime, FallTime, TimeDelay ngõ vào trường hợp Thực thiết kế layout cho mạch: THE STICK DIAGRAM: 56 Hình 3.1 Mạch layout cho thiết kế AOI22 57 Kiểm tra DRC, LVS, trích xuất tụ ký sinh xuất file GDSII cho mạch thiết kế AOI22 Hình 4.1 Kiểm tra DRC cho mạch thiết kế AOI22 58 Hình 4.2 Kiểm tra LVS cho mạch thiết kế Hình 4.3 Xuất File GDSII cho mạch thiết kế Link video thực folder file làm việc: https://drive.google.com/drive/folders/1GE7n0v_m8t55mVvccdiSyxsVC2dTHSfr?usp=sharing 59 Tài liệu tham khảo [1] Yixuan He, Gyunam Jeon, Yong-Bin Kim, “EECE7248 Lab Tutorial: Common-Source Amplifier Schematic”, tutorial_schematic.pdf (northeastern.edu) [2] Trần Hoàng Trang, “Tài liệu thực hành thiết kế vi mạch tương tự”, Đại học Quốc Gia Thành Phố Hồ Chí Minh 2022 [3] Electronics tutorials, “Common Source Amplifier”, Common-Source-Amplifier | AnalogCMOS-Design || Electronics Tutorial (electronics-tutorial.net) 60 ... 2.TRUTH TABLE: Thực thiết kế Schematic: 2.1 Mạch thiết kế cấp CMOS PMOS - Chọn NMOS PMOS để thiết kế mạch AOI22 Hình 2.1 Mơ mạch Schematic AOI22 với LP/N=180nm WP/N=2um Hình 2.2 Mơ mạch Schematic... 2.5 Mạch testbench mơ AOI22 TH1 Hình 2 .6 Kết dạng sóng ngõ theo Tran TH2: LP/N = 258nm, WP/N = 5um Cload = 58 fF Mạch mô phỏng, kiểm tra Cung cấp điện áp vào symbol thiết kế, tạo thành sơ đồ mạch. .. ad=9.6e-13 \ as=9.6e-13 pd=4.96u ps=4.96u nrd=0.135 nrs=0.135 sa=480n sb=480n \ sca=0 scb=0 scc=0 M3 (net 26 B GND GND) nch l=180n w=2u m=1 nf=1 sd=540n ad=9.6e-13 \ as=9.6e-13 pd=4.96u ps=4.96u