Poly(4-vinylphenol) gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors , Ching-Lin Fan , Ming-Chi Shang, Mao-Yuan Hsia, Shea-Jue Wang, Bohr-Ran Huang, and Win-Der Lee Citation: APL Mater 4, 036105 (2016); doi: 10.1063/1.4944748 View online: http://dx.doi.org/10.1063/1.4944748 View Table of Contents: http://aip.scitation.org/toc/apm/4/3 Published by the American Institute of Physics Articles you may be interested in High-mobility polymer gate dielectric pentacene thin film transistors APL Mater 92, (2002); 10.1063/1.1511826 APL MATERIALS 4, 036105 (2016) Poly(4-vinylphenol) gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors Ching-Lin Fan,1,2,a Ming-Chi Shang,2 Mao-Yuan Hsia,2 Shea-Jue Wang,3 Bohr-Ran Huang,1 and Win-Der Lee4 Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei 106, Taiwan Graduate Institute of Electro-Optical Engineering, National Taiwan University of Science and Technology, Taipei 106, Taiwan Institute of Materials Science and Engineering, National Taipei University of Technology, Sec 3, Chung-Hsiao E Rd., Taipei 106, Taiwan Department of Electrical Engineering, Lee-Ming Institute of Technology, 2-2, Lee-Zhuan Rd., New Taipei City 243, Taiwan (Received January 2016; accepted March 2016; published online 24 March 2016) A Microwave-Induction Heating (MIH) scheme is proposed for the poly(4vinylphenol) (PVP) gate insulator cross-linking process to replace the traditional oven heating cross-linking process The cross-linking time is significantly decreased from h to by heating the metal below the PVP layer using microwave irradiation The necessary microwave power was substantially reduced to about 50 W by decreasing the chamber pressure The MIH scheme is a good candidate to replace traditional thermal heating for cross-linking of PVP as the gate insulator for organic thin-film-transistors C 2016 Author(s) All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/) [http://dx.doi.org/10.1063/1.4944748] Organic thin-film transistors (OTFTs) have recently attracted considerable attention because of their low temperature, low-cost fabrication process,1–3 which makes them suitable for large-area, low-cost flexible electronics Polymer gate dielectrics are the most promising candidates for use in OTFTs because of their solution processability and low process temperature.4–11 Among the family of polymer gate dielectrics, poly(4-vinylphenol) (PVP) has been reported most frequently because of its superior device performance.4–6 Klauk et al.12 reported that pentacene TFTs with spin-coated PVP gate dielectric layers exhibited better electrical properties than thermally grown SiO2 gate dielectric layers However, the remaining hydroxyl groups (OH groups) in the PVP dielectric film easily attract water, usually causing degraded device performance.5–8 Therefore, an appropriate cross-linking technique must be required to reduce the OH groups in PVP dielectric films In general, the cross-linking process usually uses an oven to heat the PVP film to reduce the OH groups However, the oven heating process requires a curing temperature (100 ◦C–300 ◦C)4–6 and longer treatment time (1–2 h) Several research groups recently published alternative routes to decrease the cross-linking temperature.13–17 The short curing time and low thermal budget requirement is still an important issue for the PVP film cross-linking process Traditional microwave annealing is known to be effective for heating because of its advantages including rapid heating and low thermal budget.18–20 In previous study,18 the microwave annealing scheme was usually used for semiconductor annealing (e.g., Silicon, IGZO, ZnO, etc.) Because, using microwave irradiation for heating is limited by its selective-heating characteristic that the energy cannot be absorbed by some materials, such as insulators.19 In addition, the high microwave power (500 W–2000 W) reported in these studies was a serious issue a Author to whom correspondence should be addressed Electronic mail: clfan@mail.ntust.edu.tw 2166-532X/2016/4(3)/036105/7 4, 036105-1 © Author(s) 2016 036105-2 Fan et al APL Mater 4, 036105 (2016) In this study, it is the first time that microwave-Induction Heating (MIH) scheme is proposed for the PVP gate insulator cross-linking process to replace the traditional oven heating process As compared to traditional oven heating, the heating time is significantly decreased from h to by using MIH scheme and the used power is reduced to about 50 W Therefore, for the cross-linking process of PVP, the throughput can be reduced by above 50% and the power can be also significantly reduced Thus, it is believed that the proposed MIH scheme will be a low thermal budget process, which is more suitable for flexible devices application in the future We therefore suggest this technology has a great potential to replace the traditional thermal heating for the PVP gate insulator cross-linking process A glass substrate with an indium-tin-oxide (ITO) layer was used as a substrate and as a bottom gate electrode PVP powder was mixed with poly(melamine-coformaldehyde) methylated (PMF), working as a cross-linking agent, in propylene-glycol-monomethyl-ether-acetate (PGMEA) The mixed solution was then spin-coated onto the substrate to form a 600 nm thick insulating layer MIH was subsequently used to cross-link the PVP under 20 mTorr for The microwave power was 50 W PVP was also cross-linked in a vacuum oven at 180 ◦C for h as the control sample A 50-nm-thick pentacene layer was then deposited as a channel layer onto the PVP layer using a thermal evaporator with the substrate temperature maintained at room temperature Gold source/drain contacts were deposited through a shadow mask onto the pentacene channel layer using a thermal evaporator All devices were measured in the final step using a semiconductor parameter analyzer (HP 4145B) FIG (a) Transfer characteristic (VDS = −20 V) and (b) output characteristic of the OTFT with PVP gate insulator cross-linked using the proposed MIH at 50 W for and by vacuum oven at 180 ◦C for h, respectively (W/L = 500 µm/100 µm) 036105-3 Fan et al APL Mater 4, 036105 (2016) 1/2 Figure 1(a) illustrates the ID–VGS and ID –VGS characteristics of the OTFT with PVP gate insulator cross-linked using the MIH scheme at 50 W for and vacuum oven heating at 180 ◦C for h, respectively The device with the PVP cross-linked using MIH presents characteristics comparable to the control sample It is to say that the effect of the PVP cross-linked using the proposed MIH scheme is similar to that produced using traditional oven heating, even though the crosslinking time was significantly decreased from h to Using µsat = (2ID/Cox)(L/W)/(VGS − VT),2 the µsat of the devices with MIH cross-linking PVP gate insulator was 0.44 cm2/V s Moreover, VT of −8.5 V and an acceptable Ion/Ioff of 1.1 × 105 were also acquired The output characteristics in Fig 1(b) show that current crowding did not occur in the linear region, indicating good ohmic contact between the active layer and the S/D electrodes As shown in Fig 2(a), hydroxyl (–OH) groups in PVP layer are known to be preferentially bonded with those in PMF through the curing step, which is called a cross-linking process.7 Therefore, the cross-linking efficiency can be evaluated using Fourier transform infrared (FTIR) to measure the amount of –OH groups The –OH peaks can be observed at around 3200 cm−1–3500 cm−1 The proposed MIH cross-linking scheme can conduct the lowest –OH intensity to confirm that the PVP cross-linking efficiency using MIH is comparable to that produced using the traditional vacuum oven Figure 2(b) illustrates a schematic diagram of the proposed MIH scheme for the PVP cross-linking When the structure shown in the Fig 2(b) is irradiated by microwaves, the waves pass through the PVP gate insulator to irradiate the ITO metal surface The thin ITO metal is heated rapidly by the microwave irradiation The heated ITO metal gate cures the PVP gate insulator resulting in PVP cross-linking (named as, FIG (a) Schematic diagram of cross-linking process and the FTIR spectra of PVP films with the MIH, oven heating and without cross-linking, respectively (b) Schematic diagram of the proposed MIH scheme for the PVP gate insulator cross-linking process And the FTIR measurement of the PVP insulator without the ITO metal below the PVP layer, which is cross-linked with oven heating, MIH, and without cross-linking (intrinsic sample) 036105-4 Fan et al APL Mater 4, 036105 (2016) FIG (a) The transfer characteristics (VDS = −20 V) of OTFT with PVP gate insulator cross-linked using the proposed MIH (50 W) with different pressures (2000, 200, 20 mTorr) for (W/L = 500 µm/100 µm) (b) The transfer characteristics (VDS = −20 V) of OTFT with PVP gate insulator cross-linked using different MIH power (50, 75, and 100 W) with 20 mTorr for (W/L = 500 µm/100 µm) MIH), as shown in Fig 2(b) Figure 2(b) also shows the FTIR measurement of the PVP insulator with cross-linked by microwave irradiated or oven heated without the ITO metal below the PVP insulator The PVP insulator without cross-linking step is also measured by FTIR as the intrinsic sample It shows the PVP insulator can be cross-linked using traditional oven heating However, it was also found that the –OH group peak for the PVP insulator without ITO metal is almost the same as that for the intrinsic sample Note that the cross-linking process cannot be conducted without ITO metal beneath the PVP insulator Figure 3(a) shows the transfer curves of devices with PVP gate insulator cross-linked using the proposed MIH (50 W) with different pressures (2000, 200, 20 mTorr) for It was found that the device degradation characteristics are increased with increased microwave chamber pressure, resulting from increased microwave attenuation Thus, we presume that the MIH efficiency will be significantly decreased, producing inferior cross-linking effect on the PVP gate insulator, resulting in inferior device characteristics Figure 3(b) shows the transfer curves of devices with PVP gate insulator cross-linked using different MIH power (50, 75, 100 W) with 20 mTorr for min, respectively It is found that the device performances were 036105-5 Fan et al APL Mater 4, 036105 (2016) FIG (a) The atomic force microscope (AFM) surface image of cross-linked PVP gate insulator (b) The gate leakage current (IG) of OTFT device with PVP gate insulator cross-linked using the proposed MIH at 50 W for and by vacuum oven at 180 ◦C for h And the interface trap state density (Nit) between the PVP gate insulator and active layer is also presented for 50 W, 75 W, and 100 W, respectively degraded with the increased MIH power The atomic force microscope (AFM) surface image of cross-linked PVP gate insulator is shown in Fig 4(a) We also observed that the roughness of the PVP surface is obviously increased with the increased power, which is 0.287, 0.584, 0.749 nm for the power of 50, 75, 100 W, respectively, and the roughness is 0.327 nm for the sample by oven heating It is observed that the PVP surface seems to be melted when the MIH power exceed 75 W The melting-like PVP surface will result in the obviously increased roughness It means that the thermal energy conducted by MIH is not only to conduct the cross-linking process but also to cause the change in PVP surface morphology Therefore, we presume that the increased PVP surface roughness and the changed surface morphology will cause the degradation of device characteristics In addition, the roughness (0.287 nm) of MIH with 50 W is similar to that of oven heating (0.327 nm) Thus, the MIH power of 50 W will be suitable for PVP cross-linking process without performance degradation in the study Figure 4(b) illustrates the gate leakage current (IG) of OTFT device with PVP gate insulator cross-linked using the proposed MIH at 50 W for and by vacuum oven at 180 ◦C for h, respectively The similar gate leakage current between the both samples can be observed The gate leakage current depends on the vertical electric field (VGS) 036105-6 Fan et al APL Mater 4, 036105 (2016) and the quality of the PVP gate insulator Thus, it should be the factor to evaluate the quality of gate insulator It notes that the MIH cross-linking process did not degrade the PVP insulator performance, as compared to that with oven heating process Besides the gate leakage current, the interface trap state density (Nit) can be another factor to describe the interface status between gate insulator and active layer,21 as shown in Fig 4(b) It is found that the interface trap state density is 8.86 × 1011 cm−2, 2.42 × 1012 cm−2, and 4.48 × 1012 cm−2 for 50 W, 75 W 100 W, respectively It is 9.18 × 1011 cm−2 for the one with oven heating The lowest interface trap state density can be found in device with PVP gate insulator cross-linked by using the proposed MIH at 50 W for It is also showed that the interface trap state density is increased with the increased power, which is the similar trend to the increased surface roughness We presume that the increased surface roughness will cause the increased interface trap density as a result of the increased MIH power In summary, the proposed MIH scheme can be conducted accurately for the PVP gate insulator cross-linking process for OTFT applications under the optimal condition of MIH It is believed that the MIH scheme is a good candidate for the PVP gate insulator cross-linking process due to its rapid heating (5 min) and low power microwave-irradiation (50 W) features The proposed MIH scheme can be conducted accurately for the PVP gate insulator crosslinking process for OTFT applications We find that the annealing time for the proposed MIH and microwave power was substantially reduced to about and 50 W, respectively We suggest that this technology has great potential for the PVP gate insulator cross-linking process The authors would like to acknowledge the financial support of the National Science Council of Taiwan under Contract No NSC 104-2221-E-011-159 and the Taiwan Building Technology Center (TBTC) of National Taiwan University of Science and Technology (NTUST) C L Fan, P C Chiu, and C C Lin, “Low-temperature-deposited SiO2 gate insulator with hydrophobic methyl groups for bottom-contact organic thin-film transistors,” IEEE Electron Device Lett 31, 1485 (2010) C L Fan, Y Z Lin, W D Lee, S J Wang, and C H Huang, “Improved pentacene growth continuity for enhancing the performance of pentacene-based organic thin-film transistors,” Org Electron 13, 2924 (2012) C Y Wei, F Adriyanto, Y J Lin, Y C Li, T J Huang, D W Chou, and Y H Wang, “Pentacene-based thin-film transistors with a solution-process hafnium oxide insulator,” IEEE Electron Device Lett 30, 1039 (2009) S Lee, B Koo, J Shin, E Lee, H Park, and H Kim, “Effects of hydroxyl groups in polymeric dielectrics on organic transistor performance,” Appl Phys Lett 88, 162109 (2006) Y H Noh, S Y Park, S M Seo, and H H Lee, “Root cause of hysteresis in organic thin film transistor with polymer dielectric,” Org Electron 7, 271 (2006) G Gu and M G Kane, “Moisture induced electron traps and hysteresis in pentacene based organic thin-film transistors,” Appl Phys Lett 92, 053305 (2008) T H Kim, C G Han, and C K Song, “Instability of threshold voltage under constant bias stress in pentacene thin film transistors employing polyvinylphenol gate dielectric,” Thin Solid Films 516, 1232 (2008) T Umeda, D Kumaki, and S Tokito, “High air stability of threshold voltage on gate bias stress in pentacene TFTs with a hydroxyl-free and amorphous fluoropolymer as gate insulators,” Org Electron 9, 545 (2008) X Cheng, M Caironi, Y Y Noh, J Wang, C Newman, H Yan, A Facchetti, and H Sirringhaus, “Air stable cross-linked cytop ultrathin gate dielectric for high yield low-voltage top-gate organic field-effect transistors,” Chem Mater 22, 1559 (2010) 10 S H Kim, J Jang, H Jeon, W M Yun, S Nam, and C E Park, “Hysteresis-free pentacene field-effect transistors and inverters containing poly(4-vinyl phenol-co-methyl methacrylate) gate dielectrics,” Appl Phys Lett 92, 183306 (2008) 11 L Jiang, J Zhang, D Gamota, and C G Takoudis, “Organic thin film transistors with novel thermally cross-linked dielectric and printed electrodes on flexible substrates,” Org Electron 11, 959 (2010) 12 H Klauk, M Halik, U Zschieschang, G Schmid, W Radlik, and W Weber, “High-mobility polymer gate dielectric pentacene thin film transistors,” J Appl Phys 92, 5259 (2002) 13 P Liu, Y Wu, Y Li, B S Ong, and S Zhu, “Enabling gate dielectric design for all solution-processed, high-performance, flexible organic thin-film transistors,” J Am Chem Soc 128, 4554 (2006) 14 S Mototani, S Ochiai, X Wang, K Kojima, A Ohashi, and T Mizutani, “Performance of organic field-effect transistors with poly(3-hexylthiophene) as the semiconductor layer and poly(4-vinylphenol) thin film untreated and treated by hexamethyldisilazane as the gate insulator,” Jpn J Appl Phys 47, 496 (2008) 15 J Jang, S H Kim, S Nam, D S Chung, C Yang, W M Yun, C E Park, and J B Koo, “Hysteresis-free organic field-effect transistors and inverters using photocrosslinkable poly(vinyl cinnamate) as a gate dielectric,” Appl Phys Lett 92, 143306 (2008) 16 S De Vusser, J Genoe, and P Heremans, “Influence of transistor parameters on the noise margin of organic digital circuits,” IEEE Electron Device 53, 601 (2006) 17 S Steudel, S De Vusser, K Myny, M Lenes, J Genoe, and P Heremans, “Comparison of organic diode structures regarding high-frequency rectification behavior in radio-frequency identification tags,” J Appl Phys 99, 114519 (2006) 18 H L Hortensius, A Öztürk, P Zeng, E F C Driessen, and T M Klapwijk, “Microwave-induced nonequilibrium temperature in a suspended carbon nanotube,” Appl Phys Lett 100, 223112 (2012) 036105-7 19 Fan et al APL Mater 4, 036105 (2016) L F Teng, P T Liu, Y J Lo, and Y J Lee, “Effects of microwave annealing on electrical enhancement of amorphous oxide semiconductor thin film transistor,” Appl Phys Lett 101, 132901 (2012) 20 C S Fuh, P T Liu, L F Teng, S W Hung, Y J Lee, and H P D Shieh, “Effects of microwave annealing on nitrogenated amorphous in-Ga-Zn-O thin-film transistor for low thermal budget process application,” IEEE Electron Device Lett 34, 1157 (2013) 21 C L Fan, Y Z Lin, and C H Hung, “Combined scheme of UV/ozone and HMDS treatment on a gate insulator for performance improvement of a low-temperature-processed bottom-contact OTFT,” Semicond Sci Technol 26, 045006 (2011)