Electrical properties and interfacial issues of high k/Si MIS capacitors characterized by the thickness of Al2O3 interlayer Xing Wang, Hongxia Liu, Chenxi Fei, Lu Zhao, Shupeng Chen, and Shulong Wang[.]
Electrical properties and interfacial issues of high-k/Si MIS capacitors characterized by the thickness of Al2O3 interlayer Xing Wang, Hongxia Liu, Chenxi Fei, Lu Zhao, Shupeng Chen, and Shulong Wang Citation: AIP Advances 6, 065224 (2016); doi: 10.1063/1.4955001 View online: http://dx.doi.org/10.1063/1.4955001 View Table of Contents: http://aip.scitation.org/toc/adv/6/6 Published by the American Institute of Physics AIP ADVANCES 6, 065224 (2016) Electrical properties and interfacial issues of high-k/ Si MIS capacitors characterized by the thickness of Al2O3 interlayer Xing Wang, Hongxia Liu,a Chenxi Fei, Lu Zhao, Shupeng Chen, and Shulong Wang Key Laboratory for Wide-Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian University, Xi’an 710071, China (Received 26 April 2016; accepted 19 June 2016; published online 24 June 2016) A thin Al2O3 interlayer deposited between La2O3 layer and Si substrate was used to scavenge the interfacial layer (IL) by blocking the out-diffusion of substrate Si Some advantages and disadvantages of this method were discussed in detail Evident IL reduction corroborated by the transmission electron microscopy results suggested the feasibility of this method in IL scavenging Significant improvements in oxygen vacancy and leakage current characteristics were achieved as the thickness of Al2O3 interlayer increase Meanwhile, some disadvantages such as the degradations in interface trap and oxide trapped charge characteristics were also observed C 2016 Author(s) All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/) [http://dx.doi.org/10.1063/1.4955001] I INTRODUCTION Over the past decade, rare earth oxides (e.g., Y2O3, Gd2O3, La2O3) and their alloys have been extensively studied as alternative gate dielectric materials used in high-k/metal gate stacks, which has been applied to the sub-45-nm complementary metal oxide semiconductor (CMOS) technology to replace the conventional SiO2/poly-Si gate structures in order to scale in an equivalent oxide thickness (EOT).1–3 Among the rare earth oxides and their alloys, because of its high k value (k∼27), large band gap (∼5.5 eV), and suitable conduction band offset with silicon (> eV),4,5 La2O3 is considered as one of the most promising alternative for HfO2 which has been used to replace SiO2 as the gate oxide by Intel in its 45 nm technology at a high technological cost of maintaining an interfacial SiOx layer, to achieve a more aggressive downscaling of the EOT.1,6 Furthermore, the Al-incorporated La2O3, which is called lanthanum aluminate (LaxAl1−xOy, LAO), has a nearly high k value (k∼25–27) as La2O3 while providing an immunity against moisture absorption and much high thermal stability than that of pure La2O3 or HfO2.7 Due to the outstanding characteristics for precise thickness control, excellent uniformity and process compatibility to conventional CMOS process, atomic layer deposition (ALD) is being considered as one of the most promising deposition technique to produce high quality La2O3 or LAO gate dielectric films with nanoscale thickness controllability.8 However, ALD is a typically low-temperature deposition method, then the IL which consists of SiOx-like component and La-silicate seems inevitable at the La2O3 or LAO/Si interface because of the affinity for silicon atoms of La2O3, especially after a high-temperature post-deposition annealing (PDA) and post-metallization annealing (PMA).9,10 Recently, it was reported that an Al2O3 interlayer existed between the La-based high-k dielectric layer and Si substrate could blocking the out-diffusion of substrate Si, and to some extent, giving a suppression effect to the formation of the IL.11,12 In this paper, a further investigation was carried out to the Al2O3-interlayer IL scavenging method, and attentions were focused on the interfacial issues and electrical properties of the fabricated MIS a Electronic mail: hxliu@mail.xidian.edu.cn 2158-3226/2016/6(6)/065224/7 6, 065224-1 © Author(s) 2016 065224-2 Wang et al AIP Advances 6, 065224 (2016) capacitors using the ALD deposited nanolaminates with different thickness of Al2O3 interlayer as insulators II EXPERIMENTAL DETAILS La2O3 and Al2O3 films were deposited on p-type Si (100) wafers with resistivity of 3−8 Ω·cm in a Picosun R-200 atomic layer deposition reactor using La(i−PrCp)3 and TMA as the La and Al precursor while O3 was used as the oxidant Prior to deposition of the films, Si substrates were dipped into a diluted HF solution to remove native SiO2 At the deposition temperature of 300 ◦C, steady-state growth rates of La2O3 (∼0.85 Å/cycle) and Al2O3 (∼0.93 Å/cycle) films were achieved by adjusting the processing parameters of the precursors Different thickness (0.5, 1, and 1.5 nm, marked as sample A, B, and C, respectively) of Al2O3 layers were deposited on the diluted HF treated wafers before the deposition of 5-nm La2O3 layer, and then capped with a 2-nm Al2O3 layer to avoid moisture absorption.9 The control sample received ALD La2O3 and Al2O3 capping layer without any interlayer deposition PDA was performed for 60s in N2 ambient at 700 ◦C using rapid thermal annealing (RTA) Cross-sectional high resolution transmission electron microscopy (HRTEM) was performed to measure the film thickness and to observe the microstructure of the fabricated nanolaminates X-ray photoelectron spectroscopy (XPS) was employed to investigate the bonding structures and chemical states of the films MIS capacitors were fabricated by magnetron sputtering Ni/Au (20 nm/160 nm) electrodes on the surface of the samples through a shadow mask (gate area of 7.07×10−4 cm2), and Al was sputtered as the back contact metal, followed by annealing in an 97% N2/3% H2 ambient for 20 at 400 ◦C The electrical properties including capacitance-voltage (C-V ), conductance-voltage (G-V ), and leakage current-voltage (I-V ) characteristics were evaluated using an Agilent B1500A semiconductor parameter analyzer III RESULTS AND DISCUSSION Figure shows the cross-sectional HRTEM images for the PDA treated (a) control sample and (b) sample C with 1.5nm Al2O3 interlayer Compared with Figure 1(a), in which an amorphous IL (∼2.5 nm) between the deposited film and crystalline silicon substrate is observed, a substantially FIG HRTEM images showing the interface with Si substrate for (a) the control sample without any Al2O3 interlayer deposition and (b) sample C with 1.5nm Al2O3 interlayer Dotted lines are guides for the eyes to visualize the borderline between different parts of the film 065224-3 Wang et al AIP Advances 6, 065224 (2016) thinned IL exists at the layer interface in Figure 1(b) This phenomenon gives obvious evidence and validates that the deposited Al2O3 interlayer indeed suppresses the formation of IL during the deposition and RTA process, suggesting the feasibility of this method in IL scavenging The interdiffusion of La2O3 and Al2O3 layers during the RTA treatment makes the layer borderline indistinct, giving an advantage to the application of the fabricated nanolaminates used as gate dielectric by generating LaxAl1−xOy at the layer interface Figure shows the C-V and G-V characteristics of the fabricated MIS capacitors using the annealed stacks with different thickness of Al2O3 interlayer as insulators The capacitors were swept forward (bias from negative to positive) and backward (bias from positive to negative) to check the amount of C-V hysteresis at the frequency of 100 kHz G-V curves were obtained simultaneously with the C-V curves measured with voltage sweeping from positive to negative The flat band voltages (VFB) were extracted by fitting the C-V date using NCSU CVC program taking into account of quantum-mechanical effects.13 It can be found that along with the increase in the thickness of Al2O3 interlayer, both the forward swept and backward swept C-V curves show a VFB shift towards the positive direction, which is an indication of the presence of negative effective oxide charges in the bulk of the gate dielectric with Al2O3 interlayer.14,15 The oxide charges consist of fixed oxide charge Qf , mobile ionic charge Qm, and oxide trapped charge Qot Ruling out the influence of Qf and Qm (generally positive charged), the negative charged Qot was suspected to be responsible for the positive shift of VFB Considering this, charge trapping behavior was investigated through the C-V hysteresis characteristics, assuming the two-dimensional distribution of traps in the vicinity of the interface contributing to the film capacitance In absence of Al2O3 interlayer, the hysteresis width (∆VFB) of the control sample is 68 mV, thus the trapped charge density Not is estimated to be 3.10×1011 cm−2 following the equations:16,17 ∆VFBCox qA ( ) 2 Gac Cox = Cac 1 + ωCac Not = (1) (2) FIG Capacitance-voltage and conductance-voltage characteristics measured at 100 kHz for the fabricated MIS capacitors using the RTA processed nanolaminates with different thickness of Al2O3 interlayer as insulators 065224-4 Wang et al AIP Advances 6, 065224 (2016) FIG Capacitance-voltage characteristics measured at various frequencies for the fabricated MIS capacitors using the RTA processed nanolaminates with different thickness of Al2O3 interlayer as insulators Where Cox is the insulator capacitance, q is the electron charge (1.602×10−19 C), A is the electrode area, ω is the angular frequency, Cac is the measured accumulation capacitance, and Gac is conductance in accumulation region Using the same method, the trapped oxide charge densities of sample A, B, and C can be figured out as 5.09×1011, 7.11×1011, and 1.24×1012 cm−2, respectively As suspected, a considerable increase in the trapped charge density is obtained when the Al2O3 interlayer exists, indicating that the trapped charges introduced by the deposition of Al2O3 interlayer should be one of the causes that lead to the positive shift of VFB With the increase in the thickness of Al2O3 interlayer, the C-V curves show a more and more obvious anomalous hump phenomenon at ∼0.5 V in Figure 2, which was reported be related to weak inversion response.18 Associated with interface traps formation due to the faster capture and emission of carriers, the weak inversion response phenomenon would cause frequency dispersion in the multifrequency C-V curves as shown in Figure Using Hill-Coleman single-frequency approximation,19 the interface trap density (Dit) values for the fabricated MIS capacitors extracted from the peak conductance are shown in Table I For the control sample, the Dit is about 4.01×1011 eV−1 cm−2 However, the Al2O3 interlayer incorporated samples especially sample C, in which the thickest Al2O3 interlayer (1.5 nm) was adopt, the Dit increase evidently to ∼1.95×1012 eV−1 cm−2, indicating the insertion of Al2O3 interlayer bring in extra interface traps for sample A− C compared with the control TABLE I The various parameters for the fabricated MIS capacitors using the RTA processed nanolaminates with different thickness of Al2O3 interlayer as insulators Sample Control sample Sample A Sample B Sample C Thickness of Al2O3 Interlayer (nm) C ox (µF/cm2) ∆VFB (mV) Not (cm−2) Dit (ev−1cm−2) 0.5 1.0 1.5 0.73 0.84 0.87 0.97 68 97 131 204 3.10×1011 5.09×1011 7.11×1011 1.24×1012 4.01×1011 8.45×1011 1.02×1012 1.95×1012 065224-5 Wang et al AIP Advances 6, 065224 (2016) sample, which gives an explanation to the stronger anomalous hump tendency as the thickness of Al2O3 interlayer increases It is reported that the increment of Dit is presumably brought in by an incomplete reaction of the TMA precursor molecules taking place during the first few cycles of the ALD process, in which the functional groups at the silicon surface are not optimal for an adsorption of the TMA precursor molecules, generating structural defects and dangling bonds at the interface,20,21 which would causes significant increase in interface traps Frequency dispersion can also be detected in the accumulation region as shown in Figure M Kouda et al pointed out that this phenomenon is ascribed to the frequency-dependent changes in the dielectric constant caused by oxygen vacancies in the gate stacks.22,23 Different from what was observed in the weak inversion region, frequency dispersion becomes weaker under the accumulation condition as the thickness of Al2O3 interlayer increases, indicating that the introduction of Al2O3 interlayer suppresses oxygen vacancy generation in the stack structures The mechanisms can be explained as follows Having an Al2O3 interlayer, the diffusion of oxygen from La2O3 layer to Si substrate is suppressed, thus fewer oxygen vacancies generate in the stacks, resulting in less frequency dispersion in the accumulation region Interestingly, the decrease of positive charged oxygen vacancies indicates a reduction of the dipole generation in the gate dielectric, which may also give an explanation to the positive shift of VFB.24,25 Figure shows the leakage current density as a function of the applied electrical field A difference in the leakage current levels between the control sample and the Al2O3 interlayer incorporated samples is clearly observed With the existence of an Al2O3 interlayer between the La2O3 layer and Si substrate, 1∼3 orders of magnitude lower than that measured in the control sample with the same applied electrical field is achieved We attribute this decrease of leakage current to the change of band offsets at the nanolaminate/Si interface Al2O3 was reported has high values of conduction band offset (CBO, ∼2.8 eV) and valence band offset (VBO, ∼4.9 eV) with respect to p-type Si substrate, while for La2O3, values of 2.3 eV for the CBO and 2.6 eV for the VBO were determined.26 As a result, the addition of an Al2O3 interlayer contributes to the formation of a higher potential barrier at the fabricated nanolaminate/Si interface than that at the La2O3/Si interface or the La-silicate/Si interface, leading to a dramatically decrease in the leakage current For clarity, the change of VBO was investigated by analysing the energy difference between Al 2p for the deposited nanolaminates and Si 2s for the Si substrate using XPS, with the intensity of the signals normalized to unity for comparison as shown in Figure A clear positive binding energy shift of Al 2p relative to Si 2s can be observed with the increase in the thickness of Al2O3 interlayer, indicating that the VBO increases as the Al2O3 interlayer become thicker,27 which is in consistent with the analyses above FIG Leakage current-voltage characteristics for the fabricated MIS capacitors using the RTA processed nanolaminates with different thickness of Al2O3 interlayer as insulators 065224-6 Wang et al AIP Advances 6, 065224 (2016) FIG XPS spectra for Si 2s from Si substrate and Al 2p from LaAlO film for the RTA processed nanolaminates with different thickness of Al2O3 interlayer It is worth noting that the I-V characteristics (Figure 4) show different breakdown behaviors, which reveals that Al2O3 interlayer has a bad influence on the breakdown characteristics of the gate stacks, that is, the incorporation of Al2O3 interlayer degrades the breakdown field strength We ascribe the degradation of breakdown field strength to be associated with defects in gate dielectric.16,28 As mentioned above, extra structural defects and dangling bonds brought in by the un-optimized processing conditions of the first few cycles of Al2O3 deposition would deteriorate the interfacial characteristics of the gate stacks More structural defects and dangling bonds mean a greater possibility to create a conduction path by forming a continuous chain connecting the gate to the semiconductor, resulting in lower breakdown field IV CONCLUSION In summary, a technique of scavenging the IL by blocking the out-diffusion of substrate Si performed with a thin Al2O3 interlayer deposited between La2O3 layer and Si substrate has been studied systematically It was proved that, by suppressing the diffusion of oxygen from La2O3 layer to Si substrate with the existence of Al2O3 interlayer, oxygen vacancies in the gate stacks were reduced What’s more, significant decrease in the gate leakage current was achieved due to the large band offsets formed at the nanolaminate/Si interface However, with the increase in the thickness of Al2O3 interlayer, more interface traps and oxide trapped charges were detected in the gate dielectric, indicating that some improvements are in needed for this IL scavenging method to achieve excellent electrical performances ACKNOWLEDGMENTS This research is supported by the National Natural Science Foundation of China (Grant Nos 61376099 and 61434007) S Pelloquin, G Saint-Girons, N Baboux, D Albertini, W Hourani, J Penuelas, G Grenet, C Plossu, and G Hollinger, J Appl Phys 113, 034106 (2013) S Van Elshocht, C Adelmann, P Lehnen, and S De Gendt, Electrochem Solid-State Lett 12, G17 (2009) M Leskel, K Kukliä, and M Ritala, J Alloy Compd 418, 27 (2006) H Iwai, ECS Trans 50(5), 13 (2013) Q.-Y Liu, Z.-B Fang, S.-Y Liu, Y.-S Tan, and J.-J Chen, Mater Lett 116, 43 (2014) K Mistry, C Allen, C Auth, B Beattie, D Bergstrom, M Bost, M Brazier, M Buehler, A Cappellani, R Chau, C.-H Choi, G Ding, K Fischer, T Ghani, R Grover, W Han, D Hanken, M Hattendorf, J He, J Hicks, R Huessner, D Ingerly, P Jain, R James, L Jong, S Joshi, C Kenyon, K Kuhn, K Lee, H Liu, J Maiz, B Mclntyre, P Moon, J Neirynck, S Pae, C Parker, D Parsons, C Prasad, L Pipes, M Prince, P Ranade, T Reynolds, J Sandford, L Shifren, J Sebastian, 065224-7 Wang et al AIP Advances 6, 065224 (2016) J Seiple, D Simon, S Sivakumar, P Smith, C Thomas, T Troeger, P Vandervoorn, S Williams, and K Zawadzki, Int Electron Devices Meet 247 (2007) L.-Y Huang, A.-D Li, W.-Q Zhang, H Li, Y.-D Xia, and D Wu, Appl Surf Sci 256, 2496 (2010) W Yang, Q.-Q Sun, R.-C Fang, L Chen, P Zhou, S.-J Ding, and D W Zhang, Curr Appl Phys 12, 1445 (2012) L Lamagna, C Wiemer, M Perego, S N Volkos, S Baldovino, D Tsoutsou, S Schamm-Chardon, P E Coulon, and M Fanciulli, J Appl Phys 108, 084108 (2010) 10 H Kim, S Woo, J Lee, H Kim, Y Kim, H Lee, and H Jeon, J Electrochem Soc 157(4), H479 (2010) 11 H Wong, B.L Yang, K Kakushima, P Ahmet, and H Iwai, Vacuum 86, 929 (2012) 12 S Shen, Y Liu, R.G Gordon, and L J Brillson, Appl Phys Lett 98, 172902 (2011) 13 J R Hauser and K Ahmed, AIP Conf Proc 449, 235 (1998) 14 P Shekhter, A R Chaudhuri, A Laha, S Yehezkel, A Shriki, H J Osten, and M Eizenberg, Appl Phys Lett 105, 262901 (2014) 15 H.-S Kang, M Si P Reddy, D.-S Kim, K.-W Kim, J.-B Ha, Y S Lee, H.-C Choi, and J.-H Lee, J Phys D: Appl Phys 46, 155101 (2013) 16 S.M SZE and K.K NG, Physics of Semiconductor Devices, third ed (John Wiley & Sons, Inc., Hoboken, New Jersey, 2006), pp 223–236 17 E.H Nicollian and J.R Brews, MOS Physics and Technology (John Wiley & Sons, Inc., New York, 1982), p 223 18 K Martens, C O Chui, G Brammertz, B D Jaeger, D Kuzum, M Meuris, M M Heyns, T Krishnamohan, K Saraswat, H E Maes, and G Groeseneken, IEEE T Electron Dev 55(2), 547 (2008) 19 W A Hill and C C Coleman, Solid State Electron 23, 987 (1980) 20 F Werner, B Veith, D Zielke, L Kühnemund, C Tegenkamp, M Seibt, R Brendel, and J Schmidt, J Appl Phys 109, 113701 (2011) 21 A Stesmans and V V Afanas’ev, Appl Phys Lett 80, 1957 (2002) 22 M Kouda, T Suzuki, K Kakushima, P Ahmet, H Iwai, and T Yasuda, Jpn J Appl Phys 51, 121101 (2012) 23 C Lei, C Wang, G Wang, X Sun, T Li, and L Liu, J Alloy Compd 555, 51 (2013) 24 T Nabatame, K Iwamoto, K Akiyama, Y Nunoshige, H Ota, T Ohishi, and A Toriumi, ECS Trans 11(4), 543 (2007) 25 B Lee, A Hande, T.J Park, K.J Chung, J Ahn, M Rousseau, D Hong, H Li, X Liu, D Shenai, and J Kim, Microelectron Eng 88, 3385 (2011) 26 J Robertson, Solid State Electron 49, 283 (2005) 27 M Suzuki, Materials 5, 443 (2012) 28 S Lombardo, J H Stathis, B P Linder, K L Pey, F Palumbo, and C H Tung, J Appl Phys 98, 121301 (2005) ... (2016) Electrical properties and interfacial issues of high- k/ Si MIS capacitors characterized by the thickness of Al2O3 interlayer Xing Wang, Hongxia Liu,a Chenxi Fei, Lu Zhao, Shupeng Chen, and. .. at the layer interface Figure shows the C-V and G-V characteristics of the fabricated MIS capacitors using the annealed stacks with different thickness of Al2O3 interlayer as insulators The capacitors. .. when the Al2O3 interlayer exists, indicating that the trapped charges introduced by the deposition of Al2O3 interlayer should be one of the causes that lead to the positive shift of VFB With the