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5 PROJECT :ZAVA1/ZAVC1 PCB NO : DA60018A000 LA-B016P-R1.0 D B F D _ C @ D C S K Schematic Document r fo Intel Shark Bay ULT UMA / DIS AMD 25W/S3+DDR3x4 B t n e d i f n o C A l ia 2014-10-20 B Rev: 1.0 A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/26 Deciphered Date 2018/03/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Cover Page Document Number Rev 1.0 LA-B016P Friday, October 24, 2014 Sheet 1 of 56 D 128M*16 32bit VRAM DDR *2 PEG 2.0 x4 ~ e g a P Memory Bus (DDR3L) ~ e g a P VRAM 128M*16 32bit DDR *2 AMD 25W S3-64 23x23 Dual Channel , e g a P BANK 0, 1, 2, 3, ,5 ,6 ,7 1.35V DDR3L 1600 MHz DDI USB 3.0 e g a P Intel Broadwell ULT-U Processor BGA 1168 Port USB2.0 Port Port C Port PCI-E Port Touch Screen Card Reader RTS5170 Port Port C USB 2.0 Conn B Digital Mic Headphone Jack / Mic Jack combo 2 e g a P Audio Codec ALC3234 LPC Bus I2C 33MHz ENE KBC KB9012 PS/2 Touch Pad e g a P Int.KBD e g a P A Digital Camera (With Digital MIC) USB 3.0 Conn Int Speaker R / L e g a P 8MB Port HD Audio SPI e g a P e d i f n o C NGFF 2230 WiFi/WiGi/BT4.0 USB 3.0 Conn ~ e g a P t n SPI ROM l ia SATA3.0 SATA Rediver B r fo Port e g a P e g a P e g a P SATA HDD Conn S K Ethernet RTL8106E e g a P NGFF 2230 WiFi/WiGi /BT4.0 e g a P Port 3 e g a P x1 Port 6 e g a P x1 @ A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/26 Deciphered Date 2018/03/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: 4 e g a P B F D _ Port e g a P HDMI Conn 8GB Max e g a P eDP e g a P eDP Conn DDRIII-DIMM X2 D Block Diagram Document Number Rev 1.0 LA-B016P Friday, October 24, 2014 Sheet of 56 D Compal Confidential Project: ZAVA1/ZAVC1 File Name : LA-B016P B F D _ C USB FFC 16 pin CardReader Slot CardReader/B B t n FFC e d i f n o C A pin l ia r fo @ RJ45 S K HDMI USB USB Audio Jack B M/B LED/B A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/26 2018/03/31 Deciphered Date Title Date: D C THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC MB & DB Ass'y Document Number Rev 1.0 LA-B016P Friday, October 24, 2014 Sheet of 56 Board ID Table for AD channel Vcc Ra Board ID D C 10 11 12 13 14 15 16 17 18 19 3.3V +/- 1% 100K +/- 1% Rb 12K +/- 1% 15K +/- 1% 20K +/- 1% 27K +/- 1% 33K +/- 1% 43K +/- 1% 56K +/- 1% 75K +/- 1% 100K +/- 1% 130K +/- 1% 160K +/- 1% 200K +/- 1% 240K +/- 1% 270K +/- 1% 330K +/- 1% 430K +/- 1% 560K +/- 1% 750K +/- 1% NC V AD_BID typ 0.000V 0.354V 0.430V 0.550V 0.702V 0.819V 0.992V 1.185V 1.414V 1.650V 1.865V 2.031V 2.200V 2.329V 2.408V 2.533V 2.677V 2.800V 2.912V 3.300V V AD_BID 0.000V 0.347V 0.423V 0.541V 0.691V 0.807V 0.978V 1.169V 1.398V 1.634V 1.849V 2.015V 2.185V 2.316V 2.395V 2.521V 2.667V 2.791V 2.905V 3.000V V AD_BID max 0.300V 0.360V 0.438V 0.559V 0.713V 0.831V 1.006V 1.200V 1.430V 1.667V 1.881V 2.046V 2.215V 2.343V 2.421V 2.544V 2.687V 2.808V 2.919V 3.300V EC 0x00 0x0C 0x1D 0x27 0x31 0x3C 0x47 0x55 0x65 0x77 0x88 0x97 0xA4 0xAE 0xB8 0xC1 0xCA 0xD4 0xDD 0xE7 AD3 - 0x0B - 0x1C - 0x26 - 0x30 - 0x3B - 0x46 - 0x54 - 0x64 - 0x76 - 0x87 - 0x96 - 0xA3 - 0xAD - 0xB7 - 0xC0 - 0xC9 - 0xD3 - 0xDC - 0xE6 - 0xFF USB3.0 EC_SMB_CK1 EC_SMB_DA1 KB9012 EC_SMB_CK2 EC_SMB_DA2 KB9012 SMBCLK SMBDATA ULT SML0CLK SML0DATA ULT SML1CLK SML1DATA ULT BATT V Charger VGA DIMM XDP Thermal Sensor FFS V V V V V V t n e d i f n o C Symbol Note : l ia : means Digital Ground : means Analog Ground A Board ID 10 11 12 13 14 B F D _ DIS(JET) DIS(Topaz) UMA Pre-SSI Pre-SSI Pre-SSI SSI SSI SSI PT PT PT ST ST ST 1.0 1.0 1.0 S K r fo Link B Port2 USB connector Port4 SMBUS Control Table SOURCE USB connector Port3 BDW 3D BOARD ID Table ULT @ USB connector Port1 USB connector Port2 USB connector (D/B) Port3 C Port4 MINI Card (WLAN) Port5 Touch Screen Panel Port6 Card Reader Port7 Camera PCI EXPRESS Lane Lane Lane 10/100 LAN Lane MINI Card (WLAN) Lane PEG (AMD JET/TOBAZ) B CLOCK SIGNAL Lane CLKOUT_PCIE0 SATA CLKOUT_PCIE1 SATA0 CLKOUT_PCIE2 10/100 LAN CLKOUT_PCIE3 MINI Card (WLAN) CLKOUT_PCIE4 dGPU HDD SATA1 SATA2 SATA3 A CLKOUT_PCIE5 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/26 2018/03/31 Deciphered Date Title Date: D USB2.0 Port0 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Port1 Notes Document Number Rev 1.0 LA-B016P Friday, October 24, 2014 Sheet of 56 2.2K SMBUS Address [0x9a] 2.2K D AP2 MEM_SMBCLK AH1 MEM_SMBDATA 10K +3.3V_ALW_PCH +3VS 10K N-MOS N-MOS DDR_XDP_WLAN_TP_SMBCLK 202 DDR_XDP_WLAN_TP_SMBDAT 200 DIMM1 1K 202 +3.3V_ALW_PCH 1K BDW AN1 SML0CLK AK1 SML0DATA 200 ohm ohm 2.2K 2.2K AN1 SML1_SMBCLK AK1 SML1_SMBDATA N-MOS EC_SMB_CK2 2.2K 79 EC_SMB_CK2 80 EC_SMB_DA2 +3VALW 2.2K KBC KB9012A4 B 77 EC_SMB_CK1 78 EC_SMB_DA1 t n e d i f n o C A 51 S K r fo XDP1 @ SMBUS Address [A4] SMBUS Address [TBD] C 2.2K +3VS_VGA 2.2K N-MOS N-MOS VGA_SMB_CK2 T4 VGA_SMB_DA2 T3 UV28 GPU SMBUS Address [0xXX] +3VALW l ia 2.2K 53 DDR_XDP_SMBDAT_R1 B F D _ EC_SMB_DA2 2.2K C DDR_XDP_SMBCLK_R1 +3.3V_ALW_PCH N-MOS DIMM2 ohm ohm SCL 11 SDA 10 100 ohm 100 ohm PU701 PD1 POWER Charger SMBUS Address [0x12] BAT_ALERT BATT_PRS PBATT B BATT SMBUS Address [0x16] CONN A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/26 Deciphered Date 2018/03/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: D SMBUS Address [A0] SMBUS connection Document Number Rev 1.0 LA-B016P Friday, October 24, 2014 Sheet of 56 i3-4020U-15W-GT2-MP UC1 D I3R1@ UC1 I3R3@ CL8064701552800 QEZ5 D0 1.8G CL8064701478202 SR16Q C1 1.7G A31! SA00007MG0L SA00006SX2L TBD i5-4210U-15W-GT2-MP UC1 I5R1@ UC1 I5R3@ CL8064701477802 QEAK D0 1.7G CL8064701477702 SR170 C1 1.6G A31! SA00007LO0L SA00006SM3L TBD UC1 C54 C55 B58 C58 B55 A55 A57 B57 DDI1_LANE_N0 DDI1_LANE_P0 DDI1_LANE_N1 DDI1_LANE_P1 DDI1_LANE_N2 DDI1_LANE_P2 DDI1_LANE_N3 DDI1_LANE_P3 DDI1_LANE_N0 DDI1_LANE_P0 DDI1_LANE_N1 DDI1_LANE_P1 DDI1_LANE_N2 DDI1_LANE_P2 DDI1_LANE_N3 DDI1_LANE_P3 i7-4510U-15W-GT2-MP UC1 UC1 Broadwell I7R3@ UC1 CL8064701477301 QEAF D0 2G BGA CL8064701477202 SR16Z C1 1.8G A31! SA00007M70L SA00006SL2L TBD DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3 C51 C50 C53 B54 C49 B50 A53 B53 QG21@ CL8065801674128 QG21 C0 1.2G I7R1@ HASWELL_MCP_E UC1A EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 DDI EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3 EDP DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3 EDP_AUXN EDP_AUXP EDP_RCOMP EDP_DISP_UTIL C45 B46 A47 B47 EDP_TX0# EDP_TX0 EDP_TX1# EDP_TX1 COMPENSATION PU FOR eDP A45 B45 D20 A43 EDP_AUX# EDP_AUX UC1 EDP_BIA_PWM QG22@ SA00007OT0L B F D _ SYS_RESET# SYS_RESET# 2 H_CATERR# 49.9_0402_1% H_PROCHOT# 62_0402_5% H_CPUPWRGD HASWELL_MCP_E UC1B RC66 10K_0402_5% CC27 100P_0402_50V8J @EMI@ H_CATERR# PECI_EC PECI_EC D61 K61 N62 PROC_DETECT CATERR PECI MISC 2 r fo PRDY PREQ PROC_TCK PROC_TMS PROC_TRST PROC_TDI PROC_TDO JTAG ESD solution B @ CL8064701614813 QFSY C0 1.6G CL8065801675027 QG22 C0 1.2G C RC60 CAD Note: Avoid stub in the PWRGD path while placing resistors RC115 H_PROCHOT# RC67 H_PROCHOT#_R 56_0402_5% K63 H_CPUPWRGD C61 H_PROCHOT# DDR3 COMPENSATION SIGNALS 200_0402_1% RC68 SM_RCOMP0 120_0402_1% RC69 SM_RCOMP1 100_0402_1% RC70 SM_RCOMP2 @EMI@ CC42 22P_0402_50V8J e d i f n o C CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil DDR3_DRAMRST#_CPU CC35 @ESD@ 0.047U_0402_16V4Z PROCPWRGD t n SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 DDR3_DRAMRST#_CPU DDR_PG_CTRL AU60 AV60 AU61 AV15 AV61 l ia PROCHOT SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1 @ THERMAL PWR BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7 DDR3 RC71 CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils Rev1p2 OF 19 +1.05VS_PCH 24.9_0402_1%~D @ RC72 0_0402_5% @ SA00007AM0L @ RC58 +VCCIOA_OUT EDP_COMP EDP_DISP_UTIL S K J62 K62 E60 E61 E59 F63 F62 XDP_TCK XDP_TMS @ XDP_TRST# XDP_TDI @ XDP_TDO J60 H60 H61 H62 K59 H63 K60 J61 XDP_OBS0_R XDP_OBS1_R @ @ @ @ @ @ D C47 C46 A49 B49 SA00007OS0L QFSY@ SYS_RESET# C +3VS RC362 1K_0402_1% CC17 0.1U_0402_10V7K +1.05VS_PCH T123 R3 T122 PCH_JTAG_RST# 0_0402_5% PCH_JTAG_RST# XDP_TDO XDP_TCK XDP_TRST# RC141 @ 0_0402_1% T111 T112 T113 T114 T115 T116 B RP45 51_8P4R_5% PU/PD for JTAG signals Rev1p2 OF 19 Place CC35 on BOT A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/26 Deciphered Date 2015/03/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: MCP(1,2/19) eDP,XDP,MISC Document Number Rev 0.1 LA-B016P Monday, October 20, 2014 Sheet of 56 Interleaved Memory AP33 AR32 DDR_CS0_DIMMA# DDR_CS1_DIMMA# AY34 AW34 AU34 DDR_A_RAS# DDR_A_WE# DDR_A_CAS# AU35 AV35 AY41 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15 AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49 SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7 B Rev1p2 t n e d i f n o C RC14 1.82K_0402_1% +SM_VREF_CA 1 RC17 2.2_0402_1% 2 DDR_B_DQS#[0 1] DDR_A_DQS#[2 3] DDR_B_DQS#[2 3] DDR_A_DQS[0 1] DDR_B_DQS[0 1] DDR_A_DQS[2 3] r fo DDR_B_D[48 63] SB_CS#0 SB_CS#1 @ DDR CHANNEL B AY49 AU50 AW49 AV50 DDR_CKE2_DIMMB DDR_CKE3_DIMMB AM32 AK32 DDR_CS2_DIMMB# DDR_CS3_DIMMB# SB_RAS SB_WE SB_CAS SB_BA0 SB_BA1 SB_BA2 SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15 AM35 AK35 AM33 DDR_B_RAS# DDR_B_WE# DDR_B_CAS# AL35 AM36 AU49 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18 SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7 AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18 SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7 DDR_CKE2_DIMMB DDR_CKE3_DIMMB DDR_CS2_DIMMB# DDR_CS3_DIMMB# DDR_B_RAS# DDR_B_WE# DDR_B_CAS# DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_MA[0 15] C DDR_A_DQS#4 DDR_A_DQS#5 DDR_B_DQS#4 DDR_B_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_B_DQS#6 DDR_B_DQS#7 DDR_A_DQS#[4 5] DDR_B_DQS#[4 5] DDR_A_DQS#[6 7] DDR_B_DQS#[6 7] DDR_A_DQS4 DDR_A_DQS5 DDR_B_DQS4 DDR_B_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_B_DQS6 DDR_B_DQS7 DDR_A_DQS[4 5] DDR_B_DQS[4 5] DDR_A_DQS[6 7] DDR_B_DQS[6 7] Rev1p2 @ +1.35V +1.35V RC15 1.82K_0402_1% +SM_VREF_DQ1 +SM_VREF_DQ0_DIMM1 RC16 1.82K_0402_1% 1 RC18 2.2_0402_1% RC21 1.82K_0402_1% CC9 0.022U_0402_16V7K RC19 2.2_0402_1% RC22 1.82K_0402_1% change 22nF RC24 24.9_0402_1%~D +SM_VREF_DQ0 2 CC10 0.022U_0402_16V7K change 22nF RC25 24.9_0402_1%~D 2 confirm by intel request PDG P141 A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/26 Deciphered Date 2015/03/31 Title Date: M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3 B OF 19 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC D AL32 SB_ODT0 B F D _ DDR_A_D[48 63] S K +SM_VREF_CA +SM_VREF_DQ0 +SM_VREF_DQ1 change 22nF RC23 24.9_0402_1%~D DDR_A_DQS#[0 1] DDR_B_DQS[2 3] RC20 1.82K_0402_1% A DDR_A_DQS0 DDR_A_DQS1 DDR_B_DQS0 DDR_B_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_B_DQS2 DDR_B_DQS3 DDR_B_D[32 47] l ia CC8 0.022U_0402_16V7K DDR_A_DQS#0 DDR_A_DQS#1 DDR_B_DQS#0 DDR_B_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_B_DQS#2 DDR_B_DQS#3 +SM_VREF_DQ1_DIMM2 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_MA[0 15] AP49 AR51 AP51 SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1 +SM_VREF_CA_DIMM DDR_A_RAS# DDR_A_WE# DDR_A_CAS# DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48 SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7 +1.35V DDR_CS0_DIMMA# DDR_CS1_DIMMA# SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3 M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3 SA_BA0 SA_BA1 SA_BA2 @ SB_CK#0 SB_CK0 SB_CK#1 SB_CK1 AM38 AN38 AK38 AL38 SA_RAS SA_WE SA_CAS OF 19 DDR_CKE0_DIMMA DDR_CKE1_DIMMA AP32 SA_ODT0 DDR CHANNEL A DDR_CKE0_DIMMA DDR_CKE1_DIMMA SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 SA_CS#0 SA_CS#1 AU43 AW43 AY42 AY43 AY31 AW31 AY29 AW29 AV31 AU31 AV29 AU29 AY27 AW27 AY25 AW25 AV27 AU27 AV25 AU25 AM29 AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25 AL25 AY23 AW23 AY21 AW21 AV23 AU23 AV21 AU21 AY19 AW19 AY17 AW17 AV19 AU19 AV17 AU17 AR21 AR22 AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20 AM20 AR18 AP18 DDR_B_D[16 31] SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3 M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 SA_CLK#0 SA_CLK0 SA_CLK#1 SA_CLK1 M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1 DDR_A_D[16 31] C SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 AU37 AV37 AW36 AY36 DDR_B_D[0 15] AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56 AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51 HASWELL_MCP_E UC1D DDR_A_D[32 47] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_A_D[0 15] HASWELL_MCP_E UC1C D MCP(3,4/19) DDR3 Document Number Rev 0.1 LA-B016P Monday, October 20, 2014 Sheet of 56 1 +RTCVCC RTC Battery RC1 330K_0402_1% PCH_INTVRMEN 1 +3VS 2 +CHGRTC RC2 330K_0402_1% JP12 1 +3VLP INTVRMEN - INTEGRATED SUS 1.05V VRM ENABLE High - Enable Internal VRs Low - Enable External VRs For GCLK CC26 1U_0603_10V6K PCH_RTCX1 PCH_RTCX1 CC1 XTAL@ 1M_0402_5% 1 RC5 RC6 2 20K_0402_5% 20K_0402_5% 1 PCH_AZ_BITCLK PCH_AZ_SYNC PCH_AZ_RST# PCH_AZ_CODEC_SDIN0 RC8 ME_EN PCH_AZ_SDOUT 1K_0402_5% CMOS place near DIMM PCH_JTAG_RST# T175 @ SRTCRST# PCH_RTCRST# @ D G G RTC_DIS D S @ DMN66D0LDW-7_SOT363-6 QC2B t n S DMN66D0LDW-7_SOT363-6 QC2A CMOS_CLR1 RC368 100K_0402_5% @ l ia e d i f n o C Shunt Open ME_CLR1 AW8 AV11 AU8 AY10 AU12 AU11 AW10 AV10 AY8 HDA_BCLK/I2S0_SCLK HDA_SYNC/I2S0_SFRM HDA_RST/I2S_MCLK HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_SDO/I2S0_TXD HDA_DOCK_EN/I2S1_TXD HDA_DOCK_RST/I2S1_SFRM I2S1_SCLK S K r fo PCH_JTAG_RST# PCH_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS RTC discharge by EC B SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3 RTC CC3 1U_0402_6.3V6K PCH_AZ_CODEC_SDIN0 RTCX1 RTCX2 INTRUDER INTVRMEN SRTCRST RTCRST SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2 @ CMOS1 SHORT PADS~D 1U_0402_6.3V6K CC4 AW5 AY5 AU6 AV7 AV6 AU7 AU62 AE62 AD61 AE61 AD62 AL11 AC4 AE63 AV2 PCH_TRST PCH_TCK PCH_TDI PCH_TDO PCH_TMS RSVD RSVD JTAGX RSVD AUDIO SATA SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1 SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0 SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37 SATA_IREF RSVD RSVD SATA_RCOMP SATALED JTAG J5 H5 B15 A15 Shunt Clear ME RTC Registers Open Keep ME RTC Registers SATA HDD C J6 H6 B14 C15 PCH Rx side need use strap pin to update PCIE +/+3VS F5 E5 C17 D17 RC107 10K_0402_5% V1 U1 V6 AC1 EC_SMI# PCH_GPIO35 ODD_DETECT# PCH_GPIO37 A12 L11 K10 C12 U3 SATA_IREF RC126 SATA_RCOMP SATA_ACT# RC131 EC_SMI# +1.05VS_ASATA3PLL ODD_DETECT# SATA_ACT# @ 0_0603_1% 3.01K_0402_1% within 500 mils SATA Impedance Compensation CAD note: Place the resistor within 500 mils of the PCH Avoid routing next to clock pins reference FFRD sch 0.5 Rev1p2 OF 19 B @ +3VS HDA for Codec Clear CMOS TPM setting SATA_PRX_DTX_N0_C SATA_PRX_DTX_P0_C SATA_PTX_DRX_N0_C SATA_PTX_DRX_P0_C J8 H8 A17 B17 CMOS setting Keep CMOS @ +RTCVCC PCH_RTCX2 INTRUDER# PCH_INTVRMEN SRTCRST# PCH_RTCRST# RC7 HASWELL_MCP_E UC1E CC2 XTAL@ 15P_0402_50V8J B F D _ XTAL@ RC4 10M_0402_5% YC1 32.768KHZ_12.5PF_Q13FC1350000 2 XTAL@ PCH_AZ_SDOUT 1K_0402_5% LOW = DESABLED (DEFAULT) HIGH = ENABLED PCH_RTCX1 15P_0402_50V8J D FLASH DESCRIPTOR SECURITY OVERRIDE C @ RC3 JUMP_43X39 +RTCVCC W=20mils JUMP_43X39 W=20mils DC1 BAT54CW_SOT323-3 1 @ W=20mils 2 JP14 +RTCVCC RC10 1K_0402_5% +CHGRTC 2 +RTCBATT D PCH_AZ_CODEC_SDOUT PCH_AZ_CODEC_SYNC PCH_AZ_CODEC_RST# PCH_AZ_CODEC_BITCLK EMI@ R2356 33_0402_5% PCH_AZ_SDOUT EMI@ R2357 33_0402_5% PCH_AZ_SYNC EMI@ R2358 33_0402_5% PCH_AZ_RST# EMI@ R2359 33_0402_5% PCH_AZ_BITCLK ODD_DETECT# PCH_GPIO35 PCH_GPIO37 RP37 10K_8P4R_5% @EMI@ CC5 27P_0402_50V8J +1.05VS_PCH EMI depop location PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS RP48 51_8P4R_5% A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/26 Deciphered Date 2015/03/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: MCP(5/19) RTC,SATA,HDA,JTAG Document Number Rev 0.1 LA-B016P Monday, October 20, 2014 Sheet of 56 DE7 RB751V-40_SOD323-2 RC370 @ PCH_GPIO60 1 FW_UPDATE 0_0402_5% FW_UPDATE MEM Bus : DDR/XDP/WLAN/TP +3VALW_PCH +3VS 1 PCH_SPI_MOSI PCH_SPI_MISO PCH_SPI_WP# PCH_SPI_HOLD# C-LINK R2334 R2335 1K_0402_1% 1K_0402_1% @ QC1A DMN66D0LDW-7_SOT363-6 B F D _ Rev1p2 OF 19 MEM_SMBDATA T97 T98 T99 15_8P4R_5% +3VALW_PCH 2 @ @ @ QC1B DMN66D0LDW-7_SOT363-6 AF2 AD2 AF4 2 SPI CL_CLK CL_DATA CL_RST MEM_SMBCLK S PCH_SPI_MOSI_1 PCH_SPI_MISO_1 PCH_SPI_WP1# PCH_SPI_HOLD1# SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 SPI_MOSI SPI_MISO SPI_IO2 SPI_IO3 G RP39 AA3 Y7 Y4 AC2 AA2 AA4 Y6 AF1 PCH_SMB_ALERT# MEM_SMBCLK MEM_SMBDATA PCH_GPIO60 SML0CLK SML0DATA PCH_HOT# SML1_SMBCLK SML1_SMBDATA @ D R2332 10K_0402_5% S PCH_SPI_CLK PCH_SPI_CS0# AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3 D EMI@ R2333 15_0402_1% SMBALERT/GPIO11 SMBCLK SMBDATA SML0ALERT/GPIO60 SMBUS SML0CLK SML0DATA SML1ALERT/PCHHOT/GPIO73 SML1CLK/GPIO75 SML1DATA/GPIO74 LPC D @EMI@ C2326 68P_0402_50V8J 1 LAD0 LAD1 LAD2 LAD3 LFRAME R2331 10K_0402_5% G EMI PCH_SPI_CLK_R AU14 AW12 AY12 AW11 AV12 LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# +3VS HASWELL_MCP_E UC1G LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# R2330 10K_0402_5% R2329 10K_0402_5% 1 D DDR_XDP_WLAN_TP_SMBCLK DDR_XDP_WLAN_TP_SMBDAT SML1 Bus : EC/Sensors U2302 +3VALW_PCH CS# VCC DO(IO1) HOLD#(IO3) WP#(IO2) CLK GND DI(IO0) PCH_SPI_HOLD1# PCH_SPI_CLK_R PCH_SPI_MOSI_1 S K 2.2K_0804_8P4R_5% 64M EN25Q64-104HIP SOP 8P RP49 r fo SML0CLK SML0DATA @ QH1B SML1_SMBCLK EC_SMB_CK2 EC_SMB_DA2 DMN66D0LDW-7_SOT363-6 G U2302 4 SML1_SMBDATA D RP40 MEM_SMBCLK MEM_SMBDATA SML1_SMBCLK SML1_SMBDATA S SPI ROM ( 8MByte ) RC373 D 10K_0402_5% PCH_GPIO60 C2327 0.1U_0402_10V7K G +3VALW_PCH SA000039A30 WINBOND 64M W25Q64FVSSIQ SOIC 8P PCH_SPI_CS0# PCH_SPI_MISO_1 PCH_SPI_WP1# C +3VALW_PCH S C QH1A DMN66D0LDW-7_SOT363-6 For GCLK 1K_0804_8P4R_5% e d i f n o C 10/100 LAN -> WLAN(Mini Card) -> dGPU -> @ R2452 CLK_PCIE_LAN# CLK_PCIE_LAN LAN_CLKREQ# CLK_PCIE_WLAN# CLK_PCIE_WLAN CLK_PEG_VGA# CLK_PEG_VGA PEG_CLKREQ# S WLAN_CLKREQ# D WLAN_CLKREQ#_R G Q2409 B41 A41 Y5 C41 B42 AD1 B38 C37 N1 CLK_PCIE_WLAN# CLK_PCIE_WLAN WLAN_CLKREQ#_R A39 B39 U5 CLK_PEG_VGA# CLK_PEG_VGA B37 A37 T2 CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 PCIECLKRQ0/GPIO18 XTAL24_IN XTAL24_OUT RSVD RSVD DIFFCLK_BIASREF CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 PCIECLKRQ1/GPIO19 CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 PCIECLKRQ2/GPIO20 CLOCK SIGNALS CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 PCIECLKRQ3/GPIO21 CLKOUT_LPC_0 CLKOUT_LPC_1 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 PCIECLKRQ4/GPIO22 XTAL24_IN XTAL24_OUT K21 M21 C26 CLK_BIASREF C35 C34 AK8 AL8 AN15 AP15 SWAP_1 SWAP_2 XTAL@ CC7 15P_0402_50V8J RC13 XTAL@ 3.01K_0402_1% +1.05VS_AXCK_LCPLL RP41 10K_8P4R_5% SWAP_2 SWAP_1 CLKOUT_LPC0 R2336 EMI@ 22_0402_5% CLK_PCI_LPC B35 A35 CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 PCIECLKRQ5/GPIO23 OF 19 +3VS_WLAN_NGFF +3VS Rev1p2 @ RP42 TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8 A25 B25 B XTAL@ YC2 24MHZ_12PF_X3G024000DC1H 2 HASWELL_MCP_E UC1F 3.3P_0402_50V8C A 10K_8P4R_5% +3VS C43 C42 U2 CLK_PCIE_LAN# CLK_PCIE_LAN 0_0402_5%~D DII-DMN65D8LW-7~D A CC6 t n l ia XTAL24_IN XTAL24_IN RC12 1M_0402_5% B R2453 100K_0402_5%~D Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/26 Deciphered Date 2015/03/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: MCP(6,7/19) CLK,SMB,SPI,LPC Document Number Rev 0.1 LA-B016P Monday, October 20, 2014 Sheet of 56 PCH_PLTRST# CC33 +3VALW_PCH ME_SUS_PWR_ACK 10K_0402_5% SUSACK# 10K_0402_5% SUS_STAT#/LPCPD# 10K_0402_5% @ RC28 @ RC29 PCH_PLTRST# +3V_DSW 2 RC32 RC31 RC34 RC39 RC33 PCH_RSMRST#_R 0_0402_5% SUSACK# 0_0402_5% @ ME_SUS_PWR_ACK_R RC35 @ OUT PLT_RST# PLT_RST# UC3 MC74VHC1G08DFT2G_SC70-5 D R159 100K_0402_5% @ DSWODVREN - On Die DSW VR Enable H：Enable(DEFAULT) L：Disable Note: SUSACK# and SUSWARN# can be tied together if EC does not want to involve in the handshake mechanism for the Deep Sleep state entry and exit CAN be NC ,if not support Deep Sx CLKRUN# 8.2K_0402_5% RC36 PCH_DPWROK +3VS IN2 AC_PRESENT 10K_0402_5% PCH_BATLOW# 8.2K_0402_5% PCIE_WAKE#_R 1K_0402_5% PCH_SLP_WLAN# 10K_0402_5% IN1 @ CC11 0.1U_0402_10V7K 1 RC27 +3VS Place CC33 close to UC3.1 & UC3.2 VCC GND D ESD@ 0.047U_0402_16V4Z * B F D _ HASWELL_MCP_E UC1H +RTCVCC DPWROK: Tired toghter with RSMRST# that not support Deep Sx R2337 R2338 @ DSWODVREN - ON DIE DSW VR ENABLE HIGH = ENABLED (DEFAULT) 330K_0402_5% 330K_0402_5% LOW = DISABLED SYSTEM POWER MANAGEMENT SYS_PWROK CC31 C @ESD@ 0.047U_0402_16V4Z SUSACK# SUSACK# Place CC31 on BOT ACIN DH1 @ESD@ 0.047U_0402_16V4Z 0_0402_1% 0_0402_1% PBTN_OUT# RB751V-40_SOD323-2 PCH_PWROK CC34 0_0402_1% SUSACK#_R SYS_RESET# SYS_PWROK_R PCH_PWROK_R PM_APWROK_R PCH_PLTRST# SYS_RESET# RP50 0_8P4R_5% RC41 @ RC42 @ EC_RSMRST# ME_SUS_PWR_ACK @ SYS_PWROK SYS_PWROK PCH_PWROK RC37 SIO_SLP_S0# AK2 AC3 AG2 AY7 AB5 AG7 AW6 PCH_RSMRST#_R ME_SUS_PWR_ACK_R AV4 AL7 PBTN_OUT# AJ8 AC_PRESENT AN4 PCH_BATLOW# AF3 SIO_SLP_S0# AM5 PCH_SLP_WLAN# 2 RC73 RC74 @ RC75 RC76 2 RC77 RC79 2 @ RC87 DGPU_PWROK 10K_0402_5% PCH_TP_INT# 10K_0402_5% EDP_BIA_PWM 10K_0402_5% TS_RST# 10K_0402_5% DGPU_HOLD_RST# 10K_0402_5% FFS_INT1 10K_0402_5% l ia EDP_BIA_PWM EDP_BIA_PWM PANEL_BKLEN ENVDD_PCH DGPU_PWROK PXS_PWREN DGPU_HOLD_RST# FFS_INT1 ENVDD_PCH 100K_0402_5% CODEC_IRQ 1K_0402_1% t n e d i f n o C @ RC88 S K r fo U6 DGPU_PWROK P4 PXS_PWREN DGPU_HOLD_RST# N4 N2 FFS_INT1 AD4 T117 @ PCH_TP_INT# TS_RST# CODEC_IRQ B8 A9 C6 U7 L1 L3 R5 L4 DSWODVREN PCH_DPWROK PCIE_WAKE#_R V5 AG4 AE6 AP5 CLKRUN# SUS_STAT#/LPCPD# SUSCLK SIO_SLP_S5# AJ6 AT4 AL5 AP4 AJ7 SIO_SLP_S4# SIO_SLP_S3# @ T105 @ T107 @ T106 SLP_SUS# +3VS EDP_BKLCTL EDP_BKLEN EDP_VDDEN PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME CPU_DPB_CTRLDAT CPU_DPB_CTRLCLK CPU_DPC_CTRLCLK CPU_DPC_CTRLDAT DDPB_CTRLCLK DDPB_CTRLDATA DDPC_CTRLCLK DDPC_CTRLDATA eDP SIDEBAND DISPLAY GPIO GPIO55 GPIO52 GPIO54 GPIO51 GPIO53 DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP DDPB_HPD DDPC_HPD EDP_HPD OF 19 B9 C9 D9 D11 CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT CPU_DPC_CTRLCLK CPU_DPC_CTRLDAT C5 B6 B5 A6 CPU_DPB_AUX# CPU_DPC_AUX# CPU_DPB_AUX CPU_DPC_AUX C8 A8 D6 DPB_HPD DPC_HPD CPU_EDP_HPD# Rev1p2 DPC_HPD CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT RP52 2.2K_8P4R_5% CPU_DPB_AUX# CPU_DPB_AUX CPU_DPC_AUX CPU_DPC_AUX# B RP51 100K_8P4R_5% DPB_HPD RC84 100K_0402_5% @ C SUSCLK SIO_SLP_S5# T103 PAD~D@ T104 PAD~D @ SIO_SLP_S4# SIO_SLP_S3# G Rev1p2 CPU_EDP_HPD# @ RC82 0_0402_1% PCH_TP_INT# EDP_CPU_HPD RC89 100K_0402_5% S TP_INT# D PCH_DPWROK PCIE_WAKE# PCIE_WAKE# @ RC97 0_0402_5% +3VS TS_RST# EDP_BKLCTL PANEL_BKLEN ENVDD_PCH SLP_S4 SLP_S3 SLP_A SLP_SUS SLP_LAN AW7 AV5 AJ5 HASWELL_MCP_E UC1I @ RC81 0_0402_1% CLKRUN/GPIO32 SUS_STAT/GPIO61 SUSCLK/GPIO62 SLP_S5/GPIO63 OF 19 @ +3VS DSWVRMEN DPWROK WAKE RSMRST SUSWARN/SUSPWRDNACK/GPIO30 PWRBTN ACPRESENT/GPIO31 BATLOW/GPIO72 SLP_S0 SLP_WLAN/GPIO29 PCH_BATLOW# Need pull high to VCCDSW3_3 (If no deep Sx , connect to VCCSUS3_3) Place CC34 close to RP50.2&RP50.3 B SUSACK SYS_RESET SYS_PWROK PCH_PWROK APWROK PLTRST QC3 2N7002K_SOT23-3 RC367 0_0402_5% @ A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/26 Deciphered Date 2015/03/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: MCP(8,9/19) DDI,EDP,GPIO Document Number Rev 0.1 LA-B016P Monday, October 20, 2014 Sheet 10 of 56 @EMI@ PL1004 2.2UH_PCMB053T-2R2MS_5.5A_20% GPU_B+ VGA@_EMI@ PC1047 0.1U_0402_25V6K VGA_CORE TDC 27A Peak Current 38A OCP current 45A Load line X mV/A(not support) FSW=300kHz @EMI@ PC1025 2200P_0402_50V7K VGA@ PC1023 10U_0805_25V6K VGA@ PC1024 10U_0805_25V6K VGA@ PC1049 10U_0805_25V6K VGA@_EMI@ PC1042 0.1U_0402_25V6K VGA@ G2 D1 G1 SH00000NX00 (DCR:1.4± 5%) PL1002 36UH 20% PDME064T-R36MS1R405 24A VGA@ PR1058 10K_0402_1% ISEN1 @EMI@ PR1036 4.7_1206_5% +VGA_CORE VGA@ PR1039 3.65K_0603_1% VSUM+ @EMI@ PC1029 680P_0603_50V7K VGA@ PR1043 1_0402_1% VSUM- PJP1300 2 Vout=0.95V @ PC1306 22P_0402_50V8J VGA@ PC1308 22U_0805_6.3VAM +VGA_PCIE TDC 3A Peak Current 4.2A OCP current 6A +VGA_PCIE A JUMP_43X79 Compal Electronics, Inc Compal Secret Data Security Classification Issued Date 2014/03/26 Deciphered Date 2015/03/31 Title PWR_VGA_CORE/PCIE Date: VGA@ PC1305 22U_0805_6.3VAM +VGA_PCIEP VGA@ PC1303 22U_0805_6.3VAM 1 VGA@ VGA@ PR1301 10K_0402_1% +VGA_PCIEP SNUB_PCIE PR1302 VGA@ 5.9K_0402_1% 1 @ PR1304 47K_0402_5% FB_PCIE SY8036LDBC_DFN10_3x3 2EN_PCIE 200K_0402_5% FB EN @EMI@ PR1303 4.7_1206_5% SVIN VGA@ PR1300 @EMI@ PC1304 680P_0402_50V7K LX LX_PCIE +VGA_PCIEP PVIN LX VGA@ PC1301 22U_0805_6.3VAM LX SS PVIN 10 PCIE_B+ PG PU1300 JUMP_43X79 PXS_PWREN VGA@ PL1300 0.47UH_PCMB063T-R47MS_18A_20% @ 1 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC C VGA@ PJP1301 +3VALW VGA@ PC1302 TP VSSSENSE_VGA 11 VGA@ PR1051 10_0402_5% VCCSENSE_VGA 0_0402_5% @ PR1050 +VGA_CORE B PC1307 VGA@ 0.1U_0402_10V7K 1 +VGA_CORE t n @ PR1049 0_0402_5% 2 @EMI@ PC1045 2200P_0402_50V7K VGA@ PC1046 10U_0805_25V6K 1 l ia VGA@ PR1047 10_0402_5% @ PC1036 @ PR1048 820P_0402_50V7K 100_0402_1% 2 r fo VGA@ PC1034 330P_0402_50V7K 2 VGA@ PR1046 590_0402_1% 2 LGATE1 @ PR1038 32.4K_0402_1% VGA@ VGA@ PR1041 PC1033 137K_0402_1% 390P_0402_50V7K 2 VGA@ PR1045 2K_0402_1% e d i f n o C A S K 330P_0402_50V7K @ PC1030 VGA@ PC1032 0.22U_0603_16V7K PC1031 0.01U_0402_50V7K 2 VGA@ PR1044 11K_0402_1% VGA@ PC1035 0.1U_0603_50V7K @ VGA@ PR1040 825_0402_1% VGA@ PC1040 0.01U_0402_50V7K VSUM- VGA@ PC1028 100P_0402_50V8J VGA@ VGA@ PC1027 PR1037 1000P_0402_50V7K 301_0402_1% 2 VGA@ PH1003 10K_0402_5%_ERTJ0ER103J 2 PR1042 VGA@ 2.61K_0402_1% PH1003 near GPU_CORE choke @ PC1051 VGA@ 0.22U_0402_10V6K ISEN1 VGA@ PQ1003 AON6970_DFN5X6D-8-7 BOOT1 PC1050 VGA@ 0.22U_0402_10V6K ISEN2 VSUM+ B VGA@ PR1053 1_0402_1% PHASE1 VSUM- DGPU_PWROK S2 @ PH1002 470K_0402_5%_TSM0B474J4702RE D2/S1 S2 32 PH1002 near GPU_CORE H/S mos VGA@ VGA@ PR1034 PC1026 2.2_0603_1% 0.22U_0603_25V7K 2 S2 PHASE1 @ PR1030 100K_0402_1% +3VS BOOT1 21 UGATE1 PL1003 VGA@ PR1057 3.65K_0603_1% VSUM+ GPU_B+ VGA@ PC1021 1U_0603_10V6K 22 PHASE1 LGATE1 23 VGA@ PC1020 1U_0603_10V6K 24 VGA@ PR1059 10K_0402_1% VSUM- B F D _ +5VALW VGA@ PR1024 1_0603_5% PGOOD COMP LGATE2 20 19 FB 18 17 RTN VSEN BOOT1 @ PR1052 13.3K_0402_1% 27 ISEN2 @EMI@ PC1044 680P_0603_50V7K 31 BOOT_NB UGATE_NB 34 35 36 37 38 33 PHASE_NB LGATE_NB PGOOD_NB COMP_NB FB_NB IMON PHASE2 39 UGATE1 16 VGA@ 1000P_0402_50V7K PC1022 @ PR1031 150K_0402_1% VSEN_NB 40 PHASE1 PWROK ISUMN IMON_GPU 10 LGATE1 ENABLE UGATE2 28 25 VDD SVT NTC VDDIO BOOT2 29 UGATE1 PR1029 VGA@ 133K_0402_1% 30 26 VDDP ISL62771HRTZ-T_TQFN40_5X5 ISUMP PXS_PWREN VGA@ @ PR1027 ENABLE 0_0402_5% DGPU_PWROK LGATE2 SVD 15 VDDIO SVI2_SVT VR_HOT_L ISEN1 +1.5VS PHASE2 14 C SVC 13 UGATE2 ISEN2 @PR1025 0_0402_5% PC1019 0.1U_0402_25V6K BOOT2 IMON_NB 12 SVI2_SVD +1.8VGS OCP_L @ PR1020 100K_0402_1% 1@ PR1022 0_0402_5% ISUMN_NB 41 TP +3VS SVI2_SVC NTC_NB 11 ISUMP_NB VGA@ PR1032 100K_0402_1% VGA@ PR1033 100K_0402_1% 2 @EMI@ PR1054 4.7_1206_5% 0.1U_0402_10V7K PR1035 PR1056 +5VALW LGATE2 VGA@ PU1000 VGA@ PHASE2 VGA@ PQ1004 AON6970_DFN5X6D-8-7 G2 S2 S2 S2 VGA@ PC1041 10U_0805_25V6K 1 D2/S1 VGA@ PC1043 0.22U_0603_25V7K VGA@ PR1055 2.2_0603_1% D SH00000NX00 (DCR:1.4± 5%) G1 PHASE2 BOOT2 B+ 36UH 20% PDME064T-R36MS1R405 24A 10K_0402_1% VGA@ 10K_0402_1% VGA@ D1 D VGA@ PC1048 10U_0805_25V6K UGATE2 @EMI@ PC1052 10U_0805_25V6K VGA@_EMI@ PL1000 FBMJ4516HS720NT_2P VGA@ PC1300 22U_0805_6.3VAM Rev 0.1 LA-B016P Monday, October 20, 2014 Sheet 42 of 56 @ C @ 1 @ 1 + l ia r fo Security Classification Issued Date 2014/03/26 2 VGA@ 2.2U_0402_6.3V6M PC850 2 2 Deciphered Date @ 10U_0603_6.3V6M PC855 2015/03/31 1 VGA@ 2.2U_0402_6.3V6M PC840 PC908 22U_0805_6.3V6M VGA@ 2.2U_0402_6.3V6M PC841 VGA@ 2.2U_0402_6.3V6M PC842 VGA@ 2.2U_0402_6.3V6M PC843 VGA@ 2.2U_0402_6.3V6M PC844 VGA@ 2.2U_0402_6.3V6M PC845 VGA@ 2.2U_0402_6.3V6M PC846 VGA@ 2.2U_0402_6.3V6M PC847 VGA@ 2.2U_0402_6.3V6M PC869 VGA@ 2.2U_0402_6.3V6M PC871 10U_0603_6.3V6M PC856 2 VGA@ VGA@ 10U_0603_6.3V6M PC854 PC907 22U_0805_6.3V6M VGA@ 10U_0603_6.3V6M PC853 VGA@ 2 1 2 + + THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Compal Secret Data Date: + 2 + VGA@ 330U_D2_2V_Y VGA@ 2.2U_0402_6.3V6M PC872 PC906 22U_0805_6.3V6M VGA@ 330U_D2_2V_Y VGA@ 2.2U_0402_6.3V6M PC852 2 VGA@ 330U_D2_2V_Y VGA@ 2.2U_0402_6.3V6M PC851 PC905 22U_0805_6.3V6M VGA@ 330U_D2_2V_Y 1 0.1U_0402_10V7K PC860 VGA@ 2.2U_0402_6.3V6M PC849 B F D _ VGA@ VGA@ 2.2U_0402_6.3V6M PC848 0.1U_0402_10V7K PC859 PC916 22U_0805_6.3V6M 10U_0603_6.3V6M PC858 2 VGA@ 10U_0603_6.3V6M PC857 2 PC904 22U_0805_6.3V6M @ VGA@ VGA@ PC915 22U_0805_6.3V6M @ 220U_D2_2.5VY_R9M PC914 2.2U_0402_6.3V6M @ PC923 22U_0805_6.3V6M 1 PC903 22U_0805_6.3V6M @ PC839 B 2 PC913 22U_0805_6.3V6M @ PC922 22U_0805_6.3V6M PC902 22U_0805_6.3V6M PC912 22U_0805_6.3V6M +VGA_CORE PC838 PC837 t n e d i f n o C 1 PC901 22U_0805_6.3V6M PC911 22U_0805_6.3V6M @ PC921 22U_0805_6.3V6M PC910 22U_0805_6.3V6M @ @ PC920 22U_0805_6.3V6M PC919 22U_0805_6.3V6M PC836 @ @ PC924 A 2 @ PC918 22U_0805_6.3V6M @ PC909 22U_0805_6.3V6M D PC917 22U_0805_6.3V6M +CPU_CORE Monday, October 20, 2014 Sheet D C S K B A Title PWR_PROCESSOR DECOUPLING Compal Electronics, Inc Document Number LA-B016P 43 of 56 Rev 0.1 4 Power block D CPU OTP Page 34 Turn Off Input Switch DC IN B+ +3VALWP: TDC:5.4A +5VALWP: TDC:5.6A TPS51285BRUKR Page 35 CHARGER CC:0A~2A(3cell) or 3.9A(2cell) CV:13.3V(3cell) / 9.1V(2cell) ISL9520 S K +3VALW Page 35 Battery PXS_PWREN B +VGA_CORE TDC: 31A ISL62771HRTZ-T t n Page 42 e d i f n o C VR_ON A +CPU_CORE TDC: 14A@15W /19A@28W ISL95813HRZ-T l ia r fo EC_ON B F D _ +3VALW C +3VALW @ Page 36 +1.8VSP: TDC:1.5A SY8003DFC PXS_PWREN +1.5VSP: TDC:1A APL5930 SUSP# Page 37 +VGA_PCIEP: TDC:3A SY8036LDBC PXS_PWREN Page 42 B SYSON +VCCIO: TDC:5A SY8206DQNC Page 38 +1.35VP/+0.675VSP: TDC:6A/0.7A RT8207MZQW Page 40 SYSON Page 39 +1.35VGPUP: TDC:9A TPS51212DSCR PXS_PWREN Page 41 A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/26 Deciphered Date 2015/03/31 Title Date: C Page 37 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC D PWR_POWER BLOCK DIAGRAM Document Number Rev 0.1 LA-B016P Monday, October 20, 2014 Sheet 44 of 56 Version Change List ( P I R List ) D Item Page# 44 Title DCIN/BATT CONN/OTP Date 13/10/24 Request Owner Morris Page Issue Description Solution Description design change change PR16 from 100K to 10K 45 CHARGER 13/10/24 Morris change PC711 from 1000pF to 0.01uF design change 0.2 change PR711 from 49.9K to 51.1K change PR713 from 10K to 499K change PR724 from 100K to 499K change PC721 from 0.047u to 0.22u change PC722 from 0.1u to 1u add PC732 100u 46 3.3VALWP/5VALWP 13/10/24 Morris change PC104 from 0.1u to 0.22u design change for solve can't root issue D 0.2 add PR37 10K Rev B F D _ change PC110 from 0.1u to 0.22u change PR102 from 2.2K to 10K @ 0.2 add PR110 20K 50 VCORE 13/10/24 Morris change PR507(15W@) from 90.9K to 169K adjust CPU parameter 0.2 change PR519 from 1.91K to 10K C C change PR521 from 95.3K to 97.6K change PR539 from 8.06K to 909 change PC515,PC516 from SF000005100 to SF000004M00 change PL502 from SH00000NM00 to SH00000PQ00 r fo 52 VGA_CORE/PCIE 13/10/24 Morris design change from vendor change LL 53 PROCESSOR DECOUPLING 13/10/24 Morris adjust CPU parameter 45 CHARGER 13/10/28 Morris l ia S K t n change PR537 from 1.27K to 1.37K change PR535(28W@) from 432 to 261 change PR507(28W@) from 113K to 205K change PR551 from 2.61K to 5.23K add PC522 82pF add PR533 0-ohm change PR1040 from 1.24K to 825 0.2 change PC924 from SGA20331E10 to SGA00009800 0.2 remove PC901,PC903,PC904,PC906,PC908,PC909,PC910,PC911,PC912,PC913,PC914, PC915,PC917,PC919,PC921 design change for plug out battery shut down issue B change PR535(15W@) from 340 to 210 change PC723 from 0.01uF to 0.47uF 0.2 change PR728 from to 9.09K change PC728 from 4700pF to 2200pF B change PC701 from 220pF to 1000pF 46 3.3VALWP/5VALWP 13/12/12 Morris design change from EE request add PR115 10K-ohm 0.3 10 50 VCORE 13/12/12 Morris design change from Intel recommend change PR519 from 10K to 1.5K 0.3 0.3 e d i f n o C 11 12 13 14 A 48 +VCCIO 13/12/13 Morris design change from EE request delete PR310 and add PR300 0-ohm 50 VCORE 14/01/20 Morris adjust CPU parameter change PR507(15W@) from 169K to 90.9K 1.0 change PR507(28W@) from 205K to 113K 53 PROCESSOR DECOUPLING 14/02/13 Morris design change from thermal request change PC836 PC837 PC838 PC839 from SGA20331E10 to SGA00006A00 1.0 50 VCORE 14/03/03 Morris design change for VGA thermal issue change PC836 PC837 PC838 PC839 from SGA20331E10 to SGA00006A00 1.0 A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/26 Deciphered Date 2015/03/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PWR-PIR Document Number Rev 0.1 LA-B016P Monday, October 20, 2014 Sheet 45 of 56 +5VALW +3VALW TO +5V_3DCAM C94 1U_0402_6.3V6K J521 J518 open @ 1 +5VALW JUMP_43X39 D +5V_CAM D U2409 @ 4.7K_0402_5%~D USB3_ERD_P0 RI191 RI201 RI211 RI221 RI261 RI231 @ @ @ @ @ @ 2 2 2 USB3_OS2_P0 USB3_DE2_P0 USB3_EQ2_P0 USB3_OS1_P0 USB3_DE1_P0 USB3_EQ1_P0 B F D _ @ 0_0402_5%~D EMI@ RI871 RI311 RI361 RI401 RI351 RI321 @ @ @ @ @ @ 2 2 2 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D USB3_OS2_P0 USB3_DE2_P0 USB3_EQ2_P0 USB3_OS1_P0 USB3_DE1_P0 USB3_EQ1_P0 USB3RN4_R_C USB3RP4_R_C @ 4.7K_0402_5%~D USB3_CM_P0 RI481 @ 4.7K_0402_5%~D USB3_ERD_P0 0_0402_5%~D 0_0402_5%~D +3VS CI23 0.01U_0402_16V7K~D 2 S K UI8 13 USB3RN4_3D_CAM USB3RP4_3D_CAM USB3RN4 USB3RP4 CI22 CI19 1 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D USB3TN4_3D_CAM USB3TP4_3D_CAM A USB3TN4 USB3TP4 CI16 1 CI5 t n 0.1U_0402_10V6K~D USB3TN4_L 0.1U_0402_10V6K~D USB3TP4_L e d i f n o C VCC VCC l ia USB3RN4_L USB3RP4_L USB3_OS2_P0 USB3_DE2_P0 USB3_EQ2_P0 USB3TP4_R_C CI20 1U_0402_16V7K~D USB3RP4_R USB3_OS1_P0 USB3_DE1_P0 USB3_EQ1_P0 11 12 15 16 17 25 TX2TX2+ NC NC RX2RX2+ OS2 DE2 EN_RXD EQ2 CM RX1RX1+ OS1 DE1 EQ1 PGND TX1TX1+ GND GND GND GND r fo 24 RI56 @ RI57 20 19 USB3RN4_R_C USB3RP4_R_C 14 23 22 10 18 21 +3VALW_PCH C5221 0.1U_0402_10V6K CT pin use 2200pf for soft start tuning +3VS @ RI55 10K_0402_5% 10K_0402_5% FW_UPDATE C +3VS RI89 @ RI88 RI54 10K_0402_5% 10K_0402_5% 3D_CAM_EN 0_0402_5%~D LI9 JCAM3D USB3TN4_R 0_0402_5%~D 10 11 12 USB3RN4_R USB3RP4_R USB3TP4_R RI58 0_0402_5%~D CAM_DETECT FW_UPDATE S COM FI_ CHILISIN CMMI21T-670Y-N @ RI6 +3VALW_PCH 0_0402_5%~D EMI@ USB3_P0_PIN6 USB3_P0_PIN18 B USB3RN4_R CAM_DETECT FW_UPDATE 3.3K_0402_1% 0_0402_5%~D USB3TN4_R USB3TP4_R DETECT +5V_CAM RI91 100K_0402_5% @ 10 GND GND B ACES_50463-0104A-001 @ @ @ RI5 USB3TN4_R_C RI49 RI50 1 S COM FI_ CHILISIN CMMI21T-670Y-N @ RI4 RI461 LI10 C 1 @ RI3 TPS22967DSGR_SON8_2X2 For Test, APE8937(SA000070L00) AOZ1336(SA00006U600) TPS22967(SA000070S00) 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D VBIAS GND GND RI90 100K_0402_5% RI441 CT USB3_CM_P0 ON 2 4.7K_0402_5%~D 3D_CAM_EN VOUT VOUT USB3_P0_PIN6 USB3_P0_PIN18 RI421 3.3K_0402_5% 3.3K_0402_5% VIN VIN @ @ RI53 RI52 1 C5220 2200P_0402_25V7K +5VALW +3VS DI3 USB3_ERD_P0 USB3_CM_P0 1 USB3TN4_RC CI21 USB3TP4_RC CI24 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D USB3TN4_R_C USB3TP4_R_C USB3RN4_R 10 USB3RN4_R USB3RP4_R USB3RP4_R USB3TN4_R USB3TN4_R USB3TP4_R USB3TP4_R USB3_P0_PIN6 USB3_P0_PIN18 S DIO(BR) TVWDF1004AD0 DFN ESD @ PS8713BTQFN24GTR2-A0_TQFN24_4X4 A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/26 Deciphered Date 2015/03/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: LED / B Document Number Rev 0.1 LA-B016P Friday, October 24, 2014 Sheet 46 of 56 @ UV1A A PEG_CTX_GRX_P0 PEG_CTX_GRX_N0 PEG_CTX_GRX_P1 PEG_CTX_GRX_N1 PEG_CTX_GRX_P2 PEG_CTX_GRX_N2 PEG_CTX_GRX_P3 PEG_CTX_GRX_N3 PEG_CTX_GRX_P0 PEG_CTX_GRX_N0 AF30 AE31 PEG_CTX_GRX_P1 PEG_CTX_GRX_N1 AE29 AD28 PEG_CTX_GRX_P2 PEG_CTX_GRX_N2 AD30 AC31 PEG_CTX_GRX_P3 PEG_CTX_GRX_N3 AC29 AB28 AB30 AA31 UV1 AA29 Y28 TOPAZ@ PCIE_TX0P PCIE_TX0N PCIE_RX1P PCIE_RX1N PCIE_TX1P PCIE_TX1N PCIE_RX2P PCIE_RX2N PCIE_TX2P PCIE_TX2N PCIE_RX3P PCIE_RX3N PCIE_TX3P PCIE_TX3N PCIE_RX4P PCIE_RX4N PCIE_TX4P PCIE_TX4N PCIE_RX5P PCIE_RX5N Y30 W31 TOPAZ XT S3 FCBGA 631P GPU 0FD W29 V28 SA000079N0L PCIE_RX0P PCIE_RX0N PCIE_TX5P PCIE_TX5N PCIE_RX6P PCIE_RX6N PCIE_TX6P PCIE_TX6N PCIE_RX7P PCIE_RX7N PCIE_TX7P PCIE_TX7N AH30 AG31 PCIE_CRX_C_GTX_P0 PCIE_CRX_C_GTX_N0 0.1U_0402_10V7K 0.1U_0402_10V7K 2 CV1 CV2 DIS@ DIS@ PEG_CRX_GTX_P0 PEG_CRX_GTX_N0 PEG_CRX_GTX_P0 PEG_CRX_GTX_N0 AG29 AF28 PCIE_CRX_C_GTX_P1 PCIE_CRX_C_GTX_N1 0.1U_0402_10V7K 0.1U_0402_10V7K 2 CV3 CV4 DIS@ DIS@ PEG_CRX_GTX_P1 PEG_CRX_GTX_N1 PEG_CRX_GTX_P1 PEG_CRX_GTX_N1 AF27 AF26 PCIE_CRX_C_GTX_P2 PCIE_CRX_C_GTX_N2 0.1U_0402_10V7K 0.1U_0402_10V7K 2 CV5 CV6 DIS@ DIS@ PEG_CRX_GTX_P2 PEG_CRX_GTX_N2 PEG_CRX_GTX_P2 PEG_CRX_GTX_N2 AD27 AD26 PCIE_CRX_C_GTX_P3 PCIE_CRX_C_GTX_N3 0.1U_0402_10V7K 0.1U_0402_10V7K 2 CV7 CV8 DIS@ DIS@ PEG_CRX_GTX_P3 PEG_CRX_GTX_N3 PEG_CRX_GTX_P3 PEG_CRX_GTX_N3 AC25 AB25 V30 U31 JET@ U29 T28 T30 R31 N29 M28 M30 L31 DIS@ NC#T24 NC#T23 NC#N29 NC#M28 NC#P27 NC#P26 CLOCK AK30 AK32 B F D _ AB27 AB26 Y27 Y26 N10 TEST_PG AL27 PLT_RST_VGA# e d i f n o C l ia NC#M27 NC#N26 PERSTB CALIBRATION W24 W23 V27 U26 S K U24 U23 T26 T27 T24 T23 r fo NC#P24 NC#P23 PCIE_REFCLKP PCIE_REFCLKN t n 1K_0402_1% NC#T26 NC#T27 NC#P30 NC#N31 NC#L29 NC#K30 C RV2 NC#U24 NC#U23 NC#M30 NC#L31 L29 K30 CLK_PEG_VGA CLK_PEG_VGA# NC#V27 NC#U26 NC#R29 NC#P28 P30 N31 CLK_PEG_VGA CLK_PEG_VGA# NC#U29 NC#T28 NC#T30 NC#R31 R29 P28 NC#W24 NC#W23 PCI EXPRESS INTERFACE JET XT S3 FCBGA 631P GPU 0FD SA00007A50L NC#V30 NC#U31 PCIE_CALR_TX PCIE_CALR_RX No Use GPU Display Port outpud @ UV1F Y23 Y24 B UV1 @ A P27 P26 P24 P23 +VGA_CORE VARY_BL DIGON TXCAP_DPA3P TXCAM_DPA3N TX0P_DPA2P TX0M_DPA2N TX1P_DPA1P TX1M_DPA1N TX2P_DPA0P TX2M_DPA0N NC_TXOUT_L3P NC_TXOUT_L3N TOPAZ AL15 AK14 B AH16 AJ15 AL17 AK16 AH18 AJ17 AL19 AK18 TMDP TXCBP_DPB3P TXCBM_DPB3N TX3P_DPB2P TX3M_DPB2N TX4P_DPB1P TX4M_DPB1N TX5P_DPB0P TX5M_DPB0N NC_TXOUT_U3P NC_TXOUT_U3N M27 N26 AB11 AB12 AH20 AJ19 AL21 AK20 AH22 AJ21 AL23 AK22 AK24 AJ23 2160856030-A0_FCBGA631 ? C +VGA_PCIE Y22 RV1 DIS@ 1.69K_0402_1% AA22 RV3 DIS@ 1K_0402_1% 2160856030-A0_FCBGA631 +3VGS PLT_RST# DGPU_HOLD_RST# PLT_RST# DGPU_HOLD_RST# B Y A PLT_RST_VGA# G P UV2 DIS@ RV4 100K_0402_5% DIS@ D D MC74VHC1G08DFT2G_SC70-5 Compal Secret Data Security Classification Issued Date 2014/03/26 Deciphered Date 2015/03/31 Compal Electronics, Inc TOPAZ_PCIE/DP Size Document Number Rev Custom 0.1 LA-B016P of Monday, October 20, 2014 47 56 Date: Sheet Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 5 +3VGS ALERT# D- THERM# SCLK GND SDATA VGA_DPLUS VGA_DMINUS VGA_SMB_CK3 VGA_SMB_DA3 DIS@ CV9 DPC NC#Y4 NC#W5 +1.8VGS 1FB_VDDCI @ T221 1PLL_Analog_in RV82 TOPAZ@1 4.7K_0402_5% BP_0 U1 W1 RV81 TOPAZ@1 4.7K_0402_5% BP_1 U3 Y6 AA1 NC#U1 NC#W1 NC#U3 NC#Y6 NC#AA1 NC#AA3 NC#Y2 NC#J8 W3 V2 Y4 W5 AA3 PLL_Analog_out Y2 J8 RV77 RV78 SVI2_SVD SVI2_SVC 33_0402_5%JET@ S IC SN74AVC2T45DCTR_SM8 +3VGS U1 CPN is phase out JET@ CV169 10U_0603_6.3V6M 10K_0402_5% DIR RV79 JET@ RV74 10K_0402_5% JET@ 1 RV73 10K_0402_5% JET@ CV167 3.3V TO 1.8V LEVEL SHIF For JET/SUN to support SVI2 reaulator DNI for TOPAZ 0.1U_0402_10V7K JET@ PEG_CLKREQ# RV153 0_0402_5% @ T86 @ JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO TESTEN PAD +3VGS +VGA_CORE RV17 DIS@ 1K_0402_1% RV152 TESTEN @ 10K_0402_5% DIS@ RV151 10K_0402_5% RV20 DIS@ 1M_0402_5% JTAG_TRSTB JTAG_TDI JTAG_TMS JTAG_TCK t n RP34 10K_8P4R_5% XTALOUT XTALIN @ YV1 DIS@ 27MHZ_10PF_7V27000050 GND CV18 8.2P_0402_50V8D DIS@ e d i f n o C RV150 2 GND 1 3 CV17 8.2P_0402_50V8D DIS@ PEG_CLKREQ#_R 10K_0402_5% @ l ia @ T218 +3VGS @ T4930 C GPIO19_CTF 2 5.1K_0402_1% PX_EN AC16 R AVSSN#AK26 GENERAL PURPOSE I/O GPIO_0 GPIO_1 GPIO_2 SMBDATA SMBCLK GPIO_5_AC_BATT GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16 GPIO_17_THERMAL_INT GPIO_18 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21 GPIO_22_ROMCSB GPIO_29 GPIO_30 CLKREQB JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO TESTEN NC#AF24 G AVSSN#AJ25 B AVSSN#AG25 DAC1 HSYNC VSYNC RSET AVDD AVSSQ FutureASIC/SEYMOUR/PARK CEC_1 RSVD#AK12 RSVD#AL11 RSVD#AJ11 GENLK_CLK GENLK_VSYNC SWAPLOCKA SWAPLOCKB PS_0 PS_1 PS_2 HPD1 PX_EN PS_3 TS_A DDC/AUX DDC1CLK DDC1DATA DDC2CLK DDC2DATA AM28 AK28 AC22 AB22 XTALIN XTALOUT AUX2P AUX2N XO_IN XO_IN2 NC#AD20 NC#AC20 NC#AE16 NC#AD16 SEYMOUR/FutureASIC +1.8VGS LV2 DIS@ BLM15BD121SN1D_0402 VGA_DPLUS VGA_DMINUS 13mA R5 AD17 AC17 GPIO28 +TSVDD 10U_0603_6.3V6M CV19 DIS@ T4 T2 1U_0402_6.3V4Z CV20 DIS@ DPLUS DMINUS @ NC 11 0.68U_0402_10V 2 AH24 AG25 AH26 AJ27 CV11 DIS@ RV162 4.7K_0402_5% @ WAKEB AD22 AE23 AD23 AM12 AK12 AL11 AJ11 TOPAZ@1 RV155 TOPAZ@1 RV156 TOPAZ@1 RV157 DDCVGACLK DDCVGADATA THERMAL CV15 SVI2_SVT @ PS_2[2] N/A PS_2[4] STRAP_BIF_VGA_DIS +1.8VGS 1G@ RV15 8.45K_0402_1% PS_2[5] N/A Strap Name : PS_3[1] BOARD_CONFIG[0] (Memory ID) PS_3[2] BOARD_CONFIG[1] (Memory ID) PS_3[3] BOARD_CONFIG[2] (Memory ID) PS_3[4] AUD_PORT_CONN_PINSTRAP[1] 1G@ RV16 2K_0402_1% PS_3[5] AUD_PORT_CONN_PINSTRAP[2] RV15 Topaz SVI2 AL13 AJ13 PS_2[1] N/A B PS_3 SVI2_SVD SVI2_SVT SVI2_SVC Strap Name : PS_2[3] STRAP_BIOS_ROM_EN DIS@ RV13 4.75K_0402_1% PS_3[5:4]=11 0_0402_5% 0_0402_5% 0_0402_5% PS_1[5] STRAP_TX_DEEMPH_EN @ @ RV28 8.45K_0402_1% PS_3[3:1]=000 RV163 4.7K_0402_5% DIS@ AG24 AE22 DIS@ RV12 4.75K_0402_1% +1.8VGS PS_2[3:1]=000 B F D _ +3VGS AL25 AJ25 PS_1[3] N/A 10 +1.8VGS +1.8VGS 2G@ RV16 2G@ 4.53K_0402_1% 4.99K_0402_1% SD034453180 SD034499180 AG13 AH12 AC19 PS_0 AD19 PS_1 AE17 PS_2 AE20 PS_3 RV84 10K_0402_5% TOPAZ@ SVI2_SVD SVI2_SVC AE19 Vendor Configuration Size 000 SA000068U0L SAMSUNG K4W2G1646Q-BC1A 1GB (default) 001 SA00006H40L HYNIX H5TC2G63FFR-11C 1GB 010 SA00006750L Micron MT41J128M16JT-093G 1GB 011 SA000076P0L SAMSUNG K4W4G1646B-HC11 2GB (default) 100 SA00006E80L HYNIX H5TC4G63AFR-11C 2GB 101 SA000077K0L Micron MT41J256M16HA-093G 2GB Memory ID RV87 10K_0402_5% @ DBG_VREFG AUX1P AUX1N 10K_0402_5% 10K_0402_5% AM26 AK26 S K VDD1DI VSS1DI GENERICA GENERICB GENERICC GENERICD GENERICE NC#AJ9 NC#AL9 PLL/CLOCK XTALIN XTALOUT RV29 @ RV59 @ AC14 AB16 10nF PS_2 r fo AB13 W8 W9 W7 AD10 AJ9 AL9 +1.8VGS RV154 @ L6 L5 L3 L1 K4 K7 AF24 CV28 VCCB B1 B2 GND JET@ 33_0402_5% SVI2_SVD SVI2_SVC 2 VCCA A1 A2 DIR 01 JET@ U1 JET@ 33_0402_5% GPU_VID3 RV75 GPU_VID3_GPIO_15 GPU_VID1 RV76 GPU_VID1_GPIO_20 DIR JET@ 33_0402_5% CV170 0.1U_0402_10V7K 00 82nF PS_2[5:4]=00 SCL SDA PS_1[2] TRAP_BIF_CLK_PM_EN PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING 680nF RV89 10K_0402_5% @ 1 RV72 10K_0402_5% JET@ RV71 10K_0402_5% JET@ 0.1U_0402_10V7K JET@ B U6 U10 T10 U8 VGA_SMB_DA3 U7 VGA_SMB_CK3 T9 VGA_AC BATT T8 PCC_GPIO_6 T7 P10 P4 P2 N6 +VGA_CORE N5 N3 Y9 N1 GPU_VID3 M4 R6 THM_ALERT# W10 M2 GPIO19_CTF P8 GPU_VID1 P7 N8 AK10 AM10 N7 PEG_CLKREQ#_R JET@ PS_1 RV83 16.2K_0402_1% TOPAZ@ 2 CV166 +VGA_CORE @ RV11 8.45K_0402_1% Bitd [5:4] A Strap Name : Cap (nF) V4 U5 PS_0[5] AUD_PORT_CONN_PINSTRAP[0] PS_1[1] STRAP_BIF_GEN3_EN_A PS_1[5:4]=11 +1.8VGS +1.8VGS Capacitor Divider Lookup Lable +3VGS +3VGS 111 AK8 AL7 +3VGS R1 R3 110 NC PS_1[3:1]=000 I2C 1 @ T223 @ T224 10k 4.75k 0402 1% resistors are equired AJ7 AH6 ADM1032ARMZ_MSOP8 @ T222 3.4k @ PS_0[4] N/A 2 101 0.68U_0402_10V D+ NC#W3 NC#V2 100 5.62k PS_0[3] ROM_CONFIG[2] DIS@ RV9 2K_0402_1% 1 VDD1 NC#AA5 NC#AA6 4.99k 3.24k THM_ALERT# AA5 AA6 UV3 NC#AC5 NC#AC6 4.53k CV29 PS_0[2] ROM_CONFIG[1] 1000P_0402_50V7K @ NC#V4 NC#U5 011 AC6 AC5 NC#W6 NC#V6 4.99k W6 V6 6.98k PS_0 PS_0[1] ROM_CONFIG[0] NC#AK8 NC#AL7 THM_ALERT# DIS@ RV58 4.7K_0402_5% DIS@ CV10 0.1U_0402_16V4Z 4.7K_0402_5% 010 DIS@ +3VGS NC#AJ7 NC#AH6 AK6 AM5 001 2k RV146 +3VGS NC#AK6 NC#AM5 DPB AK5 AM3 2k 4.53k 0.68U_0402_10V +3VGS NC#AK5 NC#AM3 AK3 AK1 8.45k 0.68U_0402_10V VGA_SMB_CK3 QV1A DMN66D0LDW-7 2N SOT363-6 DIS@ NC#AK3 NC#AK1 DVO AH3 AH1 000 Strap Name : S EC_SMB_CK2 D NC#AH3 NC#AH1 4.75k A NC#AG3 NC#AG5 DPA NC DIS@ RV8 8.45K_0402_1% G QV1B DMN66D0LDW-7 2N SOT363-6 DIS@ DBG_DATA16 DBG_DATA15 DBG_DATA14 DBG_DATA13 DBG_DATA12 DBG_DATA11 DBG_DATA10 DBG_DATA9 DBG_DATA8 DBG_DATA7 DBG_DATA6 DBG_DATA5 DBG_DATA4 DBG_DATA3 DBG_DATA2 DBG_DATA1 DBG_DATA0 AG3 AG5 PS_0[5:4]=11 VGA_SMB_DA3 N9 L9 AE9 Y11 AE8 AD9 AC10 AD7 AC8 AC7 AB9 AB8 AB7 AB4 AB2 Y8 Y7 AE6 AE5 AD2 AD4 1 1 1 1 1 1 1 1 @ T201 @ T202 @ T203 @ T204 @ T205 @ T206 @ T207 @ T208 @ T209 @ T210 @ T211 @ T212 @ T213 @ T214 @ T215 @ T216 @ T217 AF2 AF4 +1.8VGS PS_0[3:1]=001 Bitd [3:1] R_pd (ohm) DIS@ S EC_SMB_DA2 NC#AF2 NC#AF4 D R_pu (ohm) RV6 45.3K_0402_1% G RV5 45.3K_0402_1% DIS@ Resistor Divider Lookup Lable U? 1 @ UV1B RV88 10K_0402_5% TOPAZ@ P/N C +VGA_CORE RV60 TOPAZ@ 0_0603_5% AC11 AC13 AD13 AD11 AD20 AC20 TOPAZ@ RV158 TOPAZ@ RV159 FB_GND FB_VDDC VSSSENSE_VGA VCCSENSE_VGA 0_0402_5% 0_0402_5% AE16 AD16 AC1 AC3 +VGA_CORE GPIO28_FDO TSVDD TSVSS VCCSENSE_VGA VSSSENSE_VGA @ RV161 @ RV160 0_0402_5% 0_0402_5% 0.1U_0402_10V6K CV21 DIS@ +3VGS RV21 JET@ 2160856030-A0_FCBGA631 10K_0402_5% ? 1 +3VGS RV147 DIS@ 2 4.7K_0402_5% +3VGS VGA_AC BATT D QV8A DMN66D0LDW-7_SOT363-6 DIS@ D Enable MLPS DIS@ 10K_0402_5% RV148 G D PACIN# RV91 10K_0402_5% TOPAZ@ D S RV149 0_0402_5% @ CVT90 0.1U_0402_10V7K TOPAZ@ ACIN_65W RV90 PCC_GPIO_6 G ACIN S DIS@ QV8B DMN66D0LDW-7_SOT363-6 2 2 OCP_L OCP_L 1K_0402_5% TOPAZ@ Peak Current Control (PCC) CKT Reversed Compal Secret Data Security Classification Issued Date 2014/03/26 Deciphered Date 2015/03/31 Title Compal Electronics, Inc TOPAZ_MSIC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: LA-B016P Sheet Monday, October 20, 2014 Rev 0.1 48 of 56 +5VALW +3VS @ 2 G D RV26 @ DGPU_PWR_EN# 10K_0402_5% G 0.1U_0402_10V7K @ +1.35VS_VGA TO +1.35V_MEM_GFX RV27 B 0_0603_1% 280mA C t n e d i f n o C l ia @ +DP_VDDC 1U_0402_6.3V4Z DIS@ r fo 0_0603_1% CV33 RV30 SHORT DEFAULT AG15 AG16 AF16 AG17 AG18 AG19 AF14 S K +VGA_PCIE +1.35V_MEM_GFX @ UV1G U? NC/DP POWER DP POWER 1 @ No Use GPU Display Port outpud +DP_VDDR 1U_0402_6.3V4Z DIS@ @ +1.35VS_VGA B F D _ 370mA (HDMI) 188mA (Display Port) +1.8VGS CV27 QV4 2N7002K_SOT23-3 S @ CV25 DIS@ CV26 10U_0603_6.3V6M DIS@ QV3 2N7002K_SOT23-3 DIS@ S CV34 G 0.1U_0402_10V7K 270K_0402_5% DIS@ CV24 RV25 PXS_PWREN D RV24 470_0603_5% @ RV23 DIS@ DGPU_PWR_EN# 10K_0402_5% 2 0.1U_0402_10V7K DIS@ CV23 D S DIS@ QV2 DIS@ AO3413_SOT23-3 10U_0603_6.3V6M CV22 JUMP_43X79 A +3VGS J514 DIS@ RV22 51K_0402_5% 0.1U_0402_10V6K DIS@ +3VS TO +3VGS AG20 AG21 AF22 AG22 AD14 AG14 AH14 AM14 AM16 AM18 AF23 AG23 AM20 AM22 AM24 AF19 AF20 AE14 AF17 DP_VDDR#AG15 DP_VDDR#AG16 DP_VDDR#AF16 DP_VDDR#AG17 DP_VDDR#AG18 DP_VDDR#AG19 DP_VDDR#AF14 NC#AE11 NC#AF11 NC#AE13 NC#AF13 NC#AG8 NC#AG10 DP_VDDC#AG20 DP_VDDC#AG21 DP_VDDC#AF22 DP_VDDC#AG22 DP_VDDC#AD14 NC#AF6 NC#AF7 NC#AF8 NC#AF9 DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR NC#AE1 NC#AE3 NC#AG1 NC#AG6 NC#AH5 NC#AF10 NC#AG9 NC#AH8 NC#AM6 NC#AM8 NC#AG7 NC#AG11 DPAB_CALR 2160856030-A0_FCBGA631 NC#AE10 AE11 AF11 AE13 AF13 AG8 AG10 AF6 AF7 AF8 AF9 AE1 AE3 AG1 AG6 AH5 AF10 AG9 AH8 AM6 AM8 AG7 AG11 AE10 ? +1.8VS TO +1.8VGS +1.8VS +1.8VGS @ UV1E AA27 AB24 AB32 AC24 AC26 AC27 AD25 AD32 AE27 AF32 AG27 AH32 K28 K32 L27 M32 N25 N27 P25 P32 R27 T25 T32 U25 U27 V32 W25 W26 W27 Y25 Y32 M6 N13 N16 N18 N21 P6 P9 R12 R15 R17 R20 T13 T16 T18 T21 T6 U15 U17 U20 U9 V13 V16 V18 Y10 Y15 Y17 Y20 R11 T11 AA11 M12 N11 V11 @ GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VSS_MECH VSS_MECH VSS_MECH A3 A30 AA13 AA16 AB10 AB15 AB6 AC9 AD6 AD8 AE7 AG12 AH10 AH28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B6 B8 C1 C32 E28 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6 C A32 AM1 AM32 2160856030-A0_FCBGA631 ? J9 D SHORT DEFAULT B 2MM D U? GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND A Compal Secret Data Security Classification Issued Date 2014/03/26 Deciphered Date 2015/03/31 Compal Electronics, Inc TOPAZ_Power/GND Size Document Number Rev Custom 0.1 LA-B016P of Monday, October 20, 2014 49 56 Date: Sheet Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 1 C +DP_VDDR +DP_VDDC +3VGS VDDR3 0 1uF 0.1uF (1@) e d i f n o C 25mA D +1.8VGS CV83 CV82 LV7 DIS@ BLM15BD121SN1D_0402 2 130mA CV39 0.1U_0402_10V6K DIS@ BIF_VDDC BIF_VDDC L8 75mA VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI SPLL_PVDD 100mA +SPLL_VDDC H8 J7 R21 U21 +BIF_VDDC CV60 CV59 1U_0402_6.3V4Z DIS@ CV58 2 +VGA_PCIE RV31 2 +BIF_VDDC 2 2 CV80 CV79 CV78 CV77 0_0805_1% @ SPLL_VDDC SPLL_PVSS 2160856030-A0_FCBGA631 +VDDCI 3.5A (DDR3) ISOLATED CORE I/O H7 1U_0402_6.3V4Z DIS@ CV57 1 1U_0402_6.3V4Z @ 1U_0402_6.3V4Z @ CV76 1U_0402_6.3V4Z DIS@ CV75 CV168 1U_0402_6.3V4Z DIS@ MPLL_PVDD +SPLL_PVDD 1U_0402_6.3V4Z DIS@ CV38 CV46 +VGA_CORE TBD 1.4A +VGA_PCIE LV8 DIS@ BLM15BD121SN1D_0402 B PLL +MPLL_PVDD 1U_0402_6.3V4Z DIS@ r fo 1U_0402_6.3V4Z DIS@ CV66 CV65 CV64 l ia t n 10uF 10U_0603_6.3V6M DIS@ 1 1U_0402_6.3V4Z DIS@ 13mA 10U_0603_6.3V6M DIS@ +TSVDD LV6 DIS@ BLM15BB221SN1D_2P CV81 +1.8VGS 1U_0402_6.3V4Z DIS@ 1 CV74 13mA 1U_0402_6.3V4Z DIS@ VDD_CT CV73 1U_0402_6.3V4Z DIS@ CV72 (300mA) VDDR4 VDDR4 VDDR4 VDDR4 CV71 V12 Y12 U12 VDDR3 VDDR3 VDDR3 VDDR3 1U_0402_6.3V4Z DIS@ I/O AA17 AA18 AB17 AB18 AA15 N15 N17 R13 R16 R18 Y21 T12 T15 T17 T20 U13 U16 U18 V21 V15 V17 V20 Y13 Y16 Y18 AA12 M11 N12 U11 1U_0402_6.3V4Z DIS@ VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC CORE M13 M15 M16 M17 M18 M20 M21 N20 2 CV87 75mA CV93 SPLL_PVDD S K 0.1U_0402_10V6K DIS@ CV92 1U_0402_6.3V4Z DIS@ CV91 130mA 10U_0603_6.3V6M DIS@ MPLL_PVDD 0.1U_0402_10V6K DIS@ 1U_0402_6.3V4Z @ 1 CV86 1 0.1U_0402_10V6K DIS@ 100mA +VDDR3 VDD_CT VDD_CT VDD_CT VDD_CT POWER PCIE_PVDD 25mA LV4 DIS@ BLM15BD121SN1D_0402 1U_0402_6.3V4Z DIS@ 0.1uF CV85 1uF 1U_0402_6.3V4Z DIS@ 10uF +3VGS +1.8VGS AA20 AA21 AB20 AB21 2 1U_0402_6.3V4Z DIS@ CV84 10U_0603_6.3V6M DIS@ 0.1U_0402_10V6K DIS@ 10U_0603_6.3V6M DIS@ VDDR1 1.5A +VDD_CT 1U_0402_6.3V4Z DIS@ BLM15BD121SN1D_0402 CV63 0.01uF 0.1uF CV62 2.2uF CV61 10uF 1U_0402_6.3V4Z DIS@ +1.35V_MEM_GFX LEVEL TRANSLATION +VGA_PCIE 2.5A CV70 LV3 DIS@ @ L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22 10U_0603_6.3V6M DIS@ B F D _ 13mA +1.8VGS B PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC 1U_0402_6.3V4Z DIS@ 2 CV56 2 1U_0402_6.3V4Z DIS@ CV69 2 10U_0603_6.3V6M DIS@ CV90 +PCIE_PVDD AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26 CV89 AM30 1U_0402_6.3V4Z DIS@ CV53 CV52 CV50 CV49 CV42 CV41 CV48 CV47 CV40 CV51 NC#AB23 NC#AC23 NC#AD24 NC#AE24 NC#AE25 NC#AE26 NC#AF25 NC#AG26 1U_0402_6.3V4Z DIS@ PCIE_PVDD VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 10U_0603_6.3V6M DIS@ MEM I/O H13 H16 H19 J10 J23 J24 J9 K10 K23 K24 K9 L11 L12 L13 L20 L21 L22 0.01U_0402_16V7K CV178 DIS@ 0.01U_0402_16V7K CV177 DIS@ 100mA SPLL_VDDC 0.01U_0402_16V7K CV176 DIS@ 0.01U_0402_16V7K CV175 DIS@ 0.01U_0402_16V7K CV174 DIS@ 0.1U_0402_10V6K DIS@ 1.4A 0.1U_0402_10V6K DIS@ BIF_VDDC 0.1U_0402_10V6K DIS@ 0.1U_0402_10V6K DIS@ (1@) 0.1U_0402_10V6K DIS@ (1@) 2.2U_0402_6.3V6M DIS@ 2.5A 2.2U_0402_6.3V6M DIS@ PCIE_VDDC 2.2U_0402_6.3V6M DIS@ 0.1uF 2.2U_0402_6.3V6M DIS@ 1uF 2.2U_0402_6.3V6M DIS@ 10uF 10U_0603_6.3V6M DIS@ +VGA_PCIE CV45 1.5A CV44 10U_0603_6.3V6M DIS@ CV43 10U_0603_6.3V6M DIS@ 3.5A PCIE VDDCI A +1.8VGS 100mA U? CV55 @ UV1D +1.35V_MEM_GFX CV54 10U_0603_6.3V6M @ 10 (2@) 10U_0603_6.3V6M DIS@ (1@) CV68 0.1uF CV67 TBD 1uF 10U_0603_6.3V6M DIS@ VDDC 10uF 10U_0603_6.3V6M DIS@ +VGA_CORE CV88 A 10U_0603_6.3V6M DIS@ DIS@ LV25 BLM15BD121SN1D_0402 LV26 BLM15BD121SN1D_0402 +VGA_CORE C DIS@ ? D Compal Secret Data Security Classification Issued Date 2014/03/26 Deciphered Date 2015/03/31 Compal Electronics, Inc TOPAZ_Power Size Document Number Rev Custom 0.1 LA-B016P of Monday, October 20, 2014 50 56 Date: Sheet Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A M_DA[63 0] M_MA[15 0] M_DQM[7 0] M_DQS[7 0] M_DQS#[7 0] M_MA[15 0] M_DQM[7 0] M_DQS[7 0] M_DQS#[7 0] @ UV1C U? DIS@ RV32 40.2_0402_1% DIS@ RV33 40.2_0402_1% +MVREFSA +MVREFDA DIS@ CV95 1U_0402_6.3V4Z DIS@ RV35 100_0402_1% 2 DIS@ CV94 1U_0402_6.3V4Z B DRAM_RST# DIS@ RV37 10_0402_1% DRAM_RST DIS@ RV36 49.9_0402_1% 2 DIS@ RV38 5.1K_0402_1% @ CV97 68P_0402_50V8J DIS@ CV96 120P_0402_50V8J Place close to GPU (within 25mm) and place componment close to each other C t n RV39 e d i f n o C RV40 @ RV41 @ 51.1_0402_1% 51.1_0402_1% l ia +MVREFDA +MVREFSA DIS@ CV98 @1 CV99 @1 120_0402_1% DRAM_RST 0.1U_0402_16V4Z 0.1U_0402_16V4Z Route 50ohms single-ended/100ohm diff and keep short debug only, for clock observation,if not need, DNI D K27 J29 H30 H32 G29 F28 F32 F30 C30 F27 A28 C28 E27 G26 D26 F25 A25 C25 E25 D24 E23 F23 D22 F21 E21 D20 F19 A19 D18 F17 A17 C17 E17 D16 F15 A15 D14 F13 A13 C13 E11 A11 C11 F11 A9 C9 F9 D8 E7 A7 C7 F7 A5 E5 C3 E1 G7 G6 G1 G3 J6 J1 J3 J5 K26 J26 J25 K25 DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 DQA0_16 DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31 DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8 DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31 GDDR5/DDR3 MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA0_8/MAA_13 MAA0_9/MAA_15 MEMORY INTERFACE M_DA0 M_DA1 M_DA2 M_DA3 M_DA4 M_DA5 M_DA6 M_DA7 M_DA8 M_DA9 M_DA10 M_DA11 M_DA12 M_DA13 M_DA14 M_DA15 M_DA16 M_DA17 M_DA18 M_DA19 M_DA20 M_DA21 M_DA22 M_DA23 M_DA24 M_DA25 M_DA26 M_DA27 M_DA28 M_DA29 M_DA30 M_DA31 M_DA32 M_DA33 M_DA34 M_DA35 M_DA36 M_DA37 M_DA38 M_DA39 M_DA40 M_DA41 M_DA42 M_DA43 M_DA44 M_DA45 M_DA46 M_DA47 M_DA48 M_DA49 M_DA50 M_DA51 M_DA52 M_DA53 M_DA54 M_DA55 M_DA56 M_DA57 M_DA58 M_DA59 M_DA60 M_DA61 M_DA62 M_DA63 +1.35V_MEM_GFX +1.35V_MEM_GFX M_DA[63 0] GDDR5/DDR3 DIS@ RV34 100_0402_1% MAA1_0/MAA_8 MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12 MAA1_5/MAA_BA2 MAA1_6/MAA_BA0 MAA1_7/MAA_BA1 MAA1_8/MAA_14 MAA1_9/RSVD WCKA0_0/DQMA0_0 WCKA0B_0/DQMA0_1 WCKA0_1/DQMA0_2 WCKA0B_1/DQMA0_3 WCKA1_0/DQMA1_0 WCKA1B_0/DQMA1_1 WCKA1_1/DQMA1_2 WCKA1B_1/DQMA1_3 EDCA0_0/QSA0_0 EDCA0_1/QSA0_1 EDCA0_2/QSA0_2 EDCA0_3/QSA0_3 EDCA1_0/QSA1_0 EDCA1_1/QSA1_1 EDCA1_2/QSA1_2 EDCA1_3/QSA1_3 MVREFDA MVREFSA NC#J25 MEM_CALRP0 ADBIA0/ODTA0 ADBIA1/ODTA1 CLKA0 CLKA0B CLKA1 CLKA1B RASA0B RASA1B CASA0B CASA1B CSA0B_0 CSA0B_1 CSA1B_0 CSA1B_1 CKEA0 CKEA1 L10 K8 L7 DRAM_RST M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA13 M_MA15 J14 K14 J11 J13 H11 G11 J16 L15 G14 L16 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_BA2 M_BA0 M_BA1 M_MA14 E32 E30 A21 C21 E13 D12 E3 F4 M_DQM0 M_DQM1 M_DQM2 M_DQM3 M_DQM4 M_DQM5 M_DQM6 M_DQM7 H28 C27 A23 E19 E15 D10 D6 G5 M_DQS0 M_DQS1 M_DQS2 M_DQS3 M_DQS4 M_DQS5 M_DQS6 M_DQS7 H27 A27 C23 C19 C15 E9 C5 H4 M_DQS#0 M_DQS#1 M_DQS#2 M_DQS#3 M_DQS#4 M_DQS#5 M_DQS#6 M_DQS#7 L18 K16 VRAM_ODT0 VRAM_ODT1 H26 H25 M_CLK0 M_CLK#0 G9 H9 M_CLK1 M_CLK#1 G22 G17 M_RAS#0 M_RAS#1 G19 G16 M_CAS#0 M_CAS#1 H22 J22 M_CS#0 G13 K13 M_CS#1 K20 J17 M_CKE0 M_CKE1 G25 H10 M_WE#0 M_WE#1 B F D _ S K DDBIA0_0/QSA0_0B DDBIA0_1/QSA0_1B DDBIA0_2/QSA0_2B DDBIA0_3/QSA0_3B DDBIA1_0/QSA1_0B DDBIA1_1/QSA1_1B DDBIA1_2/QSA1_2B DDBIA1_3/QSA1_3B r fo K17 J20 H23 G23 G24 H24 J19 K19 G20 L17 WEA0B WEA1B M_BA2 M_BA0 M_BA1 VRAM_ODT0 VRAM_ODT1 @ A B M_CLK0 M_CLK#0 M_CLK1 M_CLK#1 M_RAS#0 M_RAS#1 M_CAS#0 M_CAS#1 M_CS#0 M_CS#1 M_CKE0 M_CKE1 M_WE#0 M_WE#1 C CLKTESTA CLKTESTB 2160856030-A0_FCBGA631 ? D Compal Secret Data Security Classification Issued Date 2014/03/26 Deciphered Date 2015/03/31 Compal Electronics, Inc TOPAZ_MEM Size Document Number Rev Custom 0.1 LA-B016P of Monday, October 20, 2014 51 56 Date: Sheet Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 5 Memory Partition A - Lower 32 bits M_DA[63 0] M_DA[63 0] M_MA[15 0] M_DQM[7 0] M_DQS[7 0] M_DQS#[7 0] M_MA[15 0] M_DQM[7 0] M_DQS[7 0] M_DQS#[7 0] +1.35V_MEM_GFX +1.35V_MEM_GFX 1 A D NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 D9 G7 K2 K8 N1 N9 R1 R9 B +1.35V_MEM_GFX A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 B1 B9 D1 D8 E2 E8 F9 G1 G9 C 96-BALL SDRAM DDR3 H5TC2G63FFR-11C FBGA 96P 1G@ 2G@ 1 1 CV179 CV173 CV132 CV131 CV130 CV129 CV128 CV127 CV126 CV125 CV124 CV118 CV172 CV171 CV117 1 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z DIS@ 0.1U_0402_10V6K DIS@ 0.1U_0402_10V6K DIS@ 0.1U_0402_10V6K DIS@ 0.1U_0402_10V6K DIS@ CV116 +1.35V_MEM_GFX U1407 side CV115 CV109 CV108 CV107 CV106 CV105 ZQ/ZQ0 J1 L1 J9 L9 +1.35V_MEM_GFX VDD VDD VDD VDD VDD VDD VDD VDD VDD 0.1U_0402_10V6K DIS@ RESET L8 M_DA8 M_DA14 M_DA9 M_DA12 M_DA10 M_DA15 M_DA11 M_DA13 0.1U_0402_10V6K DIS@ DRAM_RST# T2 D7 C3 C8 C2 A7 A2 B8 A3 0.1U_0402_10V6K DIS@ DQSL DQSU M_DA30 M_DA27 M_DA31 M_DA24 M_DA29 M_DA26 M_DA28 M_DA25 @ DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 0.1U_0402_10V6K DIS@ G3 B7 DML DMU 1U_0402_6.3V4Z DIS@ M_DQS#3 M_DQS#1 DQSL DQSU 1U_0402_6.3V4Z DIS@ E7 D3 ODT/ODT0 CS/CS0 RAS CAS WE E3 F7 F2 F8 H3 H8 G2 H7 A SA00006E80L U1406 side 1U_0402_6.3V4Z DIS@ M_DQM3 M_DQM1 256MX16 H5TC4G63AFR-11C FBGA 96P 0.1U_0402_10V6K DIS@ F3 C7 CK CK CKE/CKE0 UV6 +1.35V_MEM_GFX 0.1U_0402_10V6K DIS@ 1U_0402_6.3V4Z DIS@ 1U_0402_6.3V4Z DIS@ 1U_0402_6.3V4Z DIS@ 10U_0603_6.3V6M DIS@ CV104 e d i f n o C 1U_0402_6.3V4Z DIS@ 2G@ M_DQS3 M_DQS1 BA0 BA1 BA2 CV123 t n SA00006E80L K1 L2 J3 K3 L3 DIS@ RV47 243_0402_1% 96-BALL SDRAM DDR3 H5TC2G63FFR-11C FBGA 96P 1G@ 256MX16 H5TC4G63AFR-11C FBGA 96P 1U_0402_6.3V4Z DIS@ DIS@ CV102 0.01U_0402_16V7K CV103 1U_0402_6.3V4Z DIS@ l ia VRAM_ODT0 M_CS#0 M_RAS#0 M_CAS#0 M_WE#0 CV122 UV5 RV49 40.2_0402_1% DIS@ RV48 40.2_0402_1% DIS@ J7 K7 K9 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 1U_0402_6.3V4Z DIS@ C VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ M_CLK0 M_CLK#0 M_CKE0 1U_0402_6.3V4Z DIS@ NC/ODT1 NC/CS1 NC/CE1 NCZQ1 S K r fo B1 B9 D1 D8 E2 E8 F9 G1 G9 0.1U_0402_10V6K DIS@ J1 L1 J9 L9 DIS@ RV46 243_0402_1% 1 M_CLK0 M_CLK#0 ZQ/ZQ0 M2 N8 M3 VREFCA VREFDQ RESET L8 M_BA0 M_BA1 M_BA2 CV121 DQSL DQSU T2 DRAM_RST# VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CV120 G3 B7 DML DMU A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 1U_0402_6.3V4Z DIS@ M_DQS#2 M_DQS#0 A1 A8 C1 C9 D2 E9 F1 H2 H9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU +1.35V_MEM_GFX CV119 E7 D3 ODT/ODT0 CS/CS0 RAS CAS WE M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15 B F D _ 1U_0402_6.3V4Z DIS@ M_DQM2 M_DQM0 CK CK CKE/CKE0 DIS@ CV101 0.1U_0402_10V6K 1U_0402_6.3V4Z DIS@ F3 C7 M_DQS2 M_DQS0 2 K1 L2 J3 K3 L3 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD M8 H1 +FBA_VREF1 +1.35V_MEM_GFX BA0 BA1 BA2 CV114 VRAM_ODT0 M_CS#0 M_RAS#0 M_CAS#0 M_WE#0 UV6 DIS@ RV45 4.99K_0402_1% 0.1U_0402_10V6K DIS@ VRAM_ODT0 M_CS#0 M_RAS#0 M_CAS#0 M_WE#0 J7 K7 K9 M_DA5 M_DA3 M_DA4 M_DA1 M_DA6 M_DA0 M_DA7 M_DA2 CV113 M_CLK0 M_CLK#0 M_CKE0 D7 C3 C8 C2 A7 A2 B8 A3 0.1U_0402_10V6K DIS@ M_CLK0 M_CLK#0 M_CKE0 M2 N8 M3 CV112 M_BA0 M_BA1 M_BA2 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 M_DA17 M_DA23 M_DA21 M_DA22 M_DA18 M_DA19 M_DA16 M_DA20 0.1U_0402_10V6K DIS@ B M_BA0 M_BA1 M_BA2 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 CV111 VREFCA VREFDQ E3 F7 F2 F8 H3 H8 G2 H7 0.1U_0402_10V6K DIS@ DIS@ CV100 0.1U_0402_10V6K N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 CV110 M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15 1U_0402_6.3V4Z DIS@ 1 0.1U_0402_10V6K DIS@ UV5 M8 H1 +FBA_VREF0 DIS@ RV44 4.99K_0402_1% DIS@ RV43 4.99K_0402_1% 10U_0603_6.3V6M DIS@ DIS@ RV42 4.99K_0402_1% D Compal Secret Data Security Classification Issued Date 2014/03/26 Deciphered Date 2015/03/31 Compal Electronics, Inc TOPAZ_VRAM A Lower Size Document Number Rev Custom 0.1 LA-B016P of Monday, October 20, 2014 52 56 Date: Sheet Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 5 Memory Partition A - Upper 32 bits +1.35V_MEM_GFX +1.35V_MEM_GFX 1 DIS@ RV51 4.99K_0402_1% D DRAM_RST# T2 DQSL DQSU RESET L8 ZQ/ZQ0 J1 L1 J9 L9 DIS@ RV57 243_0402_1% NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 96-BALL SDRAM DDR3 H5TC2G63FFR-11C FBGA 96P 1G@ C 256MX16 H5TC4G63AFR-11C FBGA 96P SA00006E80L +1.35V_MEM_GFX 2 2 2 2 2 2 2 2 2 CV183 CV182 CV165 CV159 CV151 CV181 CV180 CV150 CV149 1 1U_0402_6.3V4Z DIS@ 10U_0603_6.3V6M DIS@ 1U_0402_6.3V4Z DIS@ 0.1U_0402_10V6K DIS@ CV148 CV147 CV146 CV145 CV144 CV143 B1 B9 D1 D8 E2 E8 F9 G1 G9 U1409 side 0.1U_0402_10V6K DIS@ A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 +1.35V_MEM_GFX 0.1U_0402_10V6K DIS@ B 2G@ 0.1U_0402_10V6K DIS@ 0.1U_0402_10V6K DIS@ 1U_0402_6.3V4Z DIS@ 0.1U_0402_10V6K DIS@ CV142 CV141 CV138 CV137 CV139 2 G3 B7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS U1408 side 1U_0402_6.3V4Z DIS@ 1U_0402_6.3V4Z DIS@ 1U_0402_6.3V4Z DIS@ 1U_0402_6.3V4Z DIS@ 10U_0603_6.3V6M DIS@ 1U_0402_6.3V4Z DIS@ CV136 e d i f n o C 1U_0402_6.3V4Z DIS@ 2G@ CV140 t n SA00006E80L M_DQS#6 M_DQS#7 DML DMU +1.35V_MEM_GFX A1 A8 C1 C9 D2 E9 F1 H2 H9 0.1U_0402_10V6K DIS@ l ia 256MX16 H5TC4G63AFR-11C FBGA 96P E7 D3 UV8 96-BALL SDRAM DDR3 H5TC2G63FFR-11C FBGA 96P 1G@ C M_DQM6 M_DQM7 DQSL DQSU CV158 UV7 r fo 0.1U_0402_10V6K DIS@ DIS@ CV135 0.01U_0402_16V7K B1 B9 D1 D8 E2 E8 F9 G1 G9 0.1U_0402_10V6K DIS@ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ F3 C7 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ CV164 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 M_DQS6 M_DQS7 ODT/ODT0 CS/CS0 RAS CAS WE 0.1U_0402_10V6K DIS@ J1 L1 J9 L9 K1 L2 J3 K3 L3 0.1U_0402_10V6K DIS@ ZQ/ZQ0 S K A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VRAM_ODT1 M_CS#1 M_RAS#1 M_CAS#1 M_WE#1 CK CK CKE/CKE0 A +1.35V_MEM_GFX CV163 RESET 2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU L8 DIS@ RV56 243_0402_1% DML DMU DRAM_RST# T2 DRAM_RST# RV55 40.2_0402_1% DIS@ RV54 40.2_0402_1% DIS@ DQSL DQSU B F D _ A1 A8 C1 C9 D2 E9 F1 H2 H9 J7 K7 K9 CV162 G3 B7 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ +1.35V_MEM_GFX M_CLK1 M_CLK#1 M_CKE1 B2 D9 G7 K2 K8 N1 N9 R1 R9 0.1U_0402_10V6K DIS@ M_DQS#4 M_DQS#5 ODT/ODT0 CS/CS0 RAS CAS WE VDD VDD VDD VDD VDD VDD VDD VDD VDD CV161 E7 D3 CK CK CKE/CKE0 BA0 BA1 BA2 0.1U_0402_10V6K DIS@ M_DQM4 M_DQM5 VDD VDD VDD VDD VDD VDD VDD VDD VDD M_DA60 M_DA59 M_DA63 M_DA56 M_DA62 M_DA57 M_DA61 M_DA58 CV160 F3 C7 BA0 BA1 BA2 D7 C3 C8 C2 A7 A2 B8 A3 @ +1.35V_MEM_GFX B2 D9 G7 K2 K8 N1 N9 R1 R9 M_DA49 M_DA53 M_DA51 M_DA54 M_DA50 M_DA55 M_DA48 M_DA52 0.1U_0402_10V6K DIS@ M_DQS4 M_DQS5 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 0.1U_0402_10V6K DIS@ K1 L2 J3 K3 L3 M2 N8 M3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 0.1U_0402_10V6K DIS@ VRAM_ODT1 M_CS#1 M_RAS#1 M_CAS#1 M_WE#1 1 M_CLK1 M_CLK#1 VRAM_ODT1 M_CS#1 M_RAS#1 M_CAS#1 M_WE#1 J7 K7 K9 M_BA0 M_BA1 M_BA2 DIS@ CV134 0.1U_0402_10V6K CV157 B M_CLK1 M_CLK#1 M_CKE1 M_DA41 M_DA44 M_DA43 M_DA45 M_DA42 M_DA46 M_DA40 M_DA47 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 1U_0402_6.3V4Z DIS@ M_CLK1 M_CLK#1 M_CKE1 D7 C3 C8 C2 A7 A2 B8 A3 1U_0402_6.3V4Z DIS@ M2 N8 M3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DIS@ RV53 4.99K_0402_1% CV156 M_BA0 M_BA1 M_BA2 M_BA0 M_BA1 M_BA2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 CV155 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 VREFCA VREFDQ 1U_0402_6.3V4Z DIS@ M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15 1U_0402_6.3V4Z DIS@ M_DQS#[7 0] DIS@ CV133 0.1U_0402_10V6K N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 1 DIS@ RV52 4.99K_0402_1% M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15 CV154 M_DQS#[7 0] M_DQS[7 0] M8 H1 CV153 M_DQM[7 0] DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 +FBA_VREF3 1U_0402_6.3V4Z DIS@ M_DQS[7 0] VREFCA VREFDQ CV152 M_DQM[7 0] UV8 +FBA_VREF3 1U_0402_6.3V4Z DIS@ M_MA[15 0] M_DA38 M_DA36 M_DA37 M_DA35 M_DA39 M_DA32 M_DA34 M_DA33 1U_0402_6.3V4Z DIS@ M_MA[15 0] E3 F7 F2 F8 H3 H8 G2 H7 M8 H1 +FBA_VREF2 M_DA[63 0] M_DA[63 0] A UV7 DIS@ RV50 4.99K_0402_1% D Compal Secret Data Security Classification Issued Date 2014/03/26 Deciphered Date 2015/03/31 Compal Electronics, Inc TOPAZ_VRAM A Upper Size Document Number Rev Custom 0.1 LA-B016P of Monday, October 20, 2014 53 56 Date: Sheet Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 5 4 D Power-Up/Down Sequence All the ASIC supplies must reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred The maximum slew rate on all rails is 50 mV/µs The external pull ups on the DDC/AUX signals (if applicable) should ramp up before or after both VDDC and VDD_CT have ramped up B F D _ VDDC and VDD_CT should not ramp up simultaneously For example, VDDC should reach 90% before VDD_CT starts to ramp up (or vice versa) For power down, reversing the ramp-up sequence is recommended C PLT_RST# VDDR3(3.3VGS) PCH PCIE_VDDC(0.95V) VDDR1(1.5VGS) S K GPIO50 GPIO54 TACH0/GPIO17 VDDC/VDDCI(1.12V) VDD_CT(1.8V) PERSTb REFCLK B Straps Reset t n Straps Valid Global ASIC Reset e d i f n o C l ia r fo AND GATE @ D C PLT_RST_VGA# GPU PERSTB DGPU_HOLD_RST DGPU_PWR_EN DGPU_PWROK NOT DGPU_PWR_EN# +3VS_VGA +3VS MOS B +0.95VS_VGA +3VS Regulator PWM B+ +1.8VS +1.8VS_VGA MOS MOS +1.5VS +VGA_CORE +1.5VS_VGA T4+16clock CPU part A A Compal Secret Data Security Classification Issued Date 2014/03/26 Deciphered Date 2015/03/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Compal Electronics, Inc TOPAZ_NOTE Document Number Rev 0.1 LA-B016P Monday, October 20, 2014 Sheet 54 of 56 D B F D _ C B t n A e d i f n o C l ia @ D C S K r fo B A Compal Secret Data Security Classification Issued Date 2014/03/26 Deciphered Date 2015/03/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Compal Electronics, Inc Reserved Page Document Number Rev 0.1 LA-B016P Monday, October 20, 2014 Sheet 55 of 56 D B F D _ C B t n A e d i f n o C l ia @ D C S K r fo B A Compal Secret Data Security Classification Issued Date 2014/03/26 Deciphered Date 2015/03/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Compal Electronics, Inc Reserved Page Document Number Rev 0.1 LA-B016P Monday, October 20, 2014 Sheet 56 of 56 ... DDI1_LANE_N0 DDI1_LANE_P0 DDI1_LANE_N1 DDI1_LANE_P1 DDI1_LANE_N2 DDI1_LANE_P2 DDI1_LANE_N3 DDI1_LANE_P3 DDI1_LANE_N0 DDI1_LANE_P0 DDI1_LANE_N1 DDI1_LANE_P1 DDI1_LANE_N2 DDI1_LANE_P2 DDI1_LANE_N3... 68P_0402_50V8J 1 LAD0 LAD1 LAD2 LAD3 LFRAME R2331 10K_0402_5% G EMI PCH_SPI_CLK_R AU14 AW12 AY12 AW11 AV12 LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# +3VS HASWELL_MCP_E UC1G LPC_LAD0 LPC_LAD1... Port4 MINI Card (WLAN) Port5 Touch Screen Panel Port6 Card Reader Port7 Camera PCI EXPRESS Lane Lane Lane 10/100 LAN Lane MINI Card (WLAN) Lane PEG (AMD JET/TOBAZ) B CLOCK SIGNAL Lane CLKOUT_PCIE0