12 sơ đồ nguyên lý ipad 4

www.mobile-files.com www.witesomtesla.com MLB R8296 R5991 R8297 C5991 820-3249-TOP R5990 C1021 J3700 C3787 C3764 R3750 C3757 J5950 R6111_RF R6112_RF R6107_RF R5932 R5933 R5962 R5961 C3756 C3754 C3753 C3752 C3751 C3713 C3746 C3767 C3744 C3743 C3742 U3740 C3747 C8143 C8103 R0730 U5902 R1200 R1201 R1202 R2242 C2232 C2206 C2202 C2230 R2290 C2203 C2247 C2245 R2280 L2212 C2251 C2242 C2243 C2244 C2246 C2248 R8269 R8262 R2281 C2249 R8240 R8235 R8231 C5551 C3609 R2282 L2222 L5570 C5640 R5640 C5582 C5583 C5552 C5584 C5553 U5620 C5630 U5630 R5631 R5630 C5550 C5580 C5562 C0605 U5640 L5530 R5641 C5572 L5510 R0932 C5670 L5580 L5560 C5570 C5573 L5500 U5650 U5660 C5671 C5561 C5571 C5661 C5581 CA150 C11F0 R0842 CA197 C3612 C0637 C0982 C0981 C1163 R2283 C2250 C0821 C0842 C1178 C1177 C1175 R8257 C3109 C3111 C1608 R3107 C1143 C1119 C1108 R0930 C0612 CA192 R0931 R0933 C0613 C0633 C0634 R0613 C2280 R2284 L2232 C5560 R0610 C2281 R2285 U3100 C1168 C0608 C0930 R6108_RF R0708 R0716 R0710 R0709 R0700 R0701 R0702 R1206 R1205 R1204 C1429 C1428 C1416 C1329 C1328 C1317 C1142 C1194 C1109 C1125 C1121 C0955 CA152 R0920 C0950 R1260 C1110 C1148 C1147 C2282 R2286 L2202 C5563 C0933 C11A1 C1181 C11B1 C1199 DZ5760 R3740 R3070 R9021 C5766 R9031 C11A0 C2283 R2287 R8282 C11B0 R3601 U3003 C2284 R2241 CA153 C0980 C2285 L2242 C8157 C2271 C2286 R2240 C8139 C2221 C2287 L5550 U5600 R0705 R0706 U5610 J6000 C2270 R8261 C2253 C2220 L2201 R8270 C2233 C2241 C0907 C0820 C3690 R8239 C1167 C3604 R8265 C0961 CA194 C1176 C3006 R8232 R9001 C7526 R8227 C8130 C7522 C2239 C8236 C7523 U2200 R8280 C7524 FL7500 L5520 U6104_RF C7527 C7525 U3101 L2210 C6108_RF R0831 C2240 RF C1602 L5540 1_ C1606 L2200 C6 11 R1691 C5660 RF C1691 C3613 0_ R1690 C1690 R3120 19 R6114_RF R6105_RF C1605 FL0910 FL5740 J6190_RF C3611 C0904 C1171 R0843 C6 C6102_RF C6101_RF C8235 C8234 R6113_RF C6103_RF C0935 C0908 C0843 RF C3710 C3745 L8109 U6102_RF C0960 C1172 R1207 2_ C6109 L6111_RF C8256 CA198 C1145 19 C3763 C6110_RF C8110 R1421 C1450 C0903 C1185 C1174 C6 C3766 FL3741 C3761 C3720 C3755 C3768 C3760 C6104_RF C1609 C1415 C1410 R1405 C0635 C1159 C1160 C1169 C6191_RF C3750 R3743 U5670 R0719 C3783 C3749 FL3740 C3740 U5903 C1601 C1418 C1417 C0636 C11C0 R0900 R0940 C11D0 C11D1 C0621 C0609 C1158 C11C1 C1157 C1161 C1180 C11E1 R0942 C0631 C1173 C1184 C11E0 C0630 R9011 R9010 R0941 R0911 C0811 C0909 C1149 C0632 CA187 C1154 C1182 C1183 C0614 CA199 C1150 C1460 C1190 R1406 C1162 C1164 C1151 C1170 C1118 C1155 C1156 C1152 C1130 C1133 C0957 C0931 C1139 R8218 C1138 C1153 C0812 C3780 R3744 R1654 C0607 C1135 C0810 FL3751 R3745 R5935 C1604 C0606 C1122 CA188 C3711 C3721 C1607 C1117 C1131 C1106 CA193 R0950 CA195 R0604 C1123 C1134 C1116 U1400 C1114 C1128 C0953 R0921 C0929 C1126 C8109 C5936 C3712 C3722 C3723 R3753 R3742 L8225 C8233 C1600 C1124 C1132 C1140 C0928 C0934 C1107 C1141 FL0911 C0956 C1120 C1137 C1129 CA189 C0623 C0952 C0932 C1113 C1136 L6190_RF C1115 J6191_RF C0910 R1210 CA151 C0951 U6101_RF R1211 C0927 Q9010 Q8201 L6192_RF L6191_RF CA190 CA196 C1198 CA191 C1166 Q8203 C6107_RF C5733 C5731 C1352 C0924 C1165 C8156 L5730 C1191 C1361 R1352 CA186 R1321 C8188 Q8200 C8158 R8293 R1351 C1316 C1310 C1332 R1320 C8159 R8291 C8291 D5990 C1315 D8228 C8232 C8105 R8290 Q8202 C8160 C8187 C8189 C8140 C8167 C8141 C5732 C8137 C8207 C8282 R8203 C8204 C5710 DZ5710 C8215 C8146 C8135 C8153 C8190 C8136 C8191 R8100 C5741 FL5710 DZ5740 C5730 C8145 C8281 C8151 C5711 C8214 R8172 C8212 C8132 C3770 C5740 C8238 C8133 C8221 C8201 C8172 C8223 C8170 C8174 C8173 C8171 C3771 C8217 C8138 C8290 R8292 R8173 C8239 C8134 C8266 C1452 C1111 C8168 C8251 C8210 C8161 C8209 C8169 C8162 Q8104 C8192 C3773 C8267 C8193 C8206 L3750 C3759 R1655 C8196 C8220 C3772 L8104 R8196 R8219 D8230 R1452 C1195 R8170 C1461 R1306 C1196 C5990 FL5990 C3748 C3786 FL3750 MLB R1451 R1305 C1350 C1193 Q9020 R9020 C8112 C5722 R5790 C5721 U1300 R9030 C5960 R5960 C1360 Q9030 R8116 Q8123 R8130 DZ8120 C5783 C5900 C5750 L5757 C8111 C0651 DZ5901 DZ5900 DZ5902 DZ5903 L5930 C8102 C8123 R0703 R0704 Y0602 C8104 R0650 R0711 R0651 R0713 R0720 R0714 L5701 L5700 L5931 L8110 J3011 DZ5990 C5765 FL5750 L8103 L8102 820-3249-BOT DZ5750 R0721 R3741 L3740 R9000 R5934 C5920 C8142 R1220 R0717 C0650 R8216 C8122 R1203 C3070 DZ5792 C8121 C8155 C8120 CA185 C5910 C8263 C3741 C1179 J3010 L8255 C8144 R1209 DZ5791 C8148 R0652 R1208 J5401 C8262 C8147 R0718 J6051 J5400 R9002 C8124 L8101 L8100 C3784 R3755 R3754 R3752 R0621 U3750 R0622 C3758 R3751 R6109_RF R0608 R0620 R0715 R3071 L8229 C8108 C8119 R0643 C0640 R0640 R0832 U3007 C1102 R0642 C1103 D8258 C8226 C1610 C1620 C8152 C8149 Y8138 C3005 C3007 C1630 U8100 C1331 C8118 C1318 C1054 C1095 R1054 C8107 R1355 C1326 C1363 C1333 C1313 C1412 C1419 C1434 C1413 C1435 C1426 C1402 C3112 C1456 R1455 R1095 R3180 R3171 C3105 U3010 U3009 C3041 C3050 R3025 U3060 C3602 C3615 C3009 R2205 R3030 R8281 C8101 C3781 C3606 C1020 C3788 C1624 C8165 C8264 C3104 C1634 C8131 L8105 C8265 C3102 C1614 LED9000 C8164 C8237 C1325 R1021 C8292 R3181 R3155 R3033 R3101 C3103 C8166 C8163 R8222 C3031 L8112 C8117 C8100 U0600 C1101 C3030 R3031 J5900 C8126 C8125 L8106 C8154 C1303 C1414 C5941 C1309 R5930 R5931 C5943 C5944 C1057 R1053 R3066 C1305 U5900 C5934 C5933 C1321 R1354 C1100 C1319 C1430 L8111 L8107 C8195 C1302 R1353 C1362 C1354 C1403 C1404 C3053 C3605 L3620 R3614 C1301 C1323 C1322 C5930 C5932 C1320 C5935 C5940 C5942 C1330 C5931 R5929 D8100 C1304 C1306 C1308 R1056 C1056 R1356 U1600 D3000 C1104 C3101 C3607 C3620 C3608 C3632 C3631 R3631 R3620 R1055 C1058 R1022 R1096 C3603 C3614 R1420 C1105 C3601 C3630 R1084 C1314 C1096 U3600 C1409 R3032 C3618 C3617 L3000 4R7 R3160 C3616 R3630 R1454 U3000 R3190 C1085 C1084 C1411 C3108 R1083 C1405 C1407 C1307 C1334 C1401 C1421 C3106 C3000 R3612 C3002 C3001 R1456 C3110 C3192 C3107 R3611 R3613 R3610 R3640 C3191 R3173 R3012 C1463 C3060 R0760 C3691 J6050 C1454 R3009 R3060 C3610 R1453 C1422 C3008 J2200 C1462 C1431 C1432 J7500 C1420 C1423 C1335 C1324 C1356 C1022 R1020 C1327 R10234 C1312 C1425 C1311 C1424 C1023 C1408 C1197 C1613 C1427 C1633 C8194 C1623 C1612 C1433 C1622 C1192 C1632 C1625 C1144 C1635 C1406 C1615 C1650 C8113 C1651 C1631 C8114 C1652 C1621 C1611 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ REV ECN DESCRIPTION OF REVISION A 0001554595 CK APPD DATE iPad 4th Gen PRODUCTION RELEASED 2012-07-26 LAST_MODIFIED=Thu Jul 26 10:29:36 2012 D D PDF CSA CONTENTS SYNC MASTER DATE (SYSTEM DRI) TABLE_TABLEOFCONTENTS_HEAD 1 Table of Contents N/A N/A BLOCK DIAGRAM: SYSTEM N/A N/A BOM TABLES N/A N/A AP: MAIN N/A N/A AP: I/Os N/A N/A AP: NAND N/A N/A AP: TV,DP,MIPI N/A N/A 10 AP: DDR N/A N/A 11 AP: POWER N/A N/A 12 AP: MISC & ALIASES N/A N/A TABLE_TABLEOFCONTENTS_HEAD (AMANDA) TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM (AMANDA) TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM (TERRY) (TERRY) TABLE_TABLEOFCONTENTS_ITEM (TERRY) TABLE_TABLEOFCONTENTS_ITEM (TERRY) TABLE_TABLEOFCONTENTS_ITEM C 10 33 (AMANDA) TABLE_TABLEOFCONTENTS_ITEM 32 (TERRY) SYNC MASTER DATE (SYSTEM DRI) 83 PMU: ADRIANA PAGE MADHAVI 12/06/2011 (MADHAVI) 90 DEBUG/MISC MLB 11/09/2011 (AMANDA) 93 TEST/HOLES/FIDUCUALS N/A N/A (AMANDA) 121 POWER ALIASES N/A N/A (MADHAVI) 150 CONSTRAINTS: MLB RULES MIKE 11/30/2011 (AMANDA) 151 CONSTRAINTS: LOW SPEED BUS MIKE 11/30/2011 (AMANDA) 152 CONSTRAINTS: DISPLAY/AUDIO MIKE 11/30/2011 (AMANDA) 153 CONSTRAINTS: DDR/FMI MIKE 11/30/2011 (AMANDA) 154 CONSTRAINTS: POWER / GND MIKE 11/30/2011 (AMANDA) TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 31 (TERRY) TABLE_TABLEOFCONTENTS_ITEM PDF CSA CONTENTS (AMANDA) 34 35 TABLE_TABLEOFCONTENTS_ITEM 36 TABLE_TABLEOFCONTENTS_ITEM 37 TABLE_TABLEOFCONTENTS_ITEM 38 TABLE_TABLEOFCONTENTS_ITEM 39 C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 11 13 DDR AND N/A N/A 14 DDR AND N/A N/A 16 NAND N/A N/A (TERRY) TABLE_TABLEOFCONTENTS_ITEM 12 (TERRY) TABLE_TABLEOFCONTENTS_ITEM 13 (AMANDA) TABLE_TABLEOFCONTENTS_ITEM 14 (AMANDA) 21 ALIASES N/A N/A 22 VIDEO: EDP CONNECTOR N/A N/A 30 GRAPE: GROUNDHOG,CONN,BOOST N/A N/A 31 GRAPE: Z1, Z2 N/A N/A 36 AUDIO: L81 CODEC N/A N/A 37 AUDIO: SPEAKER AMP N/A N/A 54 SENSOR FLEX CONN N/A N/A 55 SENSOR CONN FILTERS N/A N/A 56 SENSOR CONN FILTERS N/A N/A 57 E75 DOCK SUPPORT N/A N/A 58 IO FLEX CONN N/A N/A 59 TRISTAR N/A N/A 60 CONNECTOR: CELLULAR N/A N/A 61 WIFI/BT N/A N/A 75 POWER: BATTERY CONNECTOR MADHAVI 12/06/2011 (MADHAVI) 81 PMU: ADRIANA PAGE MADHAVI 12/06/2011 (MADHAVI) 82 PMU: ADRIANA PAGE MADHAVI 12/06/2011 TABLE_TABLEOFCONTENTS_ITEM 15 (JOE) TABLE_TABLEOFCONTENTS_ITEM 16 (AMANDA) TABLE_TABLEOFCONTENTS_ITEM 17 (AMANDA) TABLE_TABLEOFCONTENTS_ITEM 18 (TERRY) TABLE_TABLEOFCONTENTS_ITEM 19 (TERRY) TABLE_TABLEOFCONTENTS_ITEM 20 B (MARK) B TABLE_TABLEOFCONTENTS_ITEM 21 (MARK) TABLE_TABLEOFCONTENTS_ITEM 22 (MARK) TABLE_TABLEOFCONTENTS_ITEM 23 (JOE) TABLE_TABLEOFCONTENTS_ITEM 24 (JOE) TABLE_TABLEOFCONTENTS_ITEM 25 (JOE) TABLE_TABLEOFCONTENTS_ITEM 26 (AMANDA) TABLE_TABLEOFCONTENTS_ITEM 27 (MATT) TABLE_TABLEOFCONTENTS_ITEM 28 TABLE_TABLEOFCONTENTS_ITEM 29 TABLE_TABLEOFCONTENTS_ITEM 30 A (MADHAVI) TABLE_TABLEOFCONTENTS_ITEM DRAWING TITLE A X140 MLB DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: DRAWING THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED MLB DRAWING 051-9385 REVISION A.0.0 BRANCH PAGE OF 154 SHEET 1 OF 39 SIZE D Z2 SPI3 CSA 31 D ISP_I2C1 MIPI1C FF CAMERA ISP_I2C0 MIPI0C REAR CAMERA VGA FLEX VA5 FLEX D HSIC1_1 GROUNDHOG CSA 30 Z1 UART3 CSA 31 UART4 I2S2 LPDDR2 DISPLAY/ TOUCH PANEL BT_I2S CSA 61 BALI CSA 13-14 EDP CELLULAR/ GPS HSIC1 HSIC3 IPC C WIFI/BT ANT WIFI/BT UART1 PRIMARY CELLULAR ANT DIVERSITY CELLULAR ANT USART USART BACKLIGHT NOT ON WIFI-ONLY CONFIG C GPS ANT SIM CARD CSA 60 UART5 HALL EFF BUTTON FLEX PMU ADRIANA BATTERY USB11 USB2.0 UART2 UART6 CSA 75 HALL EFF HOME BUTTON DWI I2C0 CSA 81,82 TRISTAR B I2S1 AUDIO CODEC I2C1 PROX SENSOR COMPASS SENSOR BOARD SENSOR BOARD L81 I2C2 GYRO ACCELEROMETER B CSA 59 FMI0 FMI1 SPI1 SPI I2S0 ASP I2S3 I2S4 XSP MBUS AMP SPEAKER AMP NC HP ALS CSA 36 A SENSOR BOARD SENSOR BOARD VGA FLEX SYNC_MASTER=N/A SYNC_DATE=N/A PAGE TITLE NAND FLASH MIC1 BLOCK DIAGRAM: SYSTEM MIC2 DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED CSA 16 051-9385 REVISION A.0.0 BRANCH PAGE OF 154 SHEET OF 39 SIZE D A SCH AND BOARD P/N Page Notes TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_ITEM 051-9385 SCH,MLB,X140 SCH1 CRITICAL 820-3249 PCBF,MLB,X140 PCB1 CRITICAL Power aliases required by this page: TABLE_5_ITEM (NONE) Signal aliases required by this page: (NONE) BOM options provided by this page: D D SOC BOM OPTIONS COMMON ALTERNATE 16GB_PROD: 16GB CONFIG 32GB_PROD: 32GB CONFIG 64GB_PROD: 64 GB CONFIG DEV: DEV BOARD ONLY MLB: MLB BOARD ONLY MLB_A: WIFI ONLY CONFIG MLB_B: CELLULAR CONFIG MLB_C: CELLULAR CONFIG MLB_D: LEGACY CELLULAR CONFIG MLB_E: LEGACY CELLULAR CONFIG TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL U0600 CRITICAL REFERENCE DESIGNATOR(S) CRITICAL U8100 CRITICAL REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_ITEM 343S0598 IC,SOC,H5G,FCBGA1089,0.5MM PMU TABLE_5_HEAD PART# QTY DESCRIPTION BOM OPTION TABLE_5_ITEM 343S0622 IC,PMU,ADRIANA,D2018A1,FCBGA SDRAM TABLE_5_HEAD PART# QTY DESCRIPTION BOM OPTION TABLE_5_ITEM 333S0636 LPDDR2,533MHZ,512MB,SAMSUNG,35NM U1300,U1400 CRITICAL TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS BASIC COMMON,ALTERNATE C TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER 333S0637 333S0636 U1300,U1400 LPDDR2,533MHZ,HYNIX,38NM 333S0638 333S0636 U1400,U1400 LPDDR2,533MHZ,ELPIDA,38NM TABLE_BOMGROUP_ITEM BOM OPTION REF DES COMMENTS: TABLE_ALT_ITEM C TABLE_ALT_ITEM NAND 16GB FLASH CONFIGURATIONS TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION U1600 CRITICAL 16GB_PROD REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION U1600 CRITICAL 32GB_PROD TABLE_5_ITEM 335S0878 TOSHIBA PPN1.5 16GB 32GB FLASH CONFIGURATIONS MECHANICAL PARTS TABLE_5_HEAD PART# QTY DESCRIPTION TABLE_5_ITEM 335S0879 TABLE_5_HEAD B PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL PD_FENCE_NAND CRITICAL PD_FENCE_LARGE CRITICAL PD_FENCE_AMP CRITICAL TOSHIBA PPN1.5 32GB BOM OPTION B TABLE_5_ITEM NAND 806-4195 FENCE,NAND,TOP,MLB,X140 SOC/PMU 806-3493 FENCE,LARGE,TOP,MLB,X140 AUDIO 806-3956 FENCE,AMP,MLB,X140 GRAPE 806-4196 FENCE,1,BTM,MLB,X140 PD_FENCE_BTM1 CRITICAL MEMORY 806-3492 FENCE,2,BTM,MLB,X140 PD_FENCE_BTM2 CRITICAL TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM 64GB FLASH CONFIGURATIONS TABLE_5_HEAD PART# BARCODE LABEL/EEEE CODES QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION U1600 CRITICAL 64GB_PROD REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION U1600 CRITICAL 128GB_PROD TABLE_5_ITEM 335S0880 TOSHIBA PPN1.5 64GB TABLE_5_HEAD REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 825-7838 PART# QTY EEEE FOR 639-3736 (MLB A 16G) DESCRIPTION EEEE_F1WD CRITICAL EEEE_MLB_A_16G 825-7838 EEEE FOR 639-3737 (MLB A 32G) EEEE_F1WH CRITICAL EEEE_MLB_A_32G 825-7838 EEEE FOR 639-3738 (MLB A 64G) EEEE_F1W8 CRITICAL EEEE_MLB_A_64G 825-7838 EEEE FOR 639-4176 (MLB A 128G) EEEE_F80Q CRITICAL EEEE_MLB_A_128G 825-7838 EEEE FOR 639-3263 (MLB B 16G) EEEE_DWKG CRITICAL EEEE_MLB_B_16G TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM 128GB FLASH CONFIGURATIONS TABLE_5_ITEM TABLE_5_HEAD PART# TABLE_5_ITEM 825-7838 EEEE FOR 639-3739 (MLB B 32G) EEEE_F1W7 CRITICAL EEEE_MLB_B_32G 825-7838 EEEE FOR 639-3740 (MLB B 64G) EEEE_F1WC CRITICAL EEEE_MLB_B_64G 825-7838 EEEE FOR 639-4177 (MLB B 128G) EEEE_F80P CRITICAL EEEE_MLB_B_128G 825-7838 EEEE FOR 639-3741 (MLB C 16G) EEEE_F1WG CRITICAL EEEE_MLB_C_16G 825-7838 EEEE FOR 639-3742 (MLB C 32G) EEEE_F1WF CRITICAL EEEE_MLB_C_32G 825-7838 EEEE FOR 639-3743 (MLB C 64G) EEEE_F1W9 CRITICAL EEEE_MLB_C_64G 825-7838 EEEE FOR 639-4178 (MLB C 128G) EEEE_F80R CRITICAL EEEE_MLB_C_128G DESCRIPTION TABLE_5_ITEM 335S0912 TABLE_5_ITEM A QTY TOSHIBA PPN1.5 128GB TABLE_5_ITEM SYNC_MASTER=N/A TABLE_5_ITEM PAGE TITLE SYNC_DATE=N/A BOM TABLES TABLE_5_ITEM DRAWING NUMBER TABLE_5_ITEM Apple Inc TABLE_5_ITEM R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9385 REVISION A.0.0 BRANCH PAGE OF 154 SHEET OF 39 SIZE D A A 39 0% 1/32W MF 01005 C0605 0.1UF 20% 4V X5R 01005 34 0.00 1 C0606 0.1UF 8.2PF 20% 4V X5R 01005 PP1V8_PL0_F VOLTAGE=1.8V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR C0607 MAX_NECK_LENGTH=3MM +/-0.5PF 16V NP0-C0G-CERM 01005 =PP1V0_HSIC_H5 C0630 0.01UF 34 C0631 0.01UF 10% 6.3V X5R 01005 10% 6.3V X5R 01005 1 C0637 C0621 8.2PF 10% 01005 10% 6.3V X5R 01005 C0612 0.01UF +/-0.5PF 8.2PF C0608 16V 6.3V NP0-C0G-CERM X5R +/-0.5PF 16V NP0-C0G-CERM 01005 01005 C0632 0.1UF 20% 6.3V X5R-CERM 01005 C0633 0.1UF C0634 0.1UF 20% 6.3V X5R-CERM 01005 C0635 0.01UF 20% 6.3V X5R-CERM 01005 10% 6.3V X5R 01005 C0636 8.2PF 8.2PF +/-0.5PF 16V NP0-C0G-CERM 01005 34 =PP3V3_USB_H5 34 CHANGE TO USB 3.3V TO AVOID ISSUE FOUND IN H5P: FAILURE IN CHARGE DETECT CIRCUIT AT 3.0V-5% C0614 1UF +/-0.5PF 10% 6.3V 16V NP0-C0G-CERM CERM 01005 402 BCM4330 WLAN 34 10 BI 36 14 BI NOSTUFF =PP1V8_H5 R0608 5% MF 1/32W 01005 =PP1V8_H5 36 26 BI 36 26 BI 10 100K 5% 1/32W 01005 R0621 36 100K 36 5% 1/32W 01005 36 25 36 25 R0622 10 5% 1/32W 01005 PP0600 SM R0640 P4MM PP 7.5K 10 5% 1/32W MF 01005 IN U0600 BALI-H5G USB 1.1 BASEBAND/TRISTAR NEEDED IF WE GO TO 9600 AN17 HSIC3_DATA AM17 HSIC3_STB TRISTAR H17 JTAG_SEL JTAG_AP_SEL NC_JTAG_AP_TRTCK NO_TEST=TRUE JTAG_AP_TRST_L TP_JTAG_AP_TDO JTAG_AP_TDI JTAG_AP_TMS JTAG_AP_TCK J16 K16 H16 F16 F17 J17 XI0 J33 XO0 K33 OMIT_TABLE C0613 8.2PF 0.1UF +/-0.5PF 20% 01005 01005 MLB USB_ANALOGTEST R25 JTAG_TRTCK JTAG_TRST* JTAG_TDO JTAG_TDI JTAG_TMS JTAG_TCK USB_VBUS P28 USB_ID P27 USB_BRICKID P31 MLB OPTION USED FOR FF R0652 AP_WDOG 0.00 36 36 XTAL_AP_24M_I XTAL_AP_24M_O USB_AP_P USB_AP_N AP_WDOG_RESET_IN OUT 0% 1/32W MF 01005 25 C R0650 USB11_DP E32 USB11_AP_BBMUX_P BI USB11_DM D32 USB11_AP_BBMUX_N BI USB_DP M33 USB_DM N33 34 4V 16V NP0-C0G-CERM2 X5R WDOG C18 BGA SYM OF 12 AP_TESTMODE IN D18 TESTMODE USB_REXT T30 L31 FUSE1_FSRC 10 =PP1V8_H5 39 30 26 25 8MA C0623 25 36 25 36 BI 25 36 BI 25 36 CRITICAL 1.00M 1% 1/32W MF 01005 Y0602 SM-2 R0651 22 5% 1/32W MF 01005 24.000MHZ-16PF-60PPM 36 AP_24M_O CRITICAL 1 C0650 USB_AP_VBUS0 NC_USB_ID NC_USB_BRICKID NO_TEST=TRUE CRITICAL C0651 22PF 5% 16V CERM 01005 NC_USB_ANALOGTEST NO_TEST=TRUE 22PF PPVBUS_USB 5% 16V CERM 01005 29 NO_TEST=TRUE 100K 34 10 IN 2.7MA PER PIN R31 HSIC2_DATA NC_HSIC2_DATA NO_TEST=TRUE T31 HSIC2_STB NC_HSIC2_STB NO_TEST=TRUE HSIC3_BB_DATA HSIC3_BB_STB R0620 39 36 10 R33 HSIC1_DATA T33 HSIC1_STB HSIC1_WLAN_DATA HSIC1_WLAN_STB MDM9615 BB 100K 34 10 36 14 11.9MA PER PIN 5.4MA USB_DVDD R30 30MA USB_VDD330 P26 USB_ASW_VDD18 N26 FMI CHANNEL AT 1.8V VSEL25_I2C2 HIGH => I2C2 3.0V VSEL25_SPI3 HIGH => SPI3 3.0V B 34 10 B =PP1V8_H5 NOSTUFF R0760 100K 5% 1/20W MF 201 16 GPIO_GRAPE_IRQ_L BUTTON PULLUPS I2C PULL-UPS R0708 34 32 30 23 220K =PP1V8_S2R_MISC GPIO_PMU_KEEPACT GPIO_FORCE_DFU GPIO_DFU_STATUS GPIO_BB_RADIO_ON_L GPIO_WLAN_HSIC_HOST_RDY GPIO_SPKAMP_RST_L 5% 1/20W MF 201 GPIO_BTN_HOME_L R0709 =PP1V8_ALWAYS 34 A 30 20 GPIO_BTN_ONOFF_L 220K 5% 1/20W MF 201 R0710 34 32 30 20 220K =PP1V8_S2R_MISC GPIO_BTN_SRL_L GPIO_SPKAMP_KEEPALIVE 5% 1/20W MF 201 R0711 100K 5% 1/20W MF 201 R0713 100K 5% 1/20W MF 201 NOSTUFF R0714 100K 5% 1/20W MF 201 NOSTUFF R0715 100K 5% 1/20W MF 201 R0718 100K 5% 1/20W MF 201 R0719 100K 5% 1/20W MF 201 NEED TO CHARACTERIZE RISE TIME AND SIZE THESE RESISTORS 30 32 21 20 5 26 34 10 5 14 36 R0701 19 2.2K 5% 1/32W MF 01005 19 R0721 100K 5% 1/20W MF 201 PP3V0_SENSOR_FLT =PP1V8_H5 36 30 25 19 I2C0_SDA_1V8 36 30 25 19 I2C0_SCL_1V8 36 22 I2C1_SDA_1V8 36 22 I2C1_SCL_1V8 36 22 I2C2_SDA_3V0 36 22 I2C2_SCL_3V0 R0702 2.2K 5% 1/32W MF 01005 R0703 1.00K 5% 1/32W MF 01005 R0704 1.00K 5% 1/32W MF 01005 R0705 1.00K 5% 1/32W MF 01005 R0706 1.00K 5% 1/32W MF 01005 SYNC_MASTER=N/A PAGE TITLE SYNC_DATE=N/A AP: I/Os DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9385 REVISION A.0.0 BRANCH PAGE OF 154 SHEET OF 39 SIZE D A D D 34 AB8 AB10 AB12 AB14 AB16 AB18 AB19 AB21 AB23 AB25 AB30 AC1 AC3 AC9 AC11 AC13 AC15 AC17 AC20 AC22 AC24 AD8 AD10 AD12 AD14 AD16 AD18 AD19 AD21 AD23 AD25 AE4 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE17 AE22 AE30 AE32 A6 AF3 AF16 AG2 AG16 AG17 AG25 C B U0600 BALI-H5G BGA SYM 12 OF 12 OMIT_TABLE VSS VSS AH5 AH10 AH15 AH16 AH17 AH30 AH32 P24 AJ17 AJ27 AK2 AK8 AK14 AK17 AH1 AL3 AL7 AL10 AL13 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL1 AL29 AM1 AM2 AM6 AM9 AM12 AM15 AM32 AM33 AN1 AN2 AL33 T20 AN11 AN14 AN32 AN33 AN3 AN31 AN6 C1 =PP1V8_NAND_H5 R0832 100K 38 13 FMI1_CE0_L 38 13 FMI0_CE0_L R0831 100K 5% 1/32W MF 01005 5% 1/32W MF 01005 C 38 13 OUT 38 13 BI 38 13 BI 38 13 BI 38 13 BI 38 13 BI 38 13 BI 38 13 BI 38 13 BI FMI0_CE0_L NC_FMI0_CE1_L NC_FMI0_CE2_L NC_FMI0_CE3_L NC_FMI0_CE4_L NC_FMI0_CE5_L NC_FMI0_CE6_L NC_FMI0_CE7_L NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE FMI0_AD FMI0_AD FMI0_AD FMI0_AD FMI0_AD FMI0_AD FMI0_AD FMI0_AD 38 13 OUT 38 13 OUT 38 13 OUT 38 13 OUT 38 13 OUT 34 6 AN29 AM30 AL28 AL27 AJ32 AJ31 AM31 AL30 FMI0_CEN0 FMI0_CEN1 FMI0_CEN2 FMI0_CEN3 FMI0_CEN4 FMI0_CEN5 FMI0_CEN6 FMI0_CEN7 AM29 AK33 AJ30 AK31 AH28 AJ29 AN30 AH27 FMI0_IO0 FMI0_IO1 FMI0_IO2 FMI0_IO3 FMI0_IO4 FMI0_IO5 FMI0_IO6 FMI0_IO7 CKPLUS_WAIVE=PDIFPR_BADTERM AK29 NC_FMI0_RE NO_TEST=TRUE AJ28 FMI0_ALE AH29 FMI0_CLE AK32 FMI0_WE_L AK30 FMI0_RE_L AL31 FMI0_DQS NC_FMI0_DQSN NO_TEST=TRUE AL32 AG27 U0600 BALI-H5G BGA SYM OF 12 OMIT_TABLE FMI0_WENN FMI0_ALE FMI0_CLE FMI0_WEN FMI0_REN FMI0_DQS FMI0_DQSN FMI0_DQVREF =PP1V8_NAND_H5 AF26 AB26 PVDDP_GRP1 PVDDP_GRP2 FMI_DQVREF_H5 AG28 FMI0_VREF FMI1_CEN0 FMI1_CEN1 FMI1_CEN2 FMI1_CEN3 FMI1_CEN4 FMI1_CEN5 FMI1_CEN6 FMI1_CEN7 AF29 AF30 AE29 AD30 AF27 AE27 AF28 AE28 FMI1_IO0 FMI1_IO1 FMI1_IO2 FMI1_IO3 FMI1_IO4 FMI1_IO5 FMI1_IO6 FMI1_IO7 AE33 AH33 AG33 AG30 AD31 AE31 AG29 AD29 FMI1_WENN FMI1_ALE FMI1_CLE FMI1_WEN FMI1_REN FMI1_DQS FMI1_DQSN FMI1_DQVREF FMI1_CE0_L NC_FMI1_CE1_L NC_FMI1_CE2_L NC_FMI1_CE3_L NC_FMI1_CE4_L NC_FMI1_CE5_L NC_FMI1_CE6_L NC_FMI1_CE7_L NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE OUT FMI1_AD FMI1_AD FMI1_AD FMI1_AD FMI1_AD FMI1_AD FMI1_AD FMI1_AD CKPLUS_WAIVE=PDIFPR_BADTERM AG31 NO_TEST=TRUE NC_FMI1_RE AJ33 FMI1_ALE AH31 FMI1_CLE AG32 FMI1_WE_L AF31 FMI1_RE_L AF32 FMI1_DQS AF33 NO_TEST=TRUE NC_FMI1_DQSN AD27 13 38 BI 13 38 BI 13 38 BI 13 38 BI 13 38 BI 13 38 BI 13 38 BI 13 38 BI 13 38 OUT 13 38 OUT 13 38 OUT 13 38 OUT 13 38 OUT 13 38 =PP1V8_NAND_H5 =PP1V8_VDDIO18_H5 PVDDP_GRP3 P25 PVDDP_GRP4 G19 PVDDP_GRP5 K24 FMI1_VREF AD28 R0842 51.1K 1% 1/32W MF 01005 34 A C0820 0.1UF 20% 4V X5R 01005 0.1UF FMI_DQVREF_H5 R0843 =PP1V8_NAND_H5 C0842 20% 4V X5R 01005 1% 1/32W MF 01005 34 51.1K 34 B 34 C0843 0.1UF 20% 4V X5R 01005 =PP1V8_VDDIO18_H5 C0821 0.1UF C0810 0.1UF 20% 4V X5R 01005 20% 4V X5R 01005 C0811 0.1UF 20% 4V X5R 01005 C0812 0.1UF 20% 4V X5R 01005 SYNC_MASTER=N/A PAGE TITLE SYNC_DATE=N/A AP: NAND DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9385 REVISION A.0.0 BRANCH PAGE OF 154 SHEET OF 39 SIZE D A 34 =PP1V0_DP_PAD_DVDD_H5 C0910 8.2PF +/-0.1PF% 25V CER 0201 =PP1V8_DP_H5 R0911 =PP1V8_EDP_H5 34 1 5% 1/20W MF 201 C0931 56PF 5% 6.3V NP0-C0G 01005 D 1 C0928 8.2PF C0929 8.2PF C0930 56PF C0932 0.22UF +/-0.5PF +/-0.5PF 5% 16V 16V 6.3V NP0-C0G-CERM NP0-C0G-CERM NP0-C0G 01005 01005 01005 20% 6.3V X5R 402 39 PP1V8_EDP_AVDD_AUX C0933 0.22UF C0927 0.1UF 56PF 20% 4V X5R 01005 C0934 0.22UF 34 C0924 5% 6.3V NP0-C0G 01005 20% 6.3V X5R 402 20% 6.3V X5R 402 =PP1V8_VDDIO18_H5 0.01UF 10% 6.3V X5R 01005 =PP1V0_EDP_PAD_DVDD_H5 34 C0909 0.1UF 10% 6.3V X5R 201 =PP1V8_VDDIO18_H5 VOLTAGE=1.8V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR C0955 0.1UF 10% 6.3V X5R 201 R0950 39 6.34K 1% 1/20W MF 201 10% 6.3V X5R 201 NC_DAC_AP_OUT2 K23 DAC_COMP OMIT_TABLE DAC_OUT1 F33 NO_TEST=TRUE NC_DAC_AP_OUT1 DP_HPD B18 NO_TEST=TRUE NC_DP_HPD NC_DP_AUX_P NC_DP_AUX_N 1UF C0981 0.01UF 10% 6.3V CERM 402 10% 6.3V X5R 01005 C0982 56PF 5% 6.3V NP0-C0G 01005 IN VOLTAGE=0.4V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR PP0V4_MIPI0D MAX_NECK_LENGTH=3MM C0960 37 15 OUT 37 15 OUT 37 15 OUT 37 15 OUT 37 15 OUT 37 15 OUT 37 15 OUT 37 15 OUT 37 15 OUT 37 15 OUT 2.2NF 10% 10V X5R-CERM 0201 =PP1V0_MIPI_H5 C0908 0.1UF C0903 0.1UF 10% 6.3V X5R 201 8.2PF IN 37 21 IN 37 21 IN 37 21 IN IN 37 21 IN MIPI0C_CAM_RF_DATA_P MIPI0C_CAM_RF_DATA_N AM22 MIPI0C_DPDATA0 AN22 MIPI0C_DNDATA0 MIPI0C_CAM_RF_DATA_P MIPI0C_CAM_RF_DATA_N AM21 MIPI0C_DPDATA1 AN21 MIPI0C_DNDATA1 NC_MIPI0C_CAM_RF_DATA_P NC_MIPI0C_CAM_RF_DATA_N NO_TEST=TRUE NC_MIPI0C_CAM_RF_DATA_P NC_MIPI0C_CAM_RF_DATA_N NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE BGA SYM OF 12 OMIT_TABLE AM19 MIPI0C_DPDATA2 AN19 MIPI0C_DNDATA2 R0930 1.00K 5% 1/32W MF 01005 ISP0_FLASH ISP0_PRE_FLASH ISP0_SCL ISP0_SDA M25 M31 AA27 U28 ISP1_FLASH ISP1_PRE_FLASH ISP1_SCL ISP1_SDA N25 SOCHOT1_L L30 SOCHOT0_L AA33 U30 R0931 1.00K 5% 1/32W MF 01005 NO_TEST=TRUE EDP_DATA_P A30 EDP_PAD_TX0P EDP_DATA_N A29 EDP_PAD_TX0N DP_PAD_TX0P D24 DP_PAD_TX0N D23 NO_TEST=TRUE EDP_DATA_P D28 EDP_PAD_TX1P EDP_DATA_N D27 EDP_PAD_TX1N DP_PAD_TX1P B24 DP_PAD_TX1N B23 NO_TEST=TRUE EDP_DATA_P B28 EDP_PAD_TX2P EDP_DATA_N B27 EDP_PAD_TX2N DP_PAD_TX2P C22 DP_PAD_TX2N C21 NO_TEST=TRUE EDP_DATA_P C26 EDP_PAD_TX3P EDP_DATA_N C25 EDP_PAD_TX3N DP_PAD_TX3P A22 DP_PAD_TX3N A21 NO_TEST=TRUE NO_TEST=TRUE C NC_DP_DATA_P NC_DP_DATA_N NO_TEST=TRUE NC_DP_DATA_P NC_DP_DATA_N NO_TEST=TRUE NC_DP_DATA_P NC_DP_DATA_N NO_TEST=TRUE NC_DP_DATA_P NC_DP_DATA_N NO_TEST=TRUE E28 EDP_PAD_R_BIAS R0921 4.99K F28 EDP_PAD_DC_TP 1% 1/32W MF 01005 10 34 R0932 R0933 1.00K 1.00K 5% 1/32W MF 01005 TP_EDP_AP_ANALOG_TEST 5% 1/32W MF 01005 NO_TEST=TRUE ISP0_CAM_RF_RST_L OUT NC_ISP0_CAM_RF_FLASH ISP0_CAM_RF_I2C_SCL OUT ISP0_CAM_RF_I2C_SDA BI DP_PAD_R_BIAS E23 DP_R_BIAS NOTE: 0.6V ANALOG REF DP_PAD_DC_TP F23 TP_DP_AP_ANALOG_TEST R0920 4.99K 1% 1/32W MF 01005 0.01UF 10% 6.3V X5R 01005 22 22 36 22 36 32 FRONT FACING CAM ISP1_CAM_FF_I2C_SCL ISP1_CAM_FF_I2C_SDA ISP1_CAM_FF_CLK_R MIPI1C_DPDATA1 AM25 MIPI1C_DNDATA1 AN25 0% 1/32W R0940 ISP1_CAM_FF_CLK ISP1_CAM_FF_SHUTDOWN_L MF 01005 MIPI1C_CAM_FF_DATA_P MIPI1C_CAM_FF_DATA_N NO_TEST=TRUE NO_TEST=TRUE 22 36 BI 22 36 OUT 22 36 OUT 22 OUT 22 36 OUT 22 SHUTDOWN IS ACTIVE HIGH SHUTDOWN IS ACTIVE LOW =PP1V8_H5 IN 21 37 IN 21 37 MIPI1C_CAM_FF_CLK_P MIPI1C_CAM_FF_CLK_N NOSTUFF R0942 IN 21 37 IN 21 37 SOCHOT1_L PULL-UP ON CSA 90 32 SOCHOT1_L SOCHOT0_L 10 34 R0941 100K NC_MIPI1C_CAM_FF_DATA_P NC_MIPI1C_CAM_FF_DATA_N AG20 AG21 AG22 AG23 AG24 MIPI1C_DPCLK AM24 MIPI1C_DNCLK AN24 0.00 OUT 100K 5% 1/32W MF 01005 5% 1/32W MF 01005 SYNC_MASTER=N/A PAGE TITLE SYNC_DATE=N/A AP: TV,DP,MIPI DRAWING NUMBER Apple Inc NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED NOSTUFF C0950 B R REAR FACING CAM U31 36 SENSOR1_CLK SENSOR1_RST T27 MIPI0C_DPCLK MIPI0C_DNCLK C0957 10% 6.3V X5R 01005 DP_PAD_AUXP A26 DP_PAD_AUXN A25 AP_EDP_R_BIAS NOSTUFF 0.01UF =PP1V8_H5 MIPI1C_DPDATA0 AM23 MIPI1C_DNDATA0 AN23 A 0.00 R0900 0% MF ISP0_CAM_RF_CLK 36 V31 ISP0_CAM_RF_CLK_R SENSOR0_CLK 01005 1/32W ISP0_CAM_RF_SHUTDOWN SENSOR0_RST U32 AM18 MIPI0C_DPDATA3 AN18 MIPI0C_DNDATA3 AM20 AN20 MIPI0C_CAM_RF_CLK_P MIPI0C_CAM_RF_CLK_N U0600 BALI-H5G MIPI_VSS 37 21 U27 MIPI_VSYNC 2MA PER PIN 10% 10V X5R-CERM 0201 EDP_AUX_P EDP_AUX_N C30 EDP_PAD_AUXP C29 EDP_PAD_AUXN NOTE: 0.6V ANALOG REF C0961 2.2NF 40MA MIPI_VDD10 37 21 NO_TEST=TRUE MAX_NECK_LENGTH=3MM +/-0.5PF 16V NP0-C0G-CERM 01005 B NC_MIPI_VSYNC_H5 VOLTAGE=0.4V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR PP0V4_MIPI1D C0904 AF20 AF21 AF22 AF23 AF24 10% 6.3V X5R 201 E18 EDP_HPD B25 B26 A27 A28 1UF 10% 6.3V CERM 402 MIPI0D_VREG_0P4V AH20 MIPI1D_VREG_0P4V AH23 C0935 MIPI0D_VDD18 AH19 MIPI1D_VDD18 AH24 3.3MA MIPI0D_VDD10_PLL AH21 3.3MA MIPI1D_VDD10_PLL AH22 34 EDP_HPD G24 DAC_AVSS18A C0980 15MA DAC_AVDD18A H24 NO_TEST=TRUE G23 DAC_AVSS18D 0201-1 C0907 0.1UF PP1V0_MIPI_PLL_F 15MA DAC_AVDD18D H23 NC_DAC_AP_OUT3 DAC_OUT2 E33 B22 DP_PAD_AVSS_AUX 39 A20 B20 E20 E21 NO_TEST=TRUE BGA SYM OF 12 DP_PAD_AVSS3 DP_PAD_AVSS1 DP_PAD_AVSS2 DP_PAD_AVSS0 MAX_NECK_LENGTH=3MM D25 D26 C27 C28 DAC_OUT3 D33 J24 DAC_IREF C20 F20 D20 F21 =PP1V0_MIPI_PLL_H5 0.01UF J23 DAC_VREF BALI-H5G 34 C0952 10% 6.3V X5R 01005 20% 4V X5R 01005 DAC_AP_IREF 37 15 34 U0600 65MA PER PIN B21 DP_PAD_AVSSP0 80-OHM-0.2A-0.4-OHM 34 =PP1V8_MIPI_H5 VOLTAGE=1.0V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR FL0910 DAC_AP_VREF DAC_AP_COMP C 65MA PER PIN 16MA DP_PAD_AVDD_AUX D22 10% 6.3V X5R 201 NOSTUFF DP_PAD_AVDD3 DP_PAD_AVDD2 DP_PAD_AVDD1 DP_PAD_AVDD0 0.1UF NOSTUFF 10MA DP_PAD_AVDDP0 D21 NOSTUFF C0956 22MA DP_PAD_AVDDX C23 TABLE_ALT_ITEM A23 DP_PAD_AVSSX RDAR://PROBLEM/11104943 15MA DP_PAD_DVDD C24 FL0910 A24 DP_PAD_DVSS ? 16MA EDP_PAD_AVDD_AUX D30 155S0359 B30 EDP_PAD_AVSS_AUX 155S0725 B29 EDP_PAD_AVSSP0 COMMENTS: C32 EDP_PAD_AVSSX REF DES D31 EDP_PAD_DVSS BOM OPTION EDP_PAD_AVSS3 EDP_PAD_AVSS2 EDP_PAD_AVSS1 EDP_PAD_AVSS0 ALTERNATE FOR PART NUMBER EDP_PAD_AVDD3 EDP_PAD_AVDD2 EDP_PAD_AVDD1 EDP_PAD_AVDD0 TABLE_ALT_HEAD PART NUMBER EDP_PAD_AVDDP0 D29 DAC_AP_COMP_FTR 10MA 0201 EDP_PAD_AVDDX B31 22MA 15MA EDP_PAD_DVDD C31 FL0911 240-OHM-0.2A-0.8-OHM =PP1V8_VDDIO18_H5 C0951 0.1UF MAX_NECK_LENGTH=3MM NOSTUFF 34 6 D 34 C0953 051-9385 REVISION A.0.0 BRANCH PAGE OF 154 SHEET OF 39 SIZE D A D C B 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 OUT 38 11 OUT 38 11 OUT 38 11 OUT 38 11 OUT 38 11 OUT 38 11 OUT 38 11 OUT 38 11 OUT 38 11 OUT 38 11 OUT 38 11 OUT 38 11 OUT 38 11 OUT 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 BI 38 11 OUT 38 11 OUT 38 11 OUT 38 11 34 DDR1_CA DDR1_CA DDR1_CA DDR1_CA DDR1_CA DDR1_CA DDR1_CA DDR1_CA DDR1_CA DDR1_CA DDR0_DM DDR0_DM DDR0_DM DDR0_DM E12 E9 C14 D6 DDR0_DM0 DDR0_DM1 DDR0_DM2 DDR0_DM3 DDR1_DM0 DDR1_DM1 DDR1_DM2 DDR1_DM3 L5 N5 G4 R5 DDR1_DM DDR1_DM DDR1_DM DDR1_DM DDR0_DQS_P DDR0_DQS_N DDR0_DQS_P DDR0_DQS_N DDR0_DQS_P DDR0_DQS_N DDR0_DQS_P DDR0_DQS_N A13 A12 A7 A8 A16 A15 A4 A5 DDR0_PDQS0 DDR0_NDQS0 DDR0_PDQS1 DDR0_NDQS1 DDR0_PDQS2 DDR0_NDQS2 DDR0_PDQS3 DDR0_NDQS3 DDR1_PDQS0 DDR1_NDQS0 DDR1_PDQS1 DDR1_NDQS1 DDR1_PDQS2 DDR1_NDQS2 DDR1_PDQS3 DDR1_NDQS3 G1 H1 N1 M1 D1 E1 T1 R1 DDR1_DQS_P DDR1_DQS_N DDR1_DQS_P DDR1_DQS_N DDR1_DQS_P DDR1_DQS_N DDR1_DQS_P DDR1_DQS_N DDR0_CK DDR0_CKB DDR0_CKE0 DDR0_CKE1 DDR0_RREF DDR0_CSN0 DDR0_CSN1 DDR0_VREF_DQ DDR0_VDD_CKE 4.7K PPVREF_DDR1_DQ_H5 =PP1V2_S2R_H5 20% 6.3V X5R 0201 10% 6.3V X5R 01005 C1054 0.01UF 10% 6.3V X5R 01005 BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI OUT 38 12 OUT OUT 11 38 38 12 OUT OUT 11 38 38 12 OUT OUT 11 38 38 12 OUT OUT 11 38 38 12 OUT OUT 11 38 38 12 OUT OUT 11 38 38 12 OUT OUT 11 38 38 12 OUT OUT 11 38 38 12 OUT OUT 11 38 38 12 OUT OUT 11 38 38 12 OUT OUT 11 38 38 12 OUT OUT 11 38 38 12 OUT OUT 11 38 38 12 OUT BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI BI 11 38 38 12 BI OUT 11 38 38 12 OUT OUT 11 38 38 12 OUT OUT 11 38 38 12 OUT OUT 11 38 38 12 OUT 8 34 34 1 R1056 4.7K 1% 1/32W MF 01005 DDR3_CA DDR3_CA DDR3_CA DDR3_CA DDR3_CA DDR3_CA DDR3_CA DDR3_CA DDR3_CA DDR3_CA DDR2_DM DDR2_DM DDR2_DM DDR2_DM AD4 AG4 AB6 AK4 DDR2_DM0 DDR2_DM1 DDR2_DM2 DDR2_DM3 DDR3_DM0 DDR3_DM1 DDR3_DM2 DDR3_DM3 AK11 AG14 AJ8 AG15 DDR3_DM DDR3_DM DDR3_DM DDR3_DM DDR2_DQS_P DDR2_DQS_N DDR2_DQS_P DDR2_DQS_N DDR2_DQS_P DDR2_DQS_N DDR2_DQS_P DDR2_DQS_N AA1 AB1 AG1 AF1 V1 W1 AK1 AJ1 DDR2_PDQS0 DDR2_NDQS0 DDR2_PDQS1 DDR2_NDQS1 DDR2_PDQS2 DDR2_NDQS2 DDR2_PDQS3 DDR2_NDQS3 DDR3_PDQS0 DDR3_NDQS0 DDR3_PDQS1 DDR3_NDQS1 DDR3_PDQS2 DDR3_NDQS2 DDR3_PDQS3 DDR3_NDQS3 AN7 AN8 AN13 AN12 AN4 AN5 AN16 AN15 DDR3_DQS_P DDR3_DQS_N DDR3_DQS_P DDR3_DQS_N DDR3_DQS_P DDR3_DQS_N DDR3_DQS_P DDR3_DQS_N AH14 DDR2_CK_P AH13 DDR2_CK_N AN10 DDR2_CKE NC_DDR2_CKE NO_TEST=TRUEAN9 AH9 H5G_DDR2_ZQ AG9 DDR2_CSN NO_TEST=TRUE AG8 NC_DDR2_CSN PPVREF_DDR2_DQ_H5 =PP1V2_S2R_H5 1 C1056 0.01UF 10% 6.3V X5R 01005 R1084 4.7K 1% 1/32W MF 01005 C1022 20% 6.3V X5R 0201 C1084 0.01UF 10% 6.3V X5R 01005 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI D C 12 38 B 12 38 12 38 12 38 12 38 R10234 C1023 240 1% 1/20W MF 201 20% 6.3V X5R 0201 C1095 10% 6.3V X5R 01005 SYNC_MASTER=N/A PAGE TITLE PPVREF_DDR3_DQ_H5 VOLTAGE=0.6V MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM 12 38 BI 0.01UF 1% 1/32W MF 01005 10% 6.3V X5R 01005 12 38 BI =PP1V2_VDDIOD_H5 4.7K 0.01UF BI 0.22UF R1095 C1085 AH4 DDR3_CK_P OUT AJ4 DDR3_CK_N OUT AD1 DDR3_CKE OUT AE1 NO_TEST=TRUE NC_DDR3_CKE AB5 H5G_DDR3_ZQ AC6 DDR3_CSN OUT AC5 NO_TEST=TRUE NC_DDR3_CSN AJ11 PPVREF_DDR3_DQ_H5 AE8 =PP1V2_S2R_H5 34 0.22UF PPVREF_DDR2_DQ_H5 DDR3_CK DDR3_CKB DDR3_CKE0 DDR3_CKE1 DDR3_RREF DDR3_CSN0 DDR3_CSN1 DDR3_VREF_DQ DDR3_VDD_CKE 1 VOLTAGE=0.6V MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM DDR2_CK DDR2_CKB DDR2_CKE0 DDR2_CKE1 DDR2_RREF DDR2_CSN0 DDR2_CSN1 AB4 DDR2_VREF_DQ Y8 DDR2_VDD_CKE 34 4.7K 10% 6.3V X5R 01005 OMIT_TABLE W5 W6 Y5 Y6 AA6 AD6 AE5 AE6 AF6 AF5 =PP1V2_VDDIOD_H5 R1083 0.01UF BGA SYM OF 12 DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_DQ DDR3_CA0 DDR3_CA1 DDR3_CA2 DDR3_CA3 DDR3_CA4 DDR3_CA5 DDR3_CA6 DDR3_CA7 DDR3_CA8 DDR3_CA9 1% 1/20W MF 201 1% 1/32W MF 01005 BALI-H5G AL8 AL9 AK9 AJ9 AM10 AJ10 AK10 AL11 AM11 AL12 AK12 AJ12 AM13 AK13 AJ13 AJ14 AM5 AL6 AK6 AJ6 AM7 AK7 AJ7 AM8 AM14 AL14 AJ15 AK15 AL15 AJ16 AK16 AM16 DDR2_CA0 DDR2_CA1 DDR2_CA2 DDR2_CA3 DDR2_CA4 DDR2_CA5 DDR2_CA6 DDR2_CA7 DDR2_CA8 DDR2_CA9 240 1% 1/20W MF 201 20% 6.3V X5R 0201 DDR3_DQ0 DDR3_DQ1 DDR3_DQ2 DDR3_DQ3 DDR3_DQ4 DDR3_DQ5 DDR3_DQ6 DDR3_DQ7 DDR3_DQ8 DDR3_DQ9 DDR3_DQ10 DDR3_DQ11 DDR3_DQ12 DDR3_DQ13 DDR3_DQ14 DDR3_DQ15 DDR3_DQ16 DDR3_DQ17 DDR3_DQ18 DDR3_DQ19 DDR3_DQ20 DDR3_DQ21 DDR3_DQ22 DDR3_DQ23 DDR3_DQ24 DDR3_DQ25 DDR3_DQ26 DDR3_DQ27 DDR3_DQ28 DDR3_DQ29 DDR3_DQ30 DDR3_DQ31 U0600 AH6 AG6 AH7 AG7 AH8 AH11 AG11 AG12 AH12 AG13 R1022 240 DDR2_DQ0 DDR2_DQ1 DDR2_DQ2 DDR2_DQ3 DDR2_DQ4 DDR2_DQ5 DDR2_DQ6 DDR2_DQ7 DDR2_DQ8 DDR2_DQ9 DDR2_DQ10 DDR2_DQ11 DDR2_DQ12 DDR2_DQ13 DDR2_DQ14 DDR2_DQ15 DDR2_DQ16 DDR2_DQ17 DDR2_DQ18 DDR2_DQ19 DDR2_DQ20 DDR2_DQ21 DDR2_DQ22 DDR2_DQ23 DDR2_DQ24 DDR2_DQ25 DDR2_DQ26 DDR2_DQ27 DDR2_DQ28 DDR2_DQ29 DDR2_DQ30 DDR2_DQ31 DDR2_CA DDR2_CA DDR2_CA DDR2_CA DDR2_CA DDR2_CA DDR2_CA DDR2_CA DDR2_CA DDR2_CA R1021 AB2 AB3 AC2 AC4 AD2 AD3 AE2 AE3 AF2 AF4 AG5 AH2 AJ2 AG3 AH3 AJ3 W2 W4 Y2 Y3 Y4 AA3 AA4 AA5 AK3 AL2 AM3 AM4 AL4 AL5 AK5 AJ5 DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ DDR2_DQ 11 38 C1021 PPVREF_DDR1_DQ_H5 BI C1058 VOLTAGE=0.6V MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM BI 38 12 34 1% 1/32W MF 01005 0.01UF 38 12 11 38 4.7K C1057 11 38 BI =PP1V2_VDDIOD_H5 R1055 PPVREF_DDR0_DQ_H5 NO_TEST=TRUE DDR1_CK_P DDR1_CK_N DDR1_CKE NC_DDR1_CKE H5G_DDR1_ZQ DDR1_CSN NC_DDR1_CSN BI 0.22UF R1053 NO_TEST=TRUE 34 1% 1/32W MF 01005 F11 F12 A10 A9 E11 F10 E13 L3 H8 C1020 =PP1V2_VDDIOD_H5 4.7K DDR1_CK DDR1_CKB DDR1_CKE0 DDR1_CKE1 DDR1_RREF DDR1_CSN0 DDR1_CSN1 DDR1_VREF_DQ DDR1_VDD_CKE 0.22UF 1% 1/20W MF 201 R1054 DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ DDR1_DQ E15 F15 F14 E14 F13 E8 F8 F7 E7 F6 240 OMIT_TABLE H2 H3 J3 J4 K2 L2 K4 K5 N2 P2 P3 R3 T2 R4 T3 T4 C2 D2 E2 E4 E3 F3 F4 G2 U3 V2 V3 U5 V4 V5 U6 V6 DDR1_CA0 DDR1_CA1 DDR1_CA2 DDR1_CA3 DDR1_CA4 DDR1_CA5 DDR1_CA6 DDR1_CA7 DDR1_CA8 DDR1_CA9 R1020 1% 1/32W MF 01005 BGA SYM OF 12 DDR1_DQ0 DDR1_DQ1 DDR1_DQ2 DDR1_DQ3 DDR1_DQ4 DDR1_DQ5 DDR1_DQ6 DDR1_DQ7 DDR1_DQ8 DDR1_DQ9 DDR1_DQ10 DDR1_DQ11 DDR1_DQ12 DDR1_DQ13 DDR1_DQ14 DDR1_DQ15 DDR1_DQ16 DDR1_DQ17 DDR1_DQ18 DDR1_DQ19 DDR1_DQ20 DDR1_DQ21 DDR1_DQ22 DDR1_DQ23 DDR1_DQ24 DDR1_DQ25 DDR1_DQ26 DDR1_DQ27 DDR1_DQ28 DDR1_DQ29 DDR1_DQ30 DDR1_DQ31 DDR0_CA0 DDR0_CA1 DDR0_CA2 DDR0_CA3 DDR0_CA4 DDR0_CA5 DDR0_CA6 DDR0_CA7 DDR0_CA8 DDR0_CA9 A U0600 BALI-H5G G5 G6 H5 H6 J5 M5 M6 N6 P5 P6 P4 N4 J1 NO_TEST=TRUE K1 M4 K6 NO_TEST=TRUE J6 PPVREF_DDR0_DQ_H5 D10 H15 =PP1V2_S2R_H5 OUT DDR0_DQ0 DDR0_DQ1 DDR0_DQ2 DDR0_DQ3 DDR0_DQ4 DDR0_DQ5 DDR0_DQ6 DDR0_DQ7 DDR0_DQ8 DDR0_DQ9 DDR0_DQ10 DDR0_DQ11 DDR0_DQ12 DDR0_DQ13 DDR0_DQ14 DDR0_DQ15 DDR0_DQ16 DDR0_DQ17 DDR0_DQ18 DDR0_DQ19 DDR0_DQ20 DDR0_DQ21 DDR0_DQ22 DDR0_DQ23 DDR0_DQ24 DDR0_DQ25 DDR0_DQ26 DDR0_DQ27 DDR0_DQ28 DDR0_DQ29 DDR0_DQ30 DDR0_DQ31 DDR0_CA DDR0_CA DDR0_CA DDR0_CA DDR0_CA DDR0_CA DDR0_CA DDR0_CA DDR0_CA DDR0_CA DDR0_CK_P DDR0_CK_N DDR0_CKE NC_DDR0_CKE H5G_DDR0_ZQ DDR0_CSN NC_DDR0_CSN 34 B14 B13 D13 C12 D12 B11 C11 B10 C9 D9 B8 C8 B7 B6 C6 D7 B17 C17 B16 E17 D16 E16 C15 D15 E6 B5 C5 E5 C4 D4 B3 C3 DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ R1096 4.7K 1% 1/32W MF 01005 C1096 0.01UF 10% 6.3V X5R 01005 SYNC_DATE=N/A AP: DDR DRAWING NUMBER VOLTAGE=0.6V MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9385 SIZE D REVISION A.0.0 BRANCH PAGE 10 OF 154 SHEET OF 39 A C5930 1.0UF 20% 6.3V X5R 0201-MUR C5935 0.1UF 10% 6.3V X5R 201 =PP3V3_ACC 36 25 TO BB USB 36 25 10 ACCESSORY USB 36 BI 36 BI 36 ACCESSORY UART 36 36 AP DEBUG UART 8.2PF +/-0.5PF 16V NP0-C0G-CERM 01005 36 26 MLB_A R5970 100K C R5971 100K CRITICAL U5900 IC,ASIC,TRISTAR,CBTL1608,A1,WLCSP36 D L5930 90-OHM-50MA 29 TCM0605-1 SYM_VER-1 C5934 1UF 10% 25V X5R 0402 CONN_E75_DPAIR1_P BI 24 36 CONN_E75_DPAIR1_N BI 24 36 WCSP USB_TS_BBMUX_P USB_TS_BBMUX_N A1 B1 USB_BRICKID C2 USB_AP_P USB_AP_N A3 B3 UART2_TS_ACC_TXD UART2_TS_ACC_RXD E2 E1 UART6_AP_TXD UART6_AP_RXD F2 F1 UART1_TX UART1_RX SWITCH_EN E4 HOST_RESET B6 D2 D1 UART2_TX UART2_RX SDA SCL INT BYPASS A5 B5 C5943 +/-0.5PF 16V NP0-C0G-CERM 01005 MIKEY_TS_P MIKEY_TS_N JTAG_AP_TCK_TS_R JTAG_AP_TMS_TS_R 1 CRITICAL 8.2PF DIG_DP P_IN F6 OMIT_TABLE DIG_DN ACC1 C5 ACC2 E5 USB1_DP USB1_DN DP1 A2 DN1 B2 BRICK_ID DP2 A4 USB0_DP DN2 B4 USB0_DN CON_DET_L E3 UART0_TX UART0_RX OVP_SW_EN* D6 JTAG_CLK JTAG_DIO E75_ACC_POUT_ID1 E75_ACC_POUT_ID2 5% 1/20W MF 201 23 23 36 TS_E75_DPAIR2_P TS_E75_DPAIR2_N 30 PMU_E75_ACC_DET_L D3 D4 C6 E6 L5931 RST_AP_L TS_HOST_RESET OUT IN 90-OHM-50MA 29 TCM0605-1 SYM_VER-1 26 30 39 CONN_E75_DPAIR2_P BI 24 36 CONN_E75_DPAIR2_N BI 24 36 25 19 30 36 19 30 36 30 C5944 8.2PF TSSLP-2-1 CRITICAL OUT DZ5901 ESD0P2RF-02LS OVP_SW_EN_L I2C0_SDA_1V8 I2C0_SCL_1V8 PMU_GPIO_TS_INT BYPASS_U5900 CRITICAL DZ5900 TSSLP-2-1 TS_E75_DPAIR1_P 36 TS_E75_DPAIR1_N 36 CRITICAL ESD0P2RF-02LS 36 +/-0.5PF 16V NP0-C0G-CERM 01005 F5 C1 A6 5% 1/20W MF 201 MLB_A BOM OPTION 0.1UF C3 C4 UART1_BB_RXD UART1_BB_TXD BB DEBUG UART (T’S OFF TO H5G UART1) CRITICAL 34 PPVBUS_PROT DVSS DVSS DVSS 36 26 36 REFERENCE DESIGNATOR(S) C5932 U5900 37 18 DESCRIPTION TABLE_5_ITEM THS7383IYKAR 37 18 QTY 343S0614 10% 6.3V X5R 201 +/-0.5PF 16V NP0-C0G-CERM 01005 ACC_PWR D5 10% 6.3V X5R 201 C5942 8.2PF C5941 VDD_1V8 F3 0.1UF VDD_3V0 F4 D C5931 TABLE_5_HEAD PART# 8.2PF =PP1V8_S2R_USBMUX 1 C5940 +/-0.5PF 16V NP0-C0G-CERM 01005 34 25 TRISTAR =PP3V0_S2R_TRISTAR 34 CRITICAL CRITICAL DZ5902 DZ5903 ESD0P2RF-02LS C5933 20% 6.3V X5R 0201-MUR C ESD0P2RF-02LS TSSLP-2-1 1.0UF TSSLP-2-1 1 R5930 JTAG_AP_TCK 36 0.00 PPVCC_MAIN 0% 1/32W MF 01005 TABLE_ALT_HEAD R5991 R5931 JTAG_AP_TMS 36 100K 0.00 5% 1/32W MF 01005 PLACE NEAR U5900 0% 1/32W MF 01005 R5929 18 OUT L81_MBUS_REF C5991 8.2PF 10K PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: 155S0773 155S0453 ? FL5990 RDAR://PROBLEM/10882925 TABLE_ALT_ITEM +/-0.5PF 16V NP0-C0G-CERM 01005 FL5990 120-OHM-210MA R5990 1 PMU_E75_ACC_DET_R_L 2 01005 5% 1/32W MF 01005 SM-201 MLB_D&MLB_E A 0.1UF 10% 6.3V X5R 201 CONN_E75_ACC_DET_L CRITICAL IN 24 DZ5990 ESD0P2RF-02LS +/-0.5PF 16V NP0-C0G-CERM 01005 D5990 C5960 C5990 8.2PF K CRITICAL =PP3V2_S2R_USBMUX B 0.00 0% 1/32W MF 01005 TRISTAR BASEBAND USB MUX (NEEDED FOR MDM9600 BB) 34 15 29 30 34 39 TSSLP-2-1 DSF01S30SC B MLB_D&MLB_E R5961 10K 5% 1/20W MF 201 34 25 =PP1V8_S2R_USBMUX VCC 36 36 BI BI 36 25 36 25 USB11_AP_BBMUX_P USB11_AP_BBMUX_N M+ M- USB_TS_BBMUX_P USB_TS_BBMUX_N D+ D- TS_BBMUX_EN_L MLB_D&MLB_E U5902 Y+ Y- USB_BBMUX_BB_P USB_BBMUX_BB_N PI3USB102ZLE 25 26 36 BI 25 26 36 0.1UF MLB_D&MLB_E R5934 R5962 SEL 10 OE* PMU_GPIO_BBUSBTODOCK_EN_R R5960 10K 5% 1/20W MF 201 0.00 PMU_GPIO_BBUSBTODOCK_EN 0% 1/32W MF 01005 MLB_D&MLB_E DEFAULT => SEL Y+ Y- M+ M- D+ D- IN 25 30 IN TS_HOST_RESET 0.00 IN AP_WDOG_RESET_IN TS_HOST_RESET_R 0% 1/32W MF 01005 SOT891 PMU_RESET_IN_R U5903 NOTE: ISOLATE SELECT SIGNAL FROM PMU ON MLB_B AND MLB_C SO THE MUX IS PERMANENTLY POINTED TO THE DOCK PMU_RESET_IN OUT 30 220K R5933 USB_TS_BBMUX_P 220K MF 5% 1/32W 01005 SYNC_MASTER=N/A PAGE TITLE R5965 USB_BBMUX_BB_P DRAWING NUMBER Apple Inc R MLB_B&MLB_C NOTICE OF PROPRIETARY PROPERTY: R5966 USB_TS_BBMUX_N SYNC_DATE=N/A TRISTAR 25 26 36 5% 1/20W MF 201 USB_BBMUX_BB_N THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 25 26 36 5% 1/20W MF 201 MF 5% 1/32W 01005 MLB_B&MLB_C 36 25 22 5% 1/32W MF 01005 NC R5935 R5932 BASEBAND USB MUX BYPASS 36 25 74LVC1G32 2 A C5936 10% 6.3V X5R 201 TQFN GND BI 051-9385 SIZE D REVISION A.0.0 BRANCH PAGE 59 OF 154 SHEET 25 OF 39 A D D CELLULAR/GPS HOTBAR PADS OMIT 998-3732 J6000 HOT-BAR-PADS DEBUG HB-SM BB_JTAG_TMS_RF 34 =BATT_POS_F_3G C 27 39 30 25 30 39 5 36 IN IN OUT IN OUT IN 36 OUT OUT IN IN OUT 30 OUT 30 IN 36 25 BI 36 25 BI 36 25 OUT 36 25 IN 36 B IN OUT OUT 36 IN BI WLAN_TX_BLANK RST_AP_L GPIO_BB_RADIO_ON_L PMU_GPIO_BB_PMU_RST_L GPIO_BB_GSM_TXBURST GPIO_BB_RST_L GPIO_BB_RESET_DET_L GPIO_BB_HSIC_HOST_RDY GPIO_BB_HSIC_RESUME BB_JTAG_TDO_RF BB_JTAG_TDI_RF BB_JTAG_TRST_RF_L GPIO_BB_GPS_SYNC PMU_GPIO_BB_HOST_WAKE BB_VBUS_DET USB_BBMUX_BB_P USB_BBMUX_BB_N UART1_BB_RXD UART1_BB_TXD UART1_BB_CTS_L UART1_BB_RTS_L OUT GPIO_AP_MODEM_WAKE GPIO_BB_HSIC_DEV_RDY 36 26 BI HSIC3_BB_STB 36 26 BI HSIC3_BB_DATA IN BB_JTAG_TCK_RF 36 5 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 NOSTUFF J6050 MM4829-2702 F-ST-SM 36 26 HSIC3_BB_STB C IN NOSTUFF J6051 MM4829-2702 F-ST-SM 36 26 HSIC3_BB_DATA B A SYNC_MASTER=N/A PAGE TITLE SYNC_DATE=N/A CONNECTOR: CELLULAR DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9385 SIZE D REVISION A.0.0 BRANCH PAGE 60 OF 154 SHEET 26 OF 39 A WLAN/BT CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN CONDUCTED TEST PORT TABLE_5_HEAD DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION ANTENNA CONNECTOR TABLE_5_ITEM 339S0171 D WIFI MODULE - MURATA CRITICAL U6101_RF CRITICAL CRITICAL MM4829-2702 C6193_RF TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES J6190_RF COMMENTS: F-ST-SM TABLE_ALT_ITEM 339S0175 339S0171 U6101_RF 311S0548 311S0398 U6102_RF CRITICAL WIFI MODULE - USI WIFI_50S 50_OHM RF_ANT_MATCH1 WIFI_50S 50_OHM +/-0.1PF 50V NP0-CERM 0402 1 CRITICAL CRITICAL C6191_RF WIFI_50S 50_OHM IN GND SM 5.6NH+/-0.3NH WIFI_50S 50_OHM SHORT-0402 GND NOSTUFF L6191_RF NOSTUFF 5.6NH-3%-0.35A 0201 5.6NH-3%-0.35A 0201 L6192_RF 39 C6101_RF 10UF 20% 6.3V CERM-X5R 0402-1 BATT_VCC_WLAN HI LO 0402 XW6102_RF COM RF_CAL_MATCH +/-0.25PF% 25V NP0-C0G 0201 D DPX205850DT-9038A1SJ 8.2PF RF_CAL OUT +/-0.05PF 50V NP0-CERM 0402 L6190_RF =BATT_VCC U6104_RF 0.2PF NOSTUFF 34 CRITICAL F-ST-SM C6192_RF 3.9PF RF_ANT TABLE_ALT_ITEM J6191_RF MM8030-2600RK0 QTY PART# 2 C6102_RF 27PF 5% 16V NP0-C0G 01005 R6108_RF 39 PP_WLAN_VDDIO_1V8 VOLTAGE=1.8V 1 C6103_RF 0.01UF NOSTUFF R6105_RF R6107_RF 32K INTERFACE TO AP 5% 1/32W MF 01005 XW6101_RF CLK32K_AP 14 VDDIO_1P8V SHORT-01005 WLAN_CLK32K 32 GPIO_6 CRITICAL 14 L6111_RF IN WLAN_REG_ON IN BT_REG_ON 31 JTAG_SEL 2.5UH-30%-0.7A-0.24OHM 29 WLAN_BUCK_OUT 27 14 27PF 14 27 VOLTAGE=1.8V 10K CLK32K_AP GPIO_6 VIN_1P2LDO BT_REG_ON 14 JTAG_SEL WLAN_SR_VLX1 28 SR_VLX 50_HSIC_WLAN_DATA 50_HSIC_WLAN_STROBE 24 25 WLAN_HSIC_DATA WLAN_HSIC_STROBE 2G_ANT 5G_ANT 8.2PF 42 52 38 38 HOST_WAKE_BT 34 50_WLAN_G 50_WLAN_A HOST_WAKE_BT BT_WAKE 39 OUT 14 IN 14 BT_WAKE LBEE5ZHTWC501 27 14 LGA BT_UART_RXD BT_UART_TXD OMIT_TABLE BT_UART_RTS* BT_UART_CTS* BT_PCM_CLK BT_PCM_SYNC BT_PCM_OUT C6109 BT_PCM_IN 4.7UF R6109_RF 20% 6.3V X5R-CERM1 402 38 37 35 36 BT_UART_RXD BT_UART_TXD BT_UART_RTS_L BT_UART_CTS_L NC 40 GPIO_2 10 GPIO_3 12 RF_SW_CTRL_3 GPIO_4 NO LONGER NEEDED BASED ON AND GATE REMOVAL B GPIO_5 11 GPIO_12 13 IN OUT 14 SDIO_DATA X X 14 A 27 14 IN 1.00M2 1% 1/32W MF 01005 WLAN_REG_ON_RC C6110_RF 0.22UF 20% 6.3V X5R 0201 14 14 OUT 14 IN 14 OUT 14 27 IN 14 27 PP PP6101_RF SM P4MM IN 14 27 OUT 14 27 OUT 27 R6111_RF 10K B PULL DOWN RESISTORS 53 54 55 56 57 58 59 60 5% 1/32W MF 01005 27 14 HOST_WAKE_WLAN PP PP6103_RF 27 14 AP_HSIC3_RDY PP PP6104_RF 27 14 DEV_HSIC3_RDY PP PP6105_RF 13FEB2012 AMANDA CHANGED OMIT TO OMIT_TABLE AND UPDATED BOM OPTION TABLES TO ALTERNATE TABLES REMOVED BOM TABLE FOR C6111_RF (NOW ALWAYS NOSTUFF) PP PP6102_RF P4MM P4MM P4MM P4MM SM SM SM SM 27 14 WLAN_UART_RXD PP PP6106_RF SM 27 14 WLAN_UART_TXD PP PP6107_RF SM P4MM P4MM U6102_RF R6112_RF WLAN_REG_ON 50_WLAN_A_DIPLX NC VCC 74AUP1G08GF SOT891 Y R6114_RF DEV_HSIC3_RDY 14 27 27 AGG_CHANNEL 0% 1/32W MF 01005 B NC 0.00 AGG_CHANNEL PP PP6109_RF SM 27 14 50_HSIC_WLAN_DATA PP PP6110_RF SM 27 14 50_HSIC_WLAN_STROBE PP PP6111_RF SM HSIC_DEVICE_RDY PP PP6112_RF SM 27 WLAN_TX_BLANK OUT 26 27 GND P4MM SYNC_MASTER=N/A P4MM PAGE TITLE SYNC_DATE=N/A WIFI/BT P4MM DRAWING NUMBER P4MM Apple Inc A 38 14 WLAN_REG_ON 27 14 10K HSIC_DEVICE_RDY C6111_RF +/-0.1PF 25V COG-CERM 201 +/-0.1PF 25V COG-CERM 0201 07FEB2012 MUSHTAQ COPIED FROM N41, ADDED J2 ANT MATCH/CONN C6107 FROM 20PF TO 8.2PF, C6108 FROM 10PF TO 4.7PF U6104 FROM SOSHIN TO MURATA LFD212G45DS5D355 R6113_RF 27 50_WLAN_G_1 CHANGE LIST 5% 1/32W MF 01005 38 27 PP_WL_BT_VDDIO_AP IN BI HOST_WAKE_WLAN AP_HSIC3_RDY WLAN_HSIC3_RESUME AGG_CHANNEL WLAN_UART_RXD WLAN_UART_TXD HSIC_DEVICE_RDY SDIO_DATA MODE DEFAULT ARM STATE X SDIO IN RESET GSPI IN RESET HSIC OUT OF RESET BOOTLESS HSIC IN RESET 27 14 BI NOSTUFF 0.2PF 14 14 +/-0.25PF% 25V NP0-C0G 0201 4.7PF OUT IN BT_PCM_CLK BT_PCM_SYNC BT_PCM_OUT BT_PCM_IN THRML_PAD 17 18 19 20 21 22 16 23 26 33 41 43 44 45 48 49 50 51 GND GPIO6 1 GPIO_0 GPIO_1 10K 5% 1/32W MF 01005 CRITICAL C6108_RF 0603 27 14 C CRITICAL C6107_RF U6101_RF WL_REG_ON 30 BATT_VCC 27 C 5% 1/32W MF 01005 VBATT_RF_VCC 46 VBATT_RF_VCC 47 10K PP_WL_BT_VDDIO_AP 0% 1/32W MF 01005 C6104_RF 5% 16V NP0-C0G 01005 10% 6.3V X5R 01005 15 0.00 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9385 SIZE D REVISION A.0.0 BRANCH PAGE 61 OF 154 SHEET 27 OF 39 A D D TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION 155S0644 155S0274 ? REF DES COMMENTS: TABLE_ALT_ITEM RDAR://PROBLEM/11282371 FL7500,L3620,L5550,L5730 C C CRITICAL 34 =BATT_POS_CONN J7500 BATT-J2 TP7500 F-RT-SMTH A TP-P55 NOSTUFF FL7500 240-OHM-0.2A-0.8-OHM 30 30 BI UART5_BATTERY_TRXD BI BATTERY_NTC BATT_SWI_CONN NET_SPACING_TYPE=ANLG C7522 33PF 5% 25V NPO-C0G 0201 NOTE: REMOVED R7541 HAS TP7502 29 0201 C7523 33PF 5% 25V NPO-C0G 0201 C7524 1000PF 10% 16V X7R-CERM 0201 C7525 82PF C7526 33PF 5% 5% 25V NP0-C0G-CERM 50V C0G-CERM 0201 0402 C7527 4.7PF +/-0.1PF 50V C0G-CERM 0402 HDQ THERM PACK_NEG PACK_POS SENSE BATT_SNS APN:516S0926 NET_SPACING_TYPE=ANLG MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM B B TP7501 A TP-P55 NOSTUFF TP7502 A TP-P55 NOSTUFF TP7503 A TP-P55 NOSTUFF A SYNC_MASTER=MADHAVI SYNC_DATE=12/06/2011 PAGE TITLE POWER: BATTERY CONNECTOR DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9385 SIZE D REVISION A.0.0 BRANCH PAGE 75 OF 154 SHEET 28 OF 39 A VCC_MAIN BYPASS CRITICAL TOTAL CAPS = ~400UF CRITICAL CRITICAL C8165 20% 6.3V TANT-1 B15G 20% 6.3V TANT-1 B15G 150UF PLACE ONE 10UF CAP AT EACH VDD INPUT PPVCC_MAIN C8166 10UF 150UF ESR MAX=70MOHM C8154 20% 6.3V X5R 603 CRITICAL CRITICAL C8155 10UF CRITICAL C8156 10UF 20% 6.3V X5R 603 C8157 10UF 20% 6.3V CERM-X5R 0402 CRITICAL C8162 10UF 20% 6.3V CERM-X5R 0402 CRITICAL C8187 10UF 20% 6.3V CERM-X5R 0402 20% 6.3V CERM-X5R 0402 CRITICAL CRITICAL C8188 10UF 20% 6.3V CERM-X5R 0402 C8193 CRITICAL 10UF C8194 10UF 20% 6.3V CERM-X5R 0402 20% 6.3V X5R 603 CRITICAL CRITICAL C8130 10UF C8131 1UF 20% 6.3V CERM-X5R 0402 PLACEMENT_NOTE=PLACE NEAR L8225.1 C8163 L8100 8.2PF 39 BUCK0A_LX0 QTY REFERENCE DESIGNATOR(S) CRITICAL IND,1.0UH,20%,59MO,2.74A L8100,L8101,L8102,L8103,L8109,L8110 CRITICAL PPVCC_MAIN_CPU0 29 CRITICAL TABLE_5_ITEM 152S1638 D IND,1.0UH,20%,64MO,2.3A L8104 CRITICAL PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION 152S1292 ? 138S0676 138S0654 ? REF DES C8159 10UF 20% 6.3V CERM-X5R 0402 TABLE_ALT_HEAD 152S1452 COMMENTS: CRITICAL PPVCC_MAIN_CPU1 29 34 C8190 CRITICAL 10UF C8158 10UF 20% 6.3V CERM-X5R 0402 20% 6.3V CERM-X5R 0402 CRITICAL PPVCC_MAIN_SOC 34 CRITICAL C8189 10UF CRITICAL C8160 10UF 20% 6.3V CERM-X5R 0402 C8161 10UF 20% 6.3V CERM-X5R 0402 20% 6.3V CERM-X5R 0402 CRITICAL 39 C8191 10UF C8192 10UF 20% 6.3V CERM-X5R 0402 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM NET_SPACING_TYPE=PWR DIDT=TRUE 39 L8102 CRITICAL L8112 FDMC6676BZ P-TYPE RDS(ON) 27 MOHM @-4.5V IMAX 6.9 A VGS MAX +/- 25V 39 34 32 S PMEG4030ER Q8104 FDMC6683 MLP3.3X3.3 R8172 D 28 K DZ8120 BZT52C10LP S G C8124 NOTE: 10V ZENER 39 34 29 39 34 29 39 34 29 39 34 29 39 29 18 PMU_VCENTER MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.25MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM VOLTAGE=6V 220K 1% 1/20W MF 201 LAYOUT NOTE: PLACE RIGHT AT THE PIN 29 25 R8196 OVP_SW_EN_L 4.7K OVP_SW_EN_L_R NOSTUFF 1% 1/20W MF 201 C8196 0.022UF LAYOUT NOTE: R8196, C8196 CAN BE ANYWHERE BET.TRISTAR AND PMU 10% 25V X7R 0402 34 29 34 29 C8133 C8132 4.7UF CRITICAL C8149 4.7UF 20% 6.3V X5R-CERM1 402 PP3V0_SENSOR 29 PP3V0_IO 29 PP3V0_S2R_TRISTAR 29 PP2V8_CAM 29 PP1V1_SRAM 29 PP1V8_ALWAYS CRITICAL C8148 2.2UF 20% 6.3V X5R-CERM1 402 10% 6.3V X5R 402 10% 35V X5R-CERM 0603 LAYOUT NOTE: PLACE RIGHT AT THE PIN 34 29 CRITICAL C8126 4.7UF 10% 35V X5R-CERM 0603 39 34 30 29 25 15 CRITICAL CRITICAL 4.7UF C8146 CRITICAL C8145 1UF 20% 6.3V X5R-CERM1 402 2.2UF 10% 6.3V X5R 402 10% 6.3V X5R 402 CRITICAL C8144 10UF 20% 6.3V CERM-X5R 0402 PPVCC_MAIN_CPU0 A10 VDD_BUCK0A B10 A6 VDD_BUCK0B B6 D1 VDD_BUCK0C D2 A14 VDD_BUCK2_01 B14 A18 B18 VDD_BUCK2_23 H1 VDD_BUCK3 H2 A2 VDD_BUCK4 B2 A22 VDD_BUCK5 B22 L20 VCC_MAIN_S N15 N16 VCC_MAIN N17 N18 PPVCC_MAIN_CPU1 PPVCC_MAIN PPVCC_MAIN_SOC CRITICAL C8147 2.2UF 39 34 30 29 25 15 10% 6.3V X5R 402 PPVCC_MAIN 39 34 29 39 34 34 39 34 39 34 39 34 C8169 0.22UF 20% 6.3V X5R 0201 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL 1 1 C8168 4.7UF 20% 6.3V X5R-CERM1 402 C8167 4.7UF 20% 6.3V X5R-CERM1 402 C8153 2.2UF 10% 6.3V X5R 402 C8152 C8151 4.7UF 10% 6.3V X5R 402 39 34 29 N9 N4 N7 N3 N11 N6 N2 N5 N14 PP1V8_S2R C8135 39 34 30 29 25 15 PPVCC_MAIN 1UF 10% 6.3V CERM 402 NOTE: FOR NO BATTERY SITUATION A 39 34 32 29 39 34 29 PPBATT_VCC NOSTUFF CRITICAL 1 10UF 10UF 20% 6.3V CERM-X5R 0402-1 20% 6.3V CERM-X5R 0402-1 39 R8100 0.5 1% 1/16W MF 402 C8173 PP1V2_S2R NOSTUFF CRITICAL C8174 CRITICAL C8170 10UF 20% 6.3V CERM-X5R 0402-1 BATT_POS_RC CRITICAL C8171 10UF 20% 6.3V CERM-X5R 0402-1 C8134 1UF 10% 6.3V CERM 402 C8136 CAP PER PIN N5 N14 1UF 10% 6.3V CERM 402 NET_SPACING_TYPE=CRYSTAL 39 BUCK0B_LX1 39 20% 6.3V CERM-X5R 0402 N1 XTAL1 PMU_XTAL PMU_EXTAL P1 XTAL2 NET_SPACING_TYPE=CRYSTAL CRITICAL 39 18PF 5% 25V NP0-C0G 201 39 BUCK0C_LX0 2012-1 C8143 18PF 5% 25V NP0-C0G 201 PART NUMBER 1 C8123 22UF NOSTUFF CRITICAL C8183 10UF C8185 10UF 20% 6.3V CERM-X5R 0402 20% 6.3V CERM-X5R 0402 PP1V1_CPUB PSB25201E-SM CRITICAL NOSTUFF XW8102 BUCK0C_FB 1 C8104 22UF C8105 22UF 20% 20% 6.3V 6.3V X5R-CERM-1 X5R-CERM-1 603 603 SM CRITICAL 39 BUCK2_LX0 39 BUCK2_LX1 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM NET_SPACING_TYPE=PWR DIDT=TRUE ADDITIONAL DISTRIBUTED 98UF (NO DERATING) 39 PILE32251E-SM CRITICAL 39 L8106 BUCK3_FB 39 BUCK4_LX0 39 BUCK4_FB 39 BUCK5_LX0 CRITICAL 2 NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM LDO5 LDO10 C8118 22UF CRITICAL C8119 20% 6.3V X5R-CERM-1 603 22UF 20% 6.3V X5R-CERM-1 603 NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM CRITICAL L8109 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM NET_SPACING_TYPE=PWR DIDT=TRUE OMIT_TABLE ADDITIONAL DISTRIBUTED 27UF (NO DERATING) 1.0UH-20%-2.74A-59MOHM PP1V8_S2R PSB32251E-SM NOSTUFF XW8104 CRITICAL C8110 22UF 20% 20% 6.3V 6.3V X5R-CERM-1 X5R-CERM-1 603 603 CRITICAL 39 C8109 L8110 OMIT_TABLE ADDITIONAL DISTRIBUTED 64UF (NO DERATING) 1.0UH-20%-2.74A-59MOHM 39 29 34 39 PP1V2_S2R PSB32251E-SM NOSTUFF XW8105 29 34 29 34 39 29 34 39 22UF C8112 22UF 20% 20% 6.3V 6.3V X5R-CERM-1 X5R-CERM-1 603 603 CRITICAL 29 34 39 C8111 L8111 ADDITIONAL DISTRIBUTED 32UF (NO DERATING) 2.2UH-20%-3.3A-0.064OHM 29 34 39 29 34 39 PP3V3_OUT PIME051E-SM CRITICAL NOSTUFF XW8106 (RON=0.05 OHM MAX) B 29 34 39 CRITICAL CRITICAL SM 29 34 39 29 34 39 CRITICAL 22UF SM 18 29 39 PP2V8_CAM PP1V0 PP1V1_SRAM PP1V8_ALWAYS SM 29 39 PP3V3_ACC PP3V0_S2R_TRISTAR PP3V0_S2R_HALL PP3V0_IO 20% 6.3V X5R-CERM-1 603 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM NET_SPACING_TYPE=PWR DIDT=TRUE NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM (50MA; 2.5-3.3V) (100MA; 1.8-3.3V) (300MA; 1.7-3.0V) (150MA; 2.5-3.6V) (50MA; 1.2-3.1V) (15MA; 2.0-3.55V) (300MA; 1.2-3.0V) (200MA; 2.5-3.55V) (250MA; 1.7-3.0V) (150MA; 0.6-1.3V) (650MA; 1.1V) (5MA; 1.8V) 22UF CRITICAL C8117 20% 6.3V X5R-CERM-1 603 NOSTUFF XW8103 BUCK5_FB PP3V0_GRAPE 29 34 39 PP1V7_VA_VCP 19 29 34 39 PP3V2_S2R_USBMUX 29 34 PP3V0_SENSOR 29 34 C C8195 20% 6.3V X5R-CERM-1 603 22UF (150MA; 1.2-3.1V) C8108 22UF CRITICAL PILE32251E-SM MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM NET_SPACING_TYPE=PWR DIDT=TRUE (PP3V3_OUT) (100MA; 1.65-1.805V; BUCK3) 22UF L8107 NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM BUCK3_LX0 C8107 34 39 CRITICAL 1.0UH-20%-3.9A-0.035OHM BUCK2_FB CRITICAL 20% 6.3V X5R-CERM-1 603 PILE32251E-SM BUCK2_LX2 39 39 CRITICAL 1.0UH-20%-3.9A-0.035OHM MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM NET_SPACING_TYPE=PWR DIDT=TRUE 39 PP1V2_SOC MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM NET_SPACING_TYPE=PWR DIDT=TRUE 34 39 DISTRIBUTED CRITICAL ADDITIONAL 12UF (NO DERATING) L8105 A21 BUCK5_LX0 B21 A23 BUCK5_BYP B23 BUCK5_FB E18 C8113 22UF 34 39 CRITICAL C8114 22UF 20% 20% 6.3V 6.3V X5R-CERM-1 X5R-CERM-1 603 603 (RON=0.05 OHM MAX) PP1V2_S2R 29 34 39 (RON=0.2 OHM MAX) PMU_VPUMP MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM VOLTAGE=4.6V PP1V2 34 39 PP1V8_S2R 29 34 39 PP1V8 32 34 39 TP_PP1V8_GRAPE C8137 0.01UF SYNC_MASTER=MADHAVI 10% 10V X5R-CERM 0201 BOM OPTION C8122 30 39 CRITICAL 22UF 1.0UH-20%-3.9A-0.035OHM A3 BUCK4_LX0 B3 BUCK4_FB D4 ALTERNATE FOR PART NUMBER CRITICAL C8182 20% 6.3V CERM-X5R 0402 OMIT_TABLE NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM REF DES C8138 1UF TABLE_ALT_HEAD CRITICAL C8103 22UF 10UF SM MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM NET_SPACING_TYPE=PWR DIDT=TRUE Y8138 1 CRITICAL L8104 G1 BUCK3_LX0 G2 BUCK3_FB H5 VPUMP K3 C8102 CRITICAL 1.0UH-20%-2.3A-64MOHM A13 BUCK2_LX0 B13 A15 BUCK2_LX1 B15 A17 BUCK2_LX2 B17 A19 NC BUCK2_LX3 B19 NC BUCK2_FB E15 VBUCK3 K2 CPU1V8_SW J1 CPU1V8_SW J2 WDIG_SW K1 D 20% 20% 20% 20% 6.3V 6.3V 6.3V 6.3V X5R-CERM-1 X5R-CERM-1 X5R-CERM-1 X5R-CERM-1 603 603 603 603 CRITICAL E1 E2 BUCK0C_FB F5 VBUCK4 M2 CPU1V2_SW L1 CPU1V2_SW L2 NOSTUFF CRITICAL 22UF NOSTUFF XW8101 BUCK0B_FB BUCK0C_LX0 P9 P4 N8 P2 P8 P10 P3 M6 P11 P6 M1 P5 P14 M16 C8184 10UF 20% 6.3V CERM-X5R 0402 PSB32251E-SM NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM A5 BUCK0B_LX0 B5 A7 BUCK0B_LX1 B7 BUCK0B_FB E6 VLDO1 VLDO2 VLDO3 VLDO4 VLDO5 VLDO6 VLDO7 VLDO8 VLDO9 VLDO10 VLDO11 VLDO12 VLDO16 ON_BUF MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM NET_SPACING_TYPE=PWR DIDT=TRUE A9 BUCK0A_LX0 B9 A11 BUCK0A_LX1 B11 BUCK0A_FB E11 32.768K-20PPM-12.5PF C8142 VDD_LDO1_6 VDD_LDO2 VDD_LDO3_5_8 VDD_LDO4_7 VDD_LDO9 VDD_LDO10 VDD_LDO11 VDD_LDO12 VDD_LDO16 36 36 CRITICAL MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM VOLTAGE=4.6V OMIT_TABLE SM 2.2UF 20% 6.3V X5R-CERM1 402 D2018 FCBGA SYM OF E20 E21 F19 F20 F21 G19 G20 G21 VBUS H19 H20 H21 J19 J20 J21 K20 K21 E19 K19 L23 VBUS_OVP_OFF CRITICAL C8125 4.7UF LDO5 LDO10 39 29 499 1% 1/20W MF 201 CRITICAL PP1V7_VA_VCP PP3V2_S2R_USBMUX PP3V0_S2R_HALL PP1V0 PP3V3_ACC 39 34 29 19 PPVBUS_USB LDO BYPASS PP3V0_GRAPE R8173 10% 25V X7R 0402 SHORT-0201 2.2UF USB REVERSE VOLTAGE PROTECTION 39 34 29 0.022UF 10% 25V X5R-CERM 805 MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=ANLG R81301 PPVBUS_USB_DCIN 34 C8172 NOSTUFF XW8114 CRITICAL VBUS_PROT_G D MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.25MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM VOLTAGE=6V MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM VOLTAGE=6.0V LLP MLP3.3X3.3 BATT_SNS_R NOSTUFF LAYOUT NOTE R3172- PLACE NEAR BMU C3172- PLACE NEAR PMU R3173- PLACE NEAR PMU A FDMC6676BZ 5% 1/20W MF 201 PPVBUS_PROT CRITICAL Q8123 1% 1/20W MF 201 BATT_SNS MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM NET_SPACING_TYPE=ANLG CRITICAL 470K A ACT_DIO 25 NOSTUFF F22 F23 G22 G23 CHG_LX H22 H23 J22 J23 M14 VBAT M17 IBAT_S P15 P16 P17 IBAT P18 M18 ACT_DIO E22 E23 VCENTER K22 K23 PPBATT_VCC 29 C B CRITICAL G K D8100 SOD-123W R81161 CRITICAL DCR=32MOHM MAX U8100 USB/BAT BUCK 5% 1/20W MF 201 CHANNEL 10UF CRITICAL CRITICAL L8103 LDO PIME101E-SM 4.7K MOSFET PP1V1_CPU1_FET PSB32251E-SM 1.0UH-20%-2.74A-59MOHM VCC-MAIN MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM NET_SPACING_TYPE=SWITCHNODE DIDT=TRUE C8121 OMIT_TABLE OMIT_TABLE SW_CHGA LDO INPUT SWITCH POWER OVP_SW_EN_L BUCK0B_LX0 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM NET_SPACING_TYPE=PWR DIDT=TRUE XTAL R8170 39 2.2UH-20%-4A-32MOHM PPVCC_MAIN RDSON=0.0136@VGS=-2.5V ID=12.0A 29 25 39 34 30 29 25 15 NOSTUFF CRITICAL C8181 1.0UH-20%-2.74A-59MOHM TABLE_ALT_ITEM C8100,C8101,C8102,C8103,C8104,C8105,C8107,C8108,C8109,C8110,C8111,C8112,C8113,C8114,C8117,C8118,C8119,C8120,C8121,C8222,C8123,C8195 30 39 CRITICAL CRITICAL RDAR://PROBLEM/8376462 ? NOSTUFF 20% 6.3V CERM-X5R 0402 SM TABLE_ALT_ITEM L8111 C8120 22UF CRITICAL C8180 10UF NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM 20% 6.3V CERM-X5R 0402 NOSTUFF XW8100 C8101 22UF CRITICAL PSB32251E-SM BUCK0A_FB C8100 22UF CRITICAL BUCK0A_LX1 29 34 CRITICAL NOSTUFF CRITICAL CRITICAL 22UF 20% 20% 20% 20% 6.3V 6.3V 6.3V X5R-CERM-1 X5R-CERM-1 X5R-CERM-1 6.3V X5R-CERM-1 603 603 603 603 PSB32251E-SM 1.0UH-20%-2.74A-59MOHM BOM OPTION TABLE_5_ITEM 152S1637 CRITICAL L8101 OMIT_TABLE ESR MAX=70MOHM DESCRIPTION MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM NET_SPACING_TYPE=PWR DIDT=TRUE TABLE_5_HEAD PART# OMIT_TABLE 1.0UH-20%-2.74A-59MOHM C8164 82PF +/-0.1PF% 5% 25V 25V NP0-C0G-CERM2 CER 0201 0201 20% 6.3V X5R 0201 PP1V1_CPU0_FET CRITICAL 15 25 29 30 34 39 COMMENTS: 20% 6.3V X5R 0201 C8140 1UF 10% 6.3V CERM 402 C8139 1UF 10% 6.3V CERM 402 C8141 PAGE TITLE 1UF 10% 6.3V CERM 402 SYNC_DATE=12/06/2011 PMU: ADRIANA PAGE DRAWING NUMBER Apple Inc R 051-9385 128S0339 128S0279 ? C8165,C8166 RDAR://PROBLEM/8967213 197S0392 ? Y8138 RDAR://PROBLEM/9936684 NOTICE OF PROPRIETARY PROPERTY: TABLE_ALT_ITEM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D A.0.0 TABLE_ALT_ITEM 197S0399 SIZE REVISION BRANCH PAGE 81 OF 154 SHEET 29 OF 39 A R8281 NOSTUFF 1% 1/20W MF 201 (TEMP1 (TEMP2 (TEMP3 (TEMP4 CRITICAL R8218 CRITICAL R8222 0201 10KOHM-1%-0.31MA 100PF XW8201 BOARD_TEMP8_N 37 H5G) PMU) I/O FLEX CONN) WIFI) C8223 37 32 XW8202 BOARD_TEMP3_N NOSTUFF PLACE XW AND CAP CLOSE TO PMU PLACE XW AND CAP CLOSE TO PMU C8220 XW8203 BOARD_TEMP4_N SM 3.92K 0.1% 100PF 402 1/16W MF 5% 6.3V CERM 01005 SM NOSTUFF PLACE XW AND CAP CLOSE TO PMU R8219 =PPVCC_MAIN_LED C8226 A DCR=106MOHM MAX MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM K SOD-323 37 15 20% 10V X5R 0603-1 OUT LED_IO_1_A 37 15 CRITICAL CRITICAL C8232 4.7UF CRITICAL C8233 4.7UF C8234 CRITICAL 4.7UF 10% 35V X5R-CERM 0603 10% 35V X5R-CERM 0603 OUT LED_IO_2_A C8235 37 15 OUT 10% 35V X5R-CERM 0603 B 1.00 1% 1/20W MF 201 LED_IO_3_A 4.7UF 10% 35V X5R-CERM 0603 39 26 25 OUT OUT 36 25 19 IN 36 25 19 BI 37 15 OUT OUT LED_IO_4_A 1.00 1% 1/20W MF 201 LED_IO_5_A OUT LED_IO_6_A DCR=106MOHM MAX A 4.7UF C8263 4.7UF SOD-323 10% 35V X5R-CERM 0603 10% 35V X5R-CERM 0603 CRITICAL GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 D5 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 G4 RESET_IN F4 RESET* H4 IRQ* AMUX_A0 AMUX_A1 AMUX_A2 AMUX_A3 AMUX_AY AMUX_B0 AMUX_B1 AMUX_B2 AMUX_B3 AMUX_BY A1 DWI_CK B1 DWI_DI C2 DWI_DO PMU_IREF PMU_VREF PMU_VDD_REF NET_SPACING_TYPE=ANLG 0.1UF NET_SPACING_TYPE=ANLG C8209 37 37 37 2 NET_SPACING_TYPE=SWITCHNODE DIDT=TRUE 37 37 R8239 LED_IO1_A_R LED_IO2_A_R LED_IO3_A_R LED_IO4_A_R LED_IO5_A_R LED_IO6_A_R 1.00 37 37 1% 1/20W MF 201 37 37 LED_IO1_B_R LED_IO2_B_R LED_IO3_B_R LED_IO4_B_R LED_IO5_B_R LED_IO6_B_R N21 P21 K16 K5 K6 K7 K8 M9 K9 N23 P23 K17 K10 M11 K11 K12 M12 K13 WLED_LXA VOUT_WLED_A WLED1_A WLED2_A WLED3_A WLED4_A WLED5_A WLED6_A WLED_LXB VOUT_WLED_B WLED1_B WLED2_B WLED3_B WLED4_B WLED5_B WLED6_B VDD_LCM_SW 39 VDD_BOOST_LCM 39 BOOST_LCM_LX 39 VDD_LCM LCM2_EN LCM_FB VLCM1 VLCM2 VLCM3 C8264 4.7UF 37 15 10% 35V X5R-CERM 0603 CRITICAL 1 1UF 10% 6.3V X5R 201 NET_SPACING_TYPE=ANLG 20% 6.3V X5R 0201 PMU_VDD_RTC PMU_ADC_REF NET_SPACING_TYPE=ANLG MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM PMU_GPIO_CLK_32K_GRAPE PMU_GPIO_CLK_32K_WLAN PMU_GPIO_BT_REG_ON PMU_GPIO_WLAN_REG_ON PMU_GPIO_BB_PMU_RST_L UART5_BATTERY_TRXD PMU_GPIO_BT_HOST_WAKE PMU_GPIO_WLAN_HOST_WAKE PMU_GPIO_BB_HOST_WAKE PMU_GPIO_CODEC_HS_INT_L PMU_GPIO_BBUSBTODOCK_EN PMU_GPIO_TS_INT PMU_GPIO_HALL2_IRQ PMU_GPIO_CODEC_RST_L PMU_GPIO_HALL_IRQ NC_PMU_GPIO16 NO_TEST=TRUE PMU_GPIO_BB_VBUS_DET 30 OUT 17 36 OUT 14 36 OUT 14 OUT 14 OUT 26 IN 28 IN 14 IN 14 IN 26 IN 18 OUT 25 IN 25 IN 23 OUT 18 IN 22 USED BY Z2 (1.8_S2R PUSH-PULL) (1.8_S2R;NO PD REQ’D PER BB TEAM) (1.8_S2R;NO PD REQ’D PER BB TEAM) BB_VBUS_DET STUFFING OPTION SELECTING GPIO OPTION BY DEFAULT REMOVE STUFFING RES AND WIRE DIRECTLY FOR PRODUCTION R8297 CPU1_SWITCH CPU1_SW_G CPU1_SW_S OUT LED_IO_1_B OUT LED_IO_2_B 37 15 C8265 OUT 1.00 1% 1/20W MF 201 NOSTUFF CRITICAL (NOTE: 2MHZ) 2.2UH-1.05A-0.195OHM 30 C8236 2.2UF 20% 10V X5R-CERM 402 C8237 10UF LED_IO_3_B A 10% 35V X5R-CERM 0603 37 15 37 15 A OUT OUT LED_IO_4_B 1.00 1% 1/20W MF 201 LED_IO_5_B OUT LED_IO_6_B 1.00 0.01UF 10% 50V X7R 402 C8266 R8269 1.00 C8239 A2 C8238 C8251 1% 1/20W MF 201 0.01UF 10% 50V X7R 402 1% 1/20W MF 201 Q8200 BGA ALTERNATE FOR PART NUMBER BOM OPTION 107S0150 107S0208 ? REF DES R8292 NC_PMU_DP_HPD NO_TEST=TRUE 1 NOSTUFF R8290 1M C8290 0.1UF 10% 16V X5R-CERM 0201 39 34 CPU0_SW_G_R 1M 5% 1/20W MF 201 C8291 S PP1V1_CPU0 Q8201 XW8290 CSD58874W1015 BGA SM PP1V1_CPU1_FET A1 D NOSTUFF 29 39 B1 C1 CPU1_SW_G_R A2 B2 G S C2 0.1UF Q8203 10% 16V X5R-CERM 0201 CSD58874W1015 BGA B1 C1 PP1V1_CPU1 30 34 39 30 0.01UF CPU1_SW_S MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM MAX_NECK_LENGTH=3 MM PLACEMENT_NOTE=PLACE NEAR U8100.K17 10% 50V PLACEMENT_NOTE=PLACE NEAR U8100.K17 X7R 402 A2 G S B2 XW8291 C2 SM NOSTUFF SYNC_MASTER=MADHAVI PAGE TITLE SYNC_DATE=12/06/2011 PMU: ADRIANA PAGE DRAWING NUMBER Apple Inc R TABLE_ALT_ITEM NOTICE OF PROPRIETARY PROPERTY: RDAR://PROBLEM/8380367 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED A1 D COMMENTS: B G C2 5% 1/20W MF 201 NOSTUFF A2 B2 CPU0_SW_S 29 39 PP1V1_CPU0_FET B1 C1 5% 1/20W MF 201 NOSTUFF NOSTUFF R8291 30 34 39 R8216,R8218,R8222,R8280,R8281,R8282 A1 D TABLE_ALT_HEAD PART NUMBER S C2 10% 10V X5R 402 402 C8267 B1 G B2 1UF 10% 10V X5R 402 30 PLACEMENT_NOTE=PLACE NEAR U8100.K16 X7R PPLED_OUT_B A1 CSD58874W1015 PLACEMENT_NOTE=PLACE NEAR U8100.K16 10% 50V BGA D NOSTUFF 0.01UF Q8202 CSD58874W1015 30 39 34 R8270 37 15 K C1 VLCM3 NOSTUFF C8201 0% 1/32W MF 01005 MAKE_BASE=TRUE VOLTAGE=6.0V MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM R8293 26 0.00 SOD882 1% 1/20W MF 201 R8265 4.7UF 1.00 OUT PMEG2005AEL MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM MAX_NECK_LENGTH=3 MM R8262 C BB_VBUS_DET D8230 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR DIDT=TRUE 1UF 20% 25V X5R-CERM 0603 NOSTUFF CRITICAL VLS201612E-SM NOSTUFF VLCM3 30 L8229 5% 1/20W MF 201 PPLED_OUT_A 0.00 NOSTUFF 1% 1/20W MF 201 R8296 NOSTUFF CPUB_EN L22 CPUB_SW_G J3 CPUB_SW_S K4 PMU_GPIO_BB_VBUS_DET 0% 1/32W MF 01005 NC CPU0_SWITCH CPU0_SW_G CPU0_SW_S 1000PF 10% 6.3V X5R-CERM 01005 NEED RADAR TO STOP GENERATING 32K CLOCK VOLTAGE=6.0V N19 PPVCC_MAIN MIN_LINE_WIDTH=0.4MM 15 25 29 34 39 MIN_NECK_WIDTH=0.2MM P19 PP6V0_LCM_HI NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM P20 LCM_LX N13 PP6V0_LCM_VBOOST F3 TP_LCM2_EN (INTERNAL PULLDOWN; TE ENABLE) M20 P13 NC_VLCM1 NO_TEST=TRUE P12 NC_VLCM2 NO_TEST=TRUE N12 CPUA_EN M23 CPUA_SW_G J5 CPUA_SW_S J4 C8214 (2.5V ALWAYS ON PU IN BMU) (INTERNAL PD) (INTERNAL PD) (INTERNAL PD; CAN’T BE USED FOR 32K CLK OUTPUT) (INTERNAL PU TO PP1V8_S2R) 30 I2C ADDRESS: 0111100X (0X78) 1.00 PLACEMENT NOTE: PLACE NEAR PIN K24 NET_SPACING_TYPE=ANLG C21 NC C22 NC E17 NC E14 NC C23 NC D21 NC D22 NC D19 NC E13 NC D23 DPHP E4 D C8210 0.22UF 10% 6.3V CERM 402 R8257 37 15 C8262 NET_SPACING_TYPE=SWITCHNODE DIDT=TRUE 1% 1/20W MF 201 K PPLED_OUT_B OUT 37 1.00 R8261 CRITICAL 36 (INTERNAL PULL-DOWN) (INTERNAL PULL-DOWN) M7 P7 K18 M15 N10 M10 30 20% 10V X5R 0603-1 CRITICAL IN TDEV1 TDEV2 TDEV3 TDEV4 TDEV5 TDEV6 TDEV7 TDEV8 TBAT TCAL IREF VREF VDD_REF VDD_REF_A VDD_RTC ADC_REF (PPLED_OUT_B) 10UF 39 34 30 PMEG4010BEA PIME051E-SM 1.00 1.00 D8258 4.7UH-3.2A C8256 36 DWI_AP_CLK DWI_AP_DO DWI_AP_DI 37 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM CRITICAL L8255 CRITICAL IN 1% 1/20W MF 201 WLED_LX_B CRITICAL =PPVCC_MAIN_LED 36 L19 K15 K14 M13 M5 M4 L3 M3 L21 M22 E7 SCL E9 SDA I2C0_SCL_1V8 I2C0_SDA_1V8 R8232 R8240 34 30 IN ACC_ID BRICK_ID ADC_IN7 ADC_IN31 NET_SPACING_TYPE=ANLG PMU_RESET_IN (INTERNAL PULL-DOWN) RST_AP_L (PULLUP INSIDE H5G) GPIO_PMU_IRQ_L 37 R8235 37 15 37 15 IN 25 1% 1/20W MF 201 R8231 PPLED_OUT_A 32 M8 M21 L4 L5 E10 KEEPACT GPIO_PMU_KEEPACT (INTERNAL PULL-DOWN) H3 SHDN PMU_SHDWN (PPLED_OUT_A) R8227 10UF 39 34 30 IN WLED_LX_A PMEG4010BEA PIME051E-SM CRITICAL FW_DPHP_DET BUTTON1 BUTTON2 BUTTON3 ACC_DET MAKE_BASE=TRUE D8228 4.7UH-3.2A C8212 PLACEMENT NOTE: PLACE NEAR PIN K4 FCBGA SYM OF CRITICAL L8225 34 30 IN CRITICAL DWI NAMING RELATIVE TO AP CRITICAL 28 RESISTOR FOR TEMP CALIBRATION 10KOHM-1%-0.31MA BOARD_TEMP1 BOARD_TEMP2 37 BOARD_TEMP3_P 37 BOARD_TEMP4_P 30 BOARD_TEMP5_P 30 BOARD_TEMP6_P 37 BOARD_TEMP7_P 37 BOARD_TEMP8_P BATTERY_NTC PMU_TCAL NET_SPACING_TYPE=ANLG 37 32 CRITICAL R8280 5% 6.3V CERM 01005 37 SM NOSTUFF 100PF NOSTUFF SM PLACE XW AND CAP CLOSE TO PMU NEAR NEAR NEAR NEAR 37 0201 5% 6.3V CERM 01005 XW8200 BOARD_TEMP7_N 37 R8216 100PF 37 C SIDE SIDE SIDE SIDE 37 10KOHM-1%-0.31MA C8217 5% 6.3V CERM 01005 BOTTOM BOTTOM BOTTOM BOTTOM 0201 CRITICAL 0201 - 10KOHM-1%-0.31MA C8221 5% 6.3V CERM 01005 PMU_ACC_ID PMU_USB_BRICKID_R ADC_IN7 6.34K2 PMU_USB_BRICKID IN 10 100PF IN (INTERNAL PULL-DOWN) M19 NC_FW_ZENER_PWR NO_TEST=TRUE C3 D3 E3 C1 R8299 PLACE XW AND CAP CLOSE TO PMU C8215 IN 25 1% 1/20W MF 201 U8100 GPIO_BTN_HOME_L GPIO_BTN_ONOFF_L GPIO_BTN_SRL_L PMU_E75_ACC_DET_L PLACE XW AND CAP CLOSE TO PMU SM IN 20 200K 0.1UF D2018 DIGITAL INPUT REFERENCES 37 20 OMIT_TABLE 10% 6.3V X5R 01005 R8203 C8204 10% 6.3V X5R 201 ANALOG INPUT SM NOSTUFF IN 0.01UF 10% 6.3V X5R 01005 LCM/GRAPE 37 23 C8207 TEMPERATURE GPIO XW8282 BOARD_TEMP6_N XW8281 BOARD_TEMP5_N 0.01UF 10% 6.3V X5R 01005 SENSOR LOCATIONS TBD LOCATION DESCRIPTIONS ARE FROM J2 LED BACKLIGHT 5% 6.3V CERM 01005 C8206 0.01UF 0201 100PF C8292 WDOG RESET I2C & DWI ANALOG MUX 10KOHM-1%-0.31MA D 37 0201 C8282 37 10KOHM-1%-0.31MA 5% 6.3V CERM 01005 CRITICAL R8282 100PF BOARD_TEMP5_P 30 BOARD_TEMP6_P 30 CRITICAL (TEMP5 - TOP SIDE NEAR NAND) (TEMP6 BOTTOM SIDE NEAR BRIDGE FLEX) C8281 051-9385 SIZE D REVISION A.0.0 BRANCH PAGE 82 OF 154 SHEET 30 OF 39 A D D OMIT_TABLE U8100 D2018 FCBGA SYM OF C4 D20 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 G3 G5 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 C B VSS/VSS_BUCK0A0B VSS/VSS_BUCK0A2 VSS/VSS_BUCK0B4 VSS/VSS_BUCK0C3 VSS/VSS_BUCK25 A16 B16 A20 B20 VSS/VSSA_BUCK0A VSS/VSSA_BUCK0B VSS/VSSA_BUCK0C VSS/VSSA_BUCK2 VSS/VSSA_BUCK3 VSS/VSSA_BUCK4 VSS/VSSA_BUCK5 E12 E8 G6 E16 H6 E5 F18 VSS/VSS_BUCK2_01 VSS A8 B8 A12 B12 A4 B4 F1 F2 ADD A VIA PER PIN FOR ALL VSS_* AND VSSA_* PINS C VSS_WLED N22 VSS_WLED P22 VSS_LCM N20 VSS J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 B A SYNC_MASTER=MADHAVI PAGE TITLE SYNC_DATE=12/06/2011 PMU: ADRIANA PAGE DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9385 SIZE D REVISION A.0.0 BRANCH PAGE 83 OF 154 SHEET 31 OF 39 A D D DEBUG RESET ACCESS 34 =PP1V8_S2R_MISC 39 34 29 PPBATT_VCC NOSTUFF R9000 300 OUT NOSTUFF 39 34 32 29 R9002 5% 1/20W MF 201 PP1V8 1.5K NOSTUFF 1% 1/20W MF 201 R9001 300 5% 1/20W MF 201 GPIO_FORCE_DFU PWR_ON_LED A 30 NOSTUFF OUT PMU_SHDWN LED9000 RED-50MCD-20MA C K 0603 C SOCHOT TO PMU TDEV1/TDEV2 39 34 32 29 PP1V8 B R9020 R9010 SOCHOT1_TDEV1 R9011 100K 100K 5% 1/20W MF 201 5% 1/20W MF 201 CRITICAL BOARD_TEMP1 1% 1/32W MF 01005 D SOCHOT1 470 S B 30 37 R9021 10K 1% 1/32W MF 01005 Q9020 G OUT DMN26D0UFB4 DFN SYM_VER_1 CRITICAL D IN SOCHOT1_L Q9010 G S DMN26D0UFB4 R9030 DFN SOCHOT1_TDEV2 SYM_VER_1 CRITICAL D Q9030 S 470 1% 1/32W MF 01005 G DMN26D0UFB4 DFN BOARD_TEMP2 OUT 30 37 R9031 10K 1% 1/32W MF 01005 SYM_VER_1 A SYNC_MASTER=MLB PAGE TITLE SYNC_DATE=11/09/2011 DEBUG/MISC DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9385 SIZE D REVISION A.0.0 BRANCH PAGE 90 OF 154 SHEET 32 OF 39 A D D PLATED THROUGH HOLES DRILL SIZE: 1.1MM X 0.4MM PLATING SIZE: 1.4MM X 0.7MM SL4210 TH-NSP FID4200 FID 0P5SM1P0SQ-NSP SL-1.1X0.4-1.4X0.7 FID4201 FID SL4201 TH-NSP 0P5SM1P0SQ-NSP 1 FID4202 SL-1.1X0.4-1.4X0.7 FID 0P5SM1P0SQ-NSP SL4212 TH-NSP FID4203 C FID C 0P5SM1P0SQ-NSP SL-1.1X0.4-1.4X0.7 FID4204 FID SL4213 TH-NSP 0P5SM1P0SQ-NSP 1 FID4205 SL-1.1X0.4-1.4X0.7 FID 0P5SM1P0SQ-NSP SL4214 TH-NSP SL4204 TH-NSP 1 SL-1.1X0.4-1.4X0.7 SL-1.1X0.4-1.4X0.7 SL4215 TH-NSP SL4205 TH-NSP 1 SL-1.1X0.4-1.4X0.7 SL-1.1X0.4-1.4X0.7 SL4216 TH-NSP SL4206 TH-NSP 1 SL-1.1X0.4-1.4X0.7 SL-1.1X0.4-1.4X0.7 B B A SYNC_MASTER=N/A SYNC_DATE=N/A PAGE TITLE TEST/HOLES/FIDUCUALS DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9385 SIZE D REVISION A.0.0 BRANCH PAGE 93 OF 154 SHEET 33 OF 39 A POWER CONNECTIONS BUCK5 BUCK0A PP1V1_CPU0 39 30 =PPVDD_CPU0_H5 PP3V3_OUT 39 29 MAKE_BASE=TRUE MAKE_BASE=TRUE VOLTAGE=3.3V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM VOLTAGE=1.1V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM D BUCK0B 39 30 PP1V1_CPU1 =PP3V3_NAND =PP3V3_USB_H5 =PP3V3_LCD 39 30 29 25 15 =PPVDD_CPU1_H5 39 29 PP3V0_IO =PP3V0_VDDIO30_H5 MAKE_BASE=TRUE 39 30 PPLED_OUT_A =PPLED_REG_A 15 =PPLED_REG_B 15 VOLTAGE=20.4V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM BUCK0C 39 30 PPLED_OUT_B =PPVDD_CPUB_H5 =PP2V8_CAM C 39 29 39 32 29 =PPVDD_SOC_H5 VOLTAGE=1.2V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM PP3V0_GRAPE LDO12 =PP3V0_GRAPE VOLTAGE=3.0V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM PP1V8_S2R =PP3V0_GRAPE_MARIO1 16 39 29 PP1V0 =PP1V0_MIPI_H5 MAKE_BASE=TRUE =PP3V0_GRAPE_Z1 =PP3V0_GRAPE_Z2 VOLTAGE=1.0V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM 17 17 PP1V7_VA_VCP 39 29 19 =PP1V7_VA_VCP VOLTAGE=1.7V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM 32 VDDIO_WLAN_BT_1V8 14 =PP1V8_S2R_USBMUX 25 =PP1V8_S2R_DDR 11 12 28 =BATT_POS_F_3G 26 CELLULAR RADIO =BATT_VCC 27 WLAN =PP1V0_DP_PAD_DVDD_H5 =PP1V0_EDP_PAD_DVDD_H5 =PP1V0_USB_H5 =PP1V0_HSIC_H5 39 23 PPVBUS_USB_EMI PPVBUS_USB_DCIN C 29 MAKE_BASE=TRUE VOLTAGE=6V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.15 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM 4 LDO16 18 19 MAKE_BASE=TRUE =PP1V8_S2R_MISC =BATT_POS_CONN =PP1V0_MIPI_PLL_H5 39 29 PP1V1_SRAM =PPVDD_SRAM_H5 MAKE_BASE=TRUE MAKE_BASE=TRUE VOLTAGE=1.8V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.15 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM 29 USB POWER INPUT 16 17 LDO2 BUCK3 PPBATT_VCC VOLTAGE=4.2V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MAKE_BASE=TRUE MAKE_BASE=TRUE 39 29 29 MAKE_BASE=TRUE LDO1 PP1V2_SOC D 29 BATTERY 21 VOLTAGE=2.8V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM VOLTAGE=20.4V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MAKE_BASE=TRUE PP2V8_CAM MAKE_BASE=TRUE MAKE_BASE=TRUE VOLTAGE=1.1V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM 39 29 PPVCC_MAIN_CPU0 PPVCC_MAIN_CPU1 PPVCC_MAIN_SOC 18 19 30 LDO11 MAKE_BASE=TRUE 39 29 BUCK2 =PPVCC_MAIN_AUDIO =PPVCC_MAIN_LED VOLTAGE=4.7V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM VOLTAGE=3.0V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MAKE_BASE=TRUE PP1V1_CPUB PPVCC_MAIN MAKE_BASE=TRUE 15 BACKLIGHT BOOST VOLTAGE=1.1V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM 39 29 CHARGER MAIN LDO9 13 VOLTAGE=1.1V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM LDO3 (NO LONGER NEEDED) 39 29 PP3V2_S2R_USBMUX =PP3V2_S2R_USBMUX 25 MAKE_BASE=TRUE VOLTAGE=3.0V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM BUCK4 39 29 PP1V2_S2R 39 29 LDO4 =PP1V2_S2R_H5 =PP1V2_S2R_DDR 11 12 MAKE_BASE=TRUE VOLTAGE=1.2V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM B 39 29 MAKE_BASE=TRUE VOLTAGE=1.8V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM PP3V0_SENSOR =PP3V0_SENSOR B 21 MAKE_BASE=TRUE LDO6 CPU1V8_SW PP1V8 =PP1V8_ALWAYS VOLTAGE=3.0V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM BUCK3_SW 32 29 39 PP1V8_ALWAYS MAKE_BASE=TRUE VOLTAGE=1.8V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM =PP1V8_SENSOR =PP1V8_AUDIO 21 18 =PP1V8_VDDIO18_H5 =PP1V8_H5 =PP1V8_MIPI_H5 =PP1V8_DP_H5 =PP1V8_EDP_H5 =PP1V8_NAND_H5 =PP1V8_NAND =PP1V8_PLL_H5 =PP1V8_MISC 39 29 PP3V3_ACC =PP3V3_ACC 25 MAKE_BASE=TRUE VOLTAGE=3.3V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM 10 7 13 LDO7 16 29 PP3V0_S2R_TRISTAR =PP3V0_S2R_TRISTAR 25 MAKE_BASE=TRUE A VOLTAGE=3.0V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM BUCK4_SW SYNC_MASTER=N/A PAGE TITLE CPU1V2_SW 39 29 PP1V2 MAKE_BASE=TRUE VOLTAGE=1.2V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.1 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM =PP1V2_VDDQ_DDR =PP1V2_VDDIOD_H5 =PP1V2_HSIC_H5 LDO8 11 12 DRAWING NUMBER Apple Inc R 39 29 PP3V0_S2R_HALL I927 =PP3V0_S2R_HALL NOTICE OF PROPRIETARY PROPERTY: 21 23 MAKE_BASE=TRUE VOLTAGE=3.0V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM SYNC_DATE=N/A POWER ALIASES THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9385 SIZE D REVISION A.0.0 BRANCH PAGE 121 OF 154 SHEET 34 OF 39 A MLB CONSTRAINTS TCF VERSION (USING SPACING RULE) TABLE_SPACING_RULE_HEAD TABLE_BOARD_INFO BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION SPACING_RULE_SET TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,BOTTOM NO_TYPE,BGA,BGA06-06,BGA_P4 MM 16.2 TCF_VERSION ALLOW ROUTE ON LAYER? LAYER MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP * 0.104 MM ? NOTES: NC_UART5_TXD 0.104 - 11/30/2011 ASSIGNING RULE TO NC NET SPACING CONSTRAINTS TABLE_PHYSICAL_RULE_HEAD MINIMUM NECK WIDTH WEIGHT TCF_VERSION I1 MINIMUM LINE WIDTH LINE-TO-LINE SPACING TABLE_SPACING_RULE_ITEM PHYSICAL CONSTRAINTS PHYSICAL_RULE_SET LAYER DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM D DEFAULT * Y =45_OHM_SE =45_OHM_SE 3.0 MM MM MM STANDARD * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT DEFAULT/BGA SPACING RULES TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM SINGLE-ENDED PHYSICAL RULES 45 OHMS DEFAULT * 0.100 MM ? STANDARD * =DEFAULT ? BGA_SPA * =DEFAULT ? BGA_P4_SPA * 0.200 MM ? TABLE_SPACING_RULE_ITEM LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH 45_OHM_SE TOP,BOTTOM Y 0.105 MM 0.055 MM 3.0 MM DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 45_OHM_SE ISL2,ISL9 Y 0.055 MM 0.055 MM 3.0 MM 45_OHM_SE ISL3,ISL8 Y 0.065 MM 0.055 MM 3.0 MM 45_OHM_SE ISL4,ISL7 Y 0.053 MM 0.055 MM 3.0 MM 45_OHM_SE ISL5 Y 0.072 MM 0.055 MM 3.0 MM TABLE_PHYSICAL_RULE_ITEM REGULAR SPACING RULES TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_PHYSICAL_RULE_ITEM Y ISL6 0.059 MM 0.055 MM 3.0 MM LINE-TO-LINE SPACING WEIGHT 1:1_SPACING LAYER * 0.050 MM ? 0P08_SPACING * 0.080 MM ? 1.5:1_SPACING * 0.075 MM ? 2:1_SPACING * 0.100 MM ? 2.5:1_SPACING * 0.125 MM ? 3:1_SPACING * 0.150 MM ? 4:1_SPACING * 0.200 MM ? 5:1_SPACING * 0.250 MM ? 0P5MM_SPACING * 0.5 MM ? 0P64MM_SPACING * 0.64 MM ? 0P2_SPACING * 0.20 MM ? TABLE_SPACING_RULE_ITEM ALLOW ROUTE ON LAYER? LAYER TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TOP,BOTTOM Y 0.090 MM 0.090 MM 0.170 MM =STANDARD 0.170 MM MM ~ MIL 0.114 MM ~ 4.5 MIL 0.125 MM ~ MIL 0.140 MM ~ 5.5 MIL D 0.15 MM ~ MIL 0.18 MM ~ MIL 0.2 ~ MIL MM 0.25 MM ~ 10 MIL 0.3 MM ~ 12 MIL 0.33 MM ~ 13 MIL 0.4 MM ~ 16 MIL 1.0 MM = 39.37 MIL TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 90_OHM_DIFF ISL2,ISL9 Y 0.062 MM 0.062 MM =STANDARD 0.190 MM 0.190 MM 90_OHM_DIFF ISL3,ISL8 Y 0.062 MM 0.052 MM =STANDARD 0.190 MM 0.190 MM 90_OHM_DIFF ISL4,ISL7 Y 0.051 MM 0.051 MM =STANDARD 0.190 MM 0.190 MM 90_OHM_DIFF ISL5,ISL6 Y 0.052 MM 0.052 MM =STANDARD 0.105 MM 0.105 MM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM C 0.102 TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 90_OHM_DIFF ~ 3.5 MIL TABLE_SPACING_RULE_ITEM 90 OHMS DIFFERENTIAL PAIR PHYSICAL RULES PHYSICAL_RULE_SET ~ MIL MM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 45_OHM_SE MM 0.089 TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET 0.075 TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM C TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM DDR 45 OHMS SINGLE-ENDED PHYSICAL RULES TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DDR_45_OHM_SE TOP,BOTTOM Y 0.105 MM 0.105 MM 3.0 MM DDR_45_OHM_SE ISL2 Y 0.055 MM 0.055 MM 3.0 MM DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM POWER/GND SPACING RULES TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_ITEM DDR_45_OHM_SE ISL3 Y 0.065 MM 0.065 MM 3.0 MM DDR_45_OHM_SE ISL4 Y 0.053 MM 0.053 MM 3.0 MM DDR_45_OHM_SE ISL5,ISL6 Y 0.072 MM 0.072 MM 3.0 MM DDR_45_OHM_SE * N 0.055 MM 0.055 MM 3.0 MM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM PWR_P1SPACING * 0.1 MM GND_P1SPACING * 0.1 MM SWITCHNODE * 0.2 MM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM DDR 90 OHMS DIFFERENTIAL PAIR PHYSICAL RULES TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP DDR_90_OHM_DIFF TOP,BOTTOM Y 0.090 MM 0.090 MM =STANDARD 0.170 MM 0.170 MM DDR_90_OHM_DIFF ISL2 Y 0.062 MM 0.062 MM =STANDARD 0.190 MM 0.190 MM DDR_90_OHM_DIFF ISL3 Y 0.062 MM 0.062 MM =STANDARD 0.190 MM 0.190 MM DDR_90_OHM_DIFF ISL4 Y 0.051 MM 0.051 MM =STANDARD 0.190 MM 0.190 MM DDR_90_OHM_DIFF ISL5,ISL6 Y 0.066 MM 0.066 MM =STANDARD 0.180 MM 0.180 MM POWER TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH PWR * Y 0.6MM 0.20 MM 3.0 MM GND_PH * Y 0.6MM 0.075 MM 3.0 MM PWR_PMU * Y 0.6MM 0.20 MM 3.0 MM DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM B TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET B TABLE_PHYSICAL_RULE_ITEM DDR_90_OHM_DIFF N * 0.056 MM 0.056 MM =STANDARD 0.180 MM 0.180 MM MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP WIFI PHYSICAL RULES PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MISC TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET * * BGA BGA_SPA CLK * BGA BGA_SPA GND * * GND_P1SPACING SWITCHNODE * * SWITCHNODE ANLG * * 3:1_SPACING * * BGA_P4 BGA_P4_SPA TABLE_PHYSICAL_RULE_ITEM WIFI_50S TOP,BOTTOM Y 0.245 MM 0.2 MM =STANDARD WIFI_50S * N =STANDARD =STANDARD =STANDARD WIFI_PWR100 * Y 0.10 MM 0.050 MM =STANDARD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM WIFI_PWR1000 Y * 1.00 MM 0.100 MM TABLE_SPACING_ASSIGNMENT_ITEM =STANDARD TABLE_SPACING_ASSIGNMENT_ITEM MISC PHYSICAL RULES TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.08 MM 0.08 MM SPEAKER * Y 0.5 MM 0.20 MM 10 MM 0.10 MM 0.10 MM AUDIO_DIFF * Y 0.1 MM 0.09 MM 10 MM 0.10 MM 0.10 MM LED * Y 0.1 MM 0.09 MM 10 MM 0.08 MM 0.08 MM TEMP_SENSE * Y 0.1 MM 0.09 MM 10 MM 0.08 MM 0.08 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM A SYNC_MASTER=MIKE SYNC_DATE=11/30/2011 PAGE TITLE CONSTRAINTS: MLB RULES BGA AREA PHYSICAL RULES TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET * BGA BGA_PHY DRAWING NUMBER Apple Inc TABLE_PHYSICAL_ASSIGNMENT_ITEM R NOTICE OF PROPRIETARY PROPERTY: TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP BGA_PHY * Y 0.060 MM 0.060 MM =STANDARD 0.076 MM 0.075 MM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED TABLE_PHYSICAL_RULE_ITEM 051-9385 SIZE D REVISION A.0.0 BRANCH PAGE 150 OF 154 SHEET 35 OF 39 A JTAG TABLE_PHYSICAL_ASSIGNMENT_HEAD AREA_TYPE USB Clock Signal Constraints NET_PHYSICAL_TYPE PHYSICAL_RULE_SET TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET USB_90D * 90_OHM_DIFF TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM CLK_50S * 45_OHM_SE TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET JTAG * * 2:1_SPACING TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET USB * * 4:1_SPACING TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM CLK * * 3:1_SPACING NET_TYPE D ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL SPACING PHYSICAL I63 I162 I88 I89 I96 I94 CLK_50S CLK_50S CLK CLK PMU_GPIO_CLK_32K_GRAPE PMU_GPIO_CLK_32K_WLAN CLK_50S CLK_50S CLK_50S CLK_50S CLK CLK CLK CLK ISP1_CAM_FF_CLK CONN_ISP1_CAM_FF_CLK ISP0_CAM_RF_CLK CONN_ISP0_CAM_RF_CLK I2S_50S I2S_50S CLK_50S CLK_50S CLK_50S CLK_50S CLK_50S CLK_50S I130 I131 I157 I158 I234 I235 I256 I257 I15 17 30 I14 14 30 I13 22 I20 ELECTRICAL_CONSTRAINT_SET 25 USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D I5 I6 4 10 39 I266 I267 20 22 I268 I269 20 22 I270 I2C 36 18 36 I271 I258 TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET I2C_50S * 45_OHM_SE I259 TABLE_PHYSICAL_ASSIGNMENT_ITEM I260 I261 22 TABLE_SPACING_ASSIGNMENT_HEAD 22 NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET I2C * * 1.5:1_SPACING 22 I263 I262 TABLE_SPACING_ASSIGNMENT_ITEM 22 SPACING PHYSICAL 25 22 I2S0_CODEC_ASP_MCK I2S0_CODEC_ASP_MCK_R ISP0_CAM_RF_CLK_R ISP1_CAM_FF_CLK_R ISP1_CAM_FF_C ISP0_CAM_RF_C ISP1_CAM_FF_FILT ISP0_CAM_RF_FILT I2S I2S CLK CLK CLK CLK CLK CLK JTAG_AP_TCK JTAG_AP_TMS JTAG_AP_TDI TP_JTAG_AP_TDO JTAG_AP_TRST_L JTAG JTAG JTAG JTAG RST I16 D NET_TYPE NET_TYPE ELECTRICAL_CONSTRAINT_SET I265 I264 USB_AP_P USB_AP_N USB_BBMUX_BB_P USB_BBMUX_BB_N USB_TS_BBMUX_P USB_TS_BBMUX_N USB11_AP_BBMUX_P USB11_AP_BBMUX_N CONN_E75_DPAIR1_P CONN_E75_DPAIR1_N CONN_E75_DPAIR2_P CONN_E75_DPAIR2_N TS_E75_DPAIR1_P TS_E75_DPAIR1_N TS_E75_DPAIR2_P TS_E75_DPAIR2_N USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB 25 25 25 26 25 26 25 25 25 25 24 25 24 25 24 25 24 25 25 25 25 25 NET_TYPE ELECTRICAL_CONSTRAINT_SET UART AREA_TYPE I2C_50S I2C_50S I2C_50S I2C_50S I2C_50S I2C_50S I2C_50S I2C_50S I2C_50S I2C_50S I2C_50S I2C_50S I2C_50S I2C_50S I2C_50S I2C_50S I2C_50S I2C_50S I1 TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE PHYSICAL_RULE_SET I2 TABLE_PHYSICAL_ASSIGNMENT_ITEM UART_50S * 45_OHM_SE I3 I4 I61 TABLE_SPACING_ASSIGNMENT_HEAD C NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET UART * * 3:1_SPACING UART UART * 2:1_SPACING I62 TABLE_SPACING_ASSIGNMENT_ITEM I98 I99 TABLE_SPACING_ASSIGNMENT_ITEM I100 I101 I102 NET_TYPE ELECTRICAL_CONSTRAINT_SET I103 SPACING PHYSICAL I228 I229 UART_50S UART_50S UART_50S UART_50S UART_50S UART_50S UART_50S UART_50S UART_50S UART_50S UART_50S UART_50S UART_50S UART_50S I237 I236 I174 I173 I175 I176 I177 I178 I179 I182 I181 I180 I232 I233 UART2_TS_ACC_RXD UART2_TS_ACC_TXD UART4_WLAN_RXD UART4_WLAN_TXD UART1_BB_CTS_L UART1_BB_RTS_L UART1_BB_TXD UART1_BB_RXD UART3_BT_CTS_L UART3_BT_RTS_L UART3_BT_RXD UART3_BT_TXD UART6_AP_RXD UART6_AP_TXD UART UART UART UART UART UART UART UART UART UART UART UART UART UART I124 25 I125 25 I226 14 I227 14 SPACING PHYSICAL 19 25 30 HSIC 19 25 30 TABLE_PHYSICAL_ASSIGNMENT_HEAD 22 NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET HSIC * 45_OHM_SE 22 22 TABLE_SPACING_ASSIGNMENT_HEAD 22 NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET HSIC * * 4:1_SPACING HSIC_RDY * * 2:1_SPACING 22 TABLE_SPACING_ASSIGNMENT_ITEM 20 22 TABLE_SPACING_ASSIGNMENT_ITEM 20 22 20 22 20 22 20 22 20 22 20 22 20 22 XTAL 25 26 NET_TYPE ELECTRICAL_CONSTRAINT_SET I192 TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CRYSTAL * * 5:1_SPACING I195 I196 TABLE_SPACING_ASSIGNMENT_ITEM 14 14 I197 I198 14 NET_TYPE 25 ELECTRICAL_CONSTRAINT_SET 25 SPI I199 SPACING HSIC HSIC HSIC HSIC HSIC_RDY HSIC_RDY HSIC_RDY HSIC_RDY HSIC_RDY HSIC3_BB_DATA HSIC3_BB_STB HSIC1_WLAN_DATA HSIC1_WLAN_STB GPIO_BB_HSIC_DEV_RDY GPIO_BB_HSIC_HOST_RDY GPIO_WLAN_HSIC_HOST_RDY GPIO_WLAN_HSIC_HOST_RDY GPIO_WLAN_HSIC_DEV_RDY 26 26 14 14 26 26 14 36 14 36 14 SPACING PHYSICAL XTAL_AP_24M_I XTAL_AP_24M_O AP_24M_O PMU_XTAL PMU_EXTAL CRYSTAL CRYSTAL CRYSTAL CRYSTAL CRYSTAL I230 TABLE_PHYSICAL_ASSIGNMENT_HEAD PHYSICAL_RULE_SET PHYSICAL HSIC HSIC HSIC HSIC HSIC HSIC HSIC HSIC HSIC I193 25 26 14 C TABLE_PHYSICAL_ASSIGNMENT_ITEM 22 I194 26 I92 AREA_TYPE 22 26 I93 NET_PHYSICAL_TYPE 22 I191 I90 B I2C1_SDA_1V8 I2C1_SCL_1V8 I2C0_SDA_1V8 I2C0_SCL_1V8 I2C2_SDA_3V0 I2C2_SCL_3V0 ISP0_CAM_RF_I2C_SCL ISP0_CAM_RF_I2C_SDA ISP1_CAM_FF_I2C_SCL ISP1_CAM_FF_I2C_SDA CONN_I2C1_SDA_1V8 CONN_I2C1_SCL_1V8 CONN_I2C2_SCL_3V0 CONN_I2C2_SDA_3V0 CONN_ISP0_CAM_RF_I2C_SCL CONN_ISP0_CAM_RF_I2C_SDA CONN_ISP1_CAM_FF_I2C_SCL CONN_ISP1_CAM_FF_I2C_SDA I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I231 4 B 29 29 TABLE_PHYSICAL_ASSIGNMENT_ITEM SPI_50S * 45_OHM_SE I2S TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM SPI * * 2:1_SPACING NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET I2S_50S * 45_OHM_SE TABLE_PHYSICAL_ASSIGNMENT_ITEM NET_TYPE ELECTRICAL_CONSTRAINT_SET I183 I184 I185 I186 I187 I188 I189 I190 I240 I241 I242 I243 PHYSICAL SPACING TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 SPI_50S SPI_50S SPI_50S SPI_50S SPI SPI SPI SPI SPI3_GRAPE_MISO SPI3_GRAPE_MOSI SPI3_GRAPE_SCLK SPI3_GRAPE_CS_L SPI_50S SPI_50S SPI_50S SPI_50S SPI SPI SPI SPI SPI2_IPC_MISO SPI2_IPC_MOSI SPI2_IPC_SCLK GPIO_BB_HSIC_RESUME SPI_50S SPI_50S SPI_50S SPI_50S SPI SPI SPI SPI SPI1_CODEC_MISO SPI1_CODEC_MOSI SPI1_CODEC_SCLK SPI1_CODEC_CS_L 16 * 26 I140 I143 18 I142 18 I141 18 I159 18 I144 SPACING_RULE_SET * I149 I150 2:1_SPACING I151 I161 NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL I244 SPACING I245 DWI_AP_CLK DWI_AP_DI DWI_AP_DO DWI DWI DWI I152 I153 I156 * 3:1_SPACING * 2:1_SPACING NET_TYPE TABLE_SPACING_ASSIGNMENT_ITEM DWI * I2S ELECTRICAL_CONSTRAINT_SET I145 AREA_TYPE I2S I2S 16 TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE2 SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM 16 DWI NET_SPACING_TYPE1 AREA_TYPE TABLE_SPACING_ASSIGNMENT_ITEM 16 I148 A NET_SPACING_TYPE2 I247 30 I246 SPACING PHYSICAL I2S_50S I2S_50S I2S_50S I2S_50S I2S_50S I2S_50S I2S_50S I2S I2S I2S I2S I2S I2S I2S I2S_50S I2S_50S I2S_50S I2S_50S I2S_50S I2S_50S I2S_50S I2S_50S I2S_50S I2S I2S I2S I2S I2S I2S I2S I2S I2S I2S0_CODEC_ASP_BCLK I2S0_CODEC_ASP_LRCK I2S0_CODEC_ASP_DIN I2S0_CODEC_ASP_DOUT I2S0_CODEC_ASP_SDOUT I2S0_CODEC_ASP_MCK I2S0_CODEC_ASP_MCK_R I2S3_CODEC_XSP_BCLK I2S3_CODEC_XSP_LRCK I2S3_CODEC_XSP_DIN I2S3_CODEC_XSP_DOUT I2S0_CODEC_XSP_SDOUT I2S2_BT_BCLK I2S2_BT_LRCK I2S2_BT_DIN I2S2_BT_DOUT 18 18 18 18 18 36 18 36 18 SYNC_MASTER=MIKE 18 PAGE TITLE 18 DRAWING NUMBER Apple Inc 14 R 14 NOTICE OF PROPRIETARY PROPERTY: 14 14 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 30 30 SYNC_DATE=11/30/2011 CONSTRAINTS: LOW SPEED BUS 18 051-9385 SIZE D REVISION A.0.0 BRANCH PAGE 151 OF 154 SHEET 36 OF 39 A EMBEDDED DISPLAYPORT MIPI PHYSICAL_RULE_SET TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE AREA_TYPE EDP_90D * 90_OHM_DIFF TABLE_SPACING_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_HEAD PHYSICAL_RULE_SET TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE BACKLIGHT TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET LEDA * * 3:1_SPACING LEDB * * 3:1_SPACING TABLE_PHYSICAL_ASSIGNMENT_ITEM EDP_50S * 45_OHM_SE TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM LED * LED PHYSICAL_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_PHYSICAL_ASSIGNMENT_ITEM MIPI_90D * 90_OHM_DIFF NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM EDP TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE * 4:1_SPACING * SPACING_RULE_SET NET_TYPE TABLE_SPACING_ASSIGNMENT_ITEM D MIPI0C * * 4:1_SPACING MIPI1C * * 4:1_SPACING ELECTRICAL_CONSTRAINT_SET PHYSICAL TABLE_SPACING_ASSIGNMENT_ITEM EDP_90D EDP_90D EDP_50S EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D EDP_90D I435 I436 I437 NET_TYPE I439 ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL MIPI_90D MIPI_90D MIPI_90D MIPI_90D MIPI_90D MIPI_90D I315 I316 I343 I342 I311 I312 I395 I394 I519 I518 I521 I520 I345 I346 I347 I348 I354 I356 I415 I414 I438 MIPI0C_CAM_RF_CLK_P MIPI0C_CAM_RF_CLK_N MIPI0C_CAM_RF_DATA_P MIPI0C_CAM_RF_DATA_N MIPI0C_CAM_RF_DATA_P MIPI0C_CAM_RF_DATA_N MIPI0C MIPI0C MIPI0C MIPI0C MIPI0C MIPI0C MIPI_90D MIPI_90D MIPI_90D MIPI_90D MIPI_90D MIPI_90D MIPI_90D MIPI_90D MIPI_90D MIPI_90D MIPI_90D MIPI_90D MIPI0C MIPI0C MIPI0C MIPI0C MIPI0C MIPI0C MIPI1C MIPI1C MIPI1C MIPI1C MIPI1C MIPI1C MIPI0C_CAM_RF_CLK_F_P MIPI0C_CAM_RF_CLK_F_N MIPI0C_CAM_RF_DATA_F_P MIPI0C_CAM_RF_DATA_F_N MIPI0C_CAM_RF_DATA_F_P MIPI0C_CAM_RF_DATA_F_N MIPI1C_CAM_FF_CLK_P MIPI1C_CAM_FF_CLK_N MIPI1C_CAM_FF_DATA_P MIPI1C_CAM_FF_DATA_N MIPI1C_CAM_FF_CLK_F_P MIPI1C_CAM_FF_CLK_F_N MIPI_90D MIPI_90D MIPI1C MIPI1C MIPI1C_CAM_FF_DATA_F_P MIPI1C_CAM_FF_DATA_F_N I440 21 21 I442 21 I441 21 I444 21 I443 21 I445 20 21 20 21 20 21 20 21 20 21 20 21 I447 I446 I449 I448 I450 I451 I452 21 I454 21 I453 21 I455 21 20 21 20 21 I457 I456 I458 20 21 I460 20 21 I459 C I462 I461 I463 I464 I465 NET_TYPE SPACING EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP EDP_AUX_P EDP_AUX_N EDP_HPD EDP_DATA_P EDP_DATA_N EDP_DATA_P EDP_DATA_N EDP_DATA_P EDP_DATA_N EDP_DATA_P EDP_DATA_N EDP_AUX_EMI_P EDP_AUX_EMI_N EDP_DATA_EMI_P EDP_DATA_EMI_N EDP_DATA_EMI_P EDP_DATA_EMI_N EDP_DATA_EMI_P EDP_DATA_EMI_N EDP_DATA_EMI_P EDP_DATA_EMI_N CONN_EDP_AUX_EMI_P CONN_EDP_AUX_EMI_N CONN_EDP_DATA_EMI_P CONN_EDP_DATA_EMI_N CONN_EDP_DATA_EMI_P CONN_EDP_DATA_EMI_N CONN_EDP_DATA_EMI_P CONN_EDP_DATA_EMI_N CONN_EDP_DATA_EMI_P CONN_EDP_DATA_EMI_N ELECTRICAL_CONSTRAINT_SET PHYSICAL 15 I482 15 I484 15 I483 15 I485 15 I487 15 I486 15 I489 15 I488 15 I490 15 I491 15 I492 15 I493 15 I494 15 I495 15 I496 15 I497 15 I498 15 I499 15 I500 15 I501 15 I502 15 I503 15 I504 15 I505 D SPACING 15 LED LED LED LED LED LED LED LED LED LED LED LED LED LED LED LED LED LED LED LED LED LED LED LED LED_IO1_A_R LED_IO1_B_R LED_IO2_A_R LED_IO2_B_R LED_IO3_A_R LED_IO3_B_R LED_IO4_A_R LED_IO4_B_R LED_IO5_A_R LED_IO5_B_R LED_IO6_A_R LED_IO6_B_R LED_IO_1_A LED_IO_1_B LED_IO_2_A LED_IO_2_B LED_IO_3_A LED_IO_3_B LED_IO_4_A LED_IO_4_B LED_IO_5_A LED_IO_5_B LED_IO_6_A LED_IO_6_B LEDA LEDB LEDA LEDB LEDA LEDB LEDA LEDB LEDA LEDB LEDA LEDB LEDA LEDB LEDA LEDB LEDA LEDB LEDA LEDB LEDA LEDB LEDA LEDB 30 30 30 30 30 30 30 30 30 30 30 30 15 30 15 30 15 30 15 30 15 30 15 30 15 30 15 30 15 30 15 30 15 30 15 30 15 C 15 15 15 15 15 TEMP SENSORS TABLE_SPACING_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET BOARD_TEMP * * 3:1_SPACING TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM BOARD_TEMP AUDIO/SPEAKER * TEMP_SENSE TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET AUDIO * * 3:1_SPACING NET_TYPE ELECTRICAL_CONSTRAINT_SET TABLE_SPACING_ASSIGNMENT_ITEM PHYSICAL SPACING I572 BOARD_TEMP BOARD_TEMP1 30 32 I574 BOARD_TEMP BOARD_TEMP2 30 32 BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP3_P BOARD_TEMP3_N BOARD_TEMP4_P BOARD_TEMP4_N BOARD_TEMP5_P BOARD_TEMP5_N BOARD_TEMP6_P BOARD_TEMP6_N BOARD_TEMP7_P BOARD_TEMP7_N BOARD_TEMP8_P BOARD_TEMP8_N NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL AUDIO AUDIO HP_MIC_P HP_MIC_N AUDIO_DIFF AUDIO_DIFF AUDIO AUDIO L81_AIN2_P L81_AIN2_N AUDIO_DIFF AUDIO_DIFF AUDIO_DIFF AUDIO_DIFF AUDIO AUDIO AUDIO AUDIO SPKR_L_VSENSE_N_FILT SPKR_L_VSENSE_P_FILT SPKR_L_VSENSE_N SPKR_L_VSENSE_P AUDIO_DIFF AUDIO_DIFF I584 I585 I587 I586 SPACING 18 I576 18 I577 I578 18 I579 18 I580 I589 I588 I591 B I590 I592 I593 I594 I595 I597 I596 I598 I599 I606 I607 I608 I609 I610 I611 I564 I565 I558 I560 A I570 I569 AUDIO_DIFF AUDIO_DIFF AUDIO_DIFF AUDIO_DIFF AUDIO AUDIO AUDIO AUDIO SPKR_R_VSENSE_N_FILT SPKR_R_VSENSE_P_FILT SPKR_R_VSENSE_N SPKR_R_VSENSE_P SPEAKER SPEAKER AUDIO AUDIO SPKR_L_P SPKR_L_N SPEAKER SPEAKER AUDIO AUDIO SPKR_L_CONN_P SPKR_L_CONN_N SPEAKER SPEAKER AUDIO AUDIO SPKR_R_P SPKR_R_N SPEAKER SPEAKER SPEAKER SPEAKER AUDIO AUDIO AUDIO AUDIO SPKR_R_CONN_P SPKR_R_CONN_N SPKR_L_FLR SPKR_R_FLR AUDIO_DIFF AUDIO_DIFF AUDIO AUDIO SPKR_L_SES_N SPKR_L_SES_P AUDIO_DIFF AUDIO_DIFF AUDIO AUDIO SPKR_R_SES_N SPKR_R_SES_P USB_90D USB_90D USB USB MIKEY_TS_P MIKEY_TS_N USB USB L81_MBUS_P L81_MBUS_N USB_90D USB_90D I600 I601 19 I581 19 I582 19 I583 19 I602 I603 19 I604 19 I605 19 BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP BOARD_TEMP 30 30 30 30 30 30 30 30 30 B 30 30 30 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 18 25 SYNC_MASTER=MIKE 18 25 PAGE TITLE SYNC_DATE=11/30/2011 CONSTRAINTS: DISPLAY/AUDIO 18 DRAWING NUMBER 18 Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9385 SIZE D REVISION A.0.0 BRANCH PAGE 152 OF 154 SHEET 37 OF 39 A DDR TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE TABLE_SPACING_ASSIGNMENT_HEAD PHYSICAL_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 DDR * AREA_TYPE SPACING_RULE_SET * 3:1_SPACING TABLE_PHYSICAL_ASSIGNMENT_ITEM DDR_50S * TABLE_SPACING_ASSIGNMENT_ITEM DDR_45_OHM_SE TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET DDR_90D * DDR_90_OHM_DIFF NAND TABLE_PHYSICAL_ASSIGNMENT_ITEM WIFI TABLE_SPACING_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET NAND_50S * 45_OHM_SE NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NAND0 * * 2:1_SPACING TABLE_PHYSICAL_ASSIGNMENT_ITEM SPACING PHYSICAL_RULE_SET * WIFI_50S WIFI_PWR100 * WIFI_PWR100 WIFI_PWR1000 * WIFI_PWR1000 D TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM * NAND1 * 2:1_SPACING TABLE_PHYSICAL_ASSIGNMENT_ITEM I221 I222 I223 I225 I226 I224 I228 I230 I229 I231 I232 I233 I235 I234 I236 I237 I238 I239 I240 DDR_50S DDR_50S DDR_90D DDR_90D DDR_50S DDR_50S DDR0_CA DDR0_DM DDR0_CK_P DDR0_CK_N DDR0_CKE DDR0_CSN DDR DDR DDR DDR DDR DDR DDR_50S DDR_50S DDR_90D DDR_90D DDR_50S DDR_90D DDR_90D DDR_50S DDR_90D DDR_90D DDR_50S DDR_90D DDR_90D DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR0_ZQ DDR0_DQ DDR0_DQS_P DDR0_DQS_N DDR0_DQ DDR0_DQS_P DDR0_DQS_N DDR0_DQ DDR0_DQS_P DDR0_DQS_N DDR0_DQ DDR0_DQS_P DDR0_DQS_N DDR_50S DDR_50S DDR_90D DDR_90D DDR_50S DDR_50S DDR DDR DDR DDR DDR DDR DDR1_CA DDR1_DM DDR1_CK_P DDR1_CK_N DDR1_CKE DDR1_CSN DDR_50S DDR_50S DDR_90D DDR_90D DDR_50S DDR_90D DDR_90D DDR_50S DDR_90D DDR_90D DDR_50S DDR_90D DDR_90D DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR1_ZQ DDR1_DQ DDR1_DQS_P DDR1_DQS_N DDR1_DQ DDR1_DQS_P DDR1_DQS_N DDR1_DQ DDR1_DQS_P DDR1_DQS_N DDR1_DQ DDR1_DQS_P DDR1_DQS_N DDR_50S DDR_50S DDR_90D DDR_90D DDR_50S DDR_50S DDR DDR DDR DDR DDR DDR DDR2_CA DDR2_DM DDR2_CK_P DDR2_CK_N DDR2_CKE DDR2_CSN DDR_50S DDR_50S DDR_90D DDR_90D DDR_50S DDR_90D DDR_90D DDR_50S DDR_90D DDR_90D DDR_50S DDR_90D DDR_90D DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR2_ZQ DDR2_DQ DDR2_DQS_P DDR2_DQS_N DDR2_DQ DDR2_DQS_P DDR2_DQS_N DDR2_DQ DDR2_DQS_P DDR2_DQS_N DDR2_DQ DDR2_DQS_P DDR2_DQS_N DDR_50S DDR_50S DDR_90D DDR_90D DDR_50S DDR_50S DDR DDR DDR DDR DDR DDR DDR3_CA DDR3_DM DDR3_CK_P DDR3_CK_N DDR3_CKE DDR3_CSN DDR_50S DDR_50S DDR_90D DDR_90D DDR_50S DDR_90D DDR_90D DDR_50S DDR_90D DDR_90D DDR_50S DDR_90D DDR_90D DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR3_ZQ DDR3_DQ DDR3_DQS_P DDR3_DQS_N DDR3_DQ DDR3_DQS_P DDR3_DQS_N DDR3_DQ DDR3_DQS_P DDR3_DQS_N DDR3_DQ DDR3_DQS_P DDR3_DQS_N 11 11 NET_TYPE 11 ELECTRICAL_CONSTRAINT_SET 11 I202 I203 I205 I206 I204 I208 I210 I209 I211 I212 I213 I215 I214 I216 I217 I218 I219 I220 I181 I182 I183 I185 I186 I184 I188 I190 I189 I191 I192 I193 I195 I194 I196 I197 I198 I199 I200 I38 I39 I41 I44 I43 I47 NET_TYPE SPACING PHYSICAL ELECTRICAL_CONSTRAINT_SET 11 11 I126 NAND0 NAND0 NAND0 NAND0 NAND0 NAND0 NAND0 NAND0 NAND0 NAND0 NAND0 NAND0 NAND0 NAND0 NAND0 NAND0 NAND0 NAND0 FMI0_AD FMI0_AD FMI0_AD FMI0_AD FMI0_AD FMI0_AD FMI0_AD FMI0_AD FMI0_ALE FMI0_CE0_L TP_FMI0_CE1_L TP_FMI0_CE2_L TP_FMI0_CE3_L TP_FMI0_CE4_L TP_FMI0_CE5_L TP_FMI0_CE6_L TP_FMI0_CE7_L FMI0_CLE I128 NAND_50S NAND0 FMI0_DQS 13 I131 NAND_50S NAND0 FMI0_RE_L 13 I133 NAND_50S NAND0 FMI0_WE_L 13 I144 NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND1 NAND1 NAND1 NAND1 NAND1 NAND1 NAND1 NAND1 NAND1 NAND1 FMI1_AD FMI1_AD FMI1_AD FMI1_AD FMI1_AD FMI1_AD FMI1_AD FMI1_AD FMI1_ALE FMI1_CE0_L I146 NAND_50S NAND1 TP_FMI1_CE2_L NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND1 NAND1 NAND1 NAND1 NAND1 TP_FMI1_CE4_L TP_FMI1_CE5_L TP_FMI1_CE6_L TP_FMI1_CE7_L FMI1_CLE 13 13 I68 I69 11 I70 11 I71 11 I72 11 I73 11 I74 11 I75 11 I76 11 I77 11 I78 11 I120 11 I121 11 I122 11 I123 I125 11 I245 NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S NAND_50S I124 I201 B AREA_TYPE WIFI_50S TABLE_PHYSICAL_ASSIGNMENT_ITEM D C TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE TABLE_SPACING_ASSIGNMENT_ITEM 13 I246 13 I247 13 I248 13 I249 13 I250 13 I251 PHYSICAL SPACING 50_WLAN_G 50_WLAN_A 50_WLAN_G_1 50_WLAN_A_DIPLX 50_WIFI_ANT_FD_2 50_WIFI_ANT_FD_1 50_WIFI_ANT_FD WIFI_50S WIFI_50S WIFI_50S WIFI_50S WIFI_50S WIFI_50S WIFI_50S 27 27 27 27 13 13 13 13 13 11 11 C 11 11 11 11 11 11 11 I135 11 I136 11 I137 11 I138 11 I139 11 I140 11 I141 11 I142 11 I143 11 12 13 13 13 13 13 13 13 13 13 13 12 12 I148 12 I149 12 I150 12 I151 I152 B 12 12 I154 NAND_50S NAND1 FMI1_DQS I156 NAND_50S NAND1 FMI1_RE_L 13 I160 NAND_50S NAND1 FMI1_WE_L 13 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 DDR VREF 12 TABLE_SPACING_ASSIGNMENT_HEAD I48 I37 I170 I171 A I172 I173 I174 I175 I176 I177 I178 I179 I180 12 NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET VREF * * 5:1_SPACING TABLE_SPACING_ASSIGNMENT_ITEM 12 12 12 NET_TYPE 12 ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING 12 12 I166 12 I167 12 I169 12 I168 12 I244 12 I243 12 I241 PWR PWR PWR PWR PWR PWR PWR PWR I242 PPVREF_DDR0_CA PPVREF_DDR0_DQ PPVREF_DDR1_CA PPVREF_DDR1_DQ PPVREF_DDR2_CA PPVREF_DDR2_DQ PPVREF_DDR3_CA PPVREF_DDR3_DQ 11 39 SYNC_MASTER=MIKE 11 39 PAGE TITLE SYNC_DATE=11/30/2011 CONSTRAINTS: DDR/FMI 11 39 11 39 DRAWING NUMBER 12 39 Apple Inc 12 39 R 12 39 NOTICE OF PROPRIETARY PROPERTY: 12 39 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9385 SIZE D REVISION A.0.0 BRANCH PAGE 153 OF 154 SHEET 38 OF 39 A PWR NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET PP_PWR * PWR_PMU NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET PWR * * 3:1_SPACING TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET GND * GND_PH TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM NET_TYPE VOLTAGE 1.1V 1.1V 1.1V 1.1V 1.1V 1.1V 1.1V 1.1V 1.1V 1.1V 1.1V 1.2V 1.2V 1.2V 1.2V 1.2V 1.8V 1.8V 1.8V 1.2V 1.2V 1.2V 1.1V 1.1V 3.3V 3.0V 1.7V 3.0V I221 I1 I2 I3 I4 I5 I6 I7 I8 I9 I12 I11 I10 I13 I15 I14 I16 I17 I18 I19 I20 I21 I23 I22 I24 I25 I26 I28 PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR NET_TYPE SPACING ELECTRICAL_CONSTRAINT_SET BUCK0A_LX0 BUCK0A_LX1 BUCK0A_FB PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PP1V1_CPU0_FET BUCK0B_LX0 BUCK0B_LX1 BUCK0B_FB PP1V1_CPU1_FET BUCK0C_LX0 BUCK0C_FB PP1V1_CPUB BUCK2_LX0 BUCK2_LX1 BUCK2_LX2 BUCK2_FB PP1V2_SOC BUCK3_LX0 BUCK3_FB PP1V8_S2R BUCK4_LX0 BUCK4_FB PP1V2_S2R BUCK5_LX0 BUCK5_FB PP3V3_OUT PP3V0_GRAPE PP1V7_VA_VCP PP3V2_S2R_USBMUX PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR LDO5 1.8V 1.8V 4.7V 4.2V 6.0V 6.0V 6.0V 5.25V 1.1V 1.1V PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PWR500 PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR I61 20.4V 20.4V 1.8V 1.0V 1.8V 1.8V 3.3V 3.3V 20.4V 20.4V PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PWR500 PP_PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PPLED_OUT_A PPLED_OUT_B PP1V8_PL0_F PP1V0_MIPI_PLL_F PP1V8_EDP_AVDD_AUX PP1V8_DP_AVDD_AUX PP3V3_S0_LCD_FERR PP3V3_LCDVDD_SW_F PPLED_BACK_REG_B PPLED_BACK_REG_A I64 6V PP_PWR PWR PPVBUS_USB_EMI 0.6V 0.6V 0.6V PP_PWR PP_PWR PP_PWR PWR PWR PWR PPVREF_DDR0_CA PPVREF_DDR0_DQ PPVREF_DDR1_CA 0.6V 0.6V 0.6V 0.6V 0.6V I222 PWR PWR PWR PWR PWR PWR PWR PWR PWR PPVREF_DDR1_DQ PPVREF_DDR2_CA PPVREF_DDR2_DQ PPVREF_DDR3_CA PPVREF_DDR3_DQ 4.6V 4.6V 1.8V PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR PP_PWR I227 3.55V PP_PWR PWR LDO10 3.2V 3.3V 3.0V 3.0V 3.0V 3.0V 2.8V 1.0V 1.1V 1.8V 1.2V I30 I31 I32 I33 I34 I35 I36 I37 I38 I39 I40 I41 I42 I43 I44 I45 I46 I47 I49 I51 I50 I53 I52 I54 I55 I56 I57 I58 I59 I60 I67 I68 I69 I70 I71 I72 I73 I74 I76 I75 A PHYSICAL I223 PP3V3_ACC PP3V0_S2R_HALL PP3V2_S2R_USBMUX PP3V0_IO PP3V0_SENSOR PP2V8_CAM PP1V0 PP1V1_SRAM PP1V8_ALWAYS PP1V2 VOLTAGE=0V GND GND GND I200 VOLTAGE=0V GND GND GND_AUDIO_CODEC LCM_LX PP6V0_LCM_VBOOST PP5V25_VLCM1 PP1V1_CPU0 PP1V1_CPU1 DAC_AP_VREF BATT_POS_RC BATT_VCC_WLAN PP_WLAN_VDDIO_1V8 D 29 29 18 29 30 29 29 I203 VOLTAGE=0V 29 I207 VOLTAGE=0V GND GND GND GND GND_SPKR_AMP1 GND_SPKR_AMP2 VOLTAGE=0V GND GND AGND_U3000 GND GND GND GND GND GND J2200_29_GND J2200_36_GND J2200_43_GND 29 30 29 29 I217 29 34 29 29 I224 VOLTAGE=0V I225 VOLTAGE=0V I226 VOLTAGE=0V 16 15 15 15 29 29 29 34 29 29 RST 29 34 29 TABLE_SPACING_ASSIGNMENT_HEAD 29 NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET RST * * 4:1_SPACING TABLE_SPACING_ASSIGNMENT_ITEM 29 34 29 29 NET_TYPE 29 34 ELECTRICAL_CONSTRAINT_SET 29 34 19 29 34 I165 29 34 39 I167 29 I171 29 34 I169 29 34 I170 29 34 39 I168 29 34 I172 29 34 I174 29 34 I173 29 34 I175 29 34 I176 29 34 I177 29 34 DSP_SW PP1V8 PP1V8_GRAPE PPVCC_MAIN PPBATT_VCC PP6V0_LCM_HI SPACING PHYSICAL I199 29 I166 I29 B TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_PHYSICAL_ASSIGNMENT_ITEM C GND TABLE_PHYSICAL_ASSIGNMENT_HEAD D I178 I179 29 32 34 I181 15 25 29 30 34 I182 29 32 34 I183 30 PHYSICAL SPACING RST RST RST RST RST RST RST RST RST RST RST GRAPE RST RST RST RST BB_TRST_L DBG_RST DEBUG_RST_L GSM_TXBURST_IND JTAG_AP_TRST_L RST_AP_1V8_L RST_AP_L GPIO_BB_RST_L RST_BB_PMU_L RST_BT_L RST_DET_L RST_GRAPE_L RST_L63_L RST_PMU_IN RST_WLAN_L SIMCRD_RST RST RST UD881_RST UD882_RST C 10 36 25 26 30 26 30 30 30 34 30 34 30 34 B 30 34 7 15 15 15 15 23 34 11 38 11 38 11 38 11 38 12 38 12 38 12 38 12 38 29 27 27 SYNC_MASTER=MIKE SYNC_DATE=11/30/2011 PAGE TITLE CONSTRAINTS: POWER / GND 18 29 DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9385 SIZE D REVISION A.0.0 BRANCH PAGE 154 OF 154 SHEET 39 OF 39 A ... I 440 21 21 I 442 21 I 441 21 I 444 21 I 443 21 I 445 20 21 20 21 20 21 20 21 20 21 20 21 I 447 I 446 I 449 I 448 I450 I451 I452 21 I4 54 21 I453 21 I455 21 20 21 20 21 I457 I456 I458 20 21 I460 20 21 I459... OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI D C 12 38 B 12 38 12 38 12. .. BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 BI 12 38 OUT 12 38 OUT 12 38 OUT 12 38 OUT 12 38