DESIGN OF PIXEL LEVEL CMOS READOUT CIRCUITRY FOR CONTINUOUS BIAS UNCOOLED BOLOMETRIC LWIR FOCAL PLANE ARRAYS

ABSTRACT Title of Thesis: DESIGN OF PIXEL LEVEL CMOS READOUT CIRCUITRY FOR CONTINUOUS BIAS UNCOOLED BOLOMETRIC LWIR FOCAL PLANE ARRAYS Troy Alexander Chesler, Master of Science, 2004 Thesis Directed By: Professor Martin Peckerar, Department of Electrical and Computer Engineering Modern IC foundries not provide large analog storage capacitors and therefore limit the charge well capacity for modern LWIR infrared readout integrated circuits A technique for increasing the effective capacity and integration times while maintaining linearity for a continuous biased bolometric LWIR focal plane arrays is presented Increasing integration times in the pixel reduces noise bandwidth and effectively increases dynamic range without saturating the integration capacitor Background suppression techniques, such as current skimming and charge subtraction reduce the overall temporal noise by subtracting the DC input current This thesis addresses the following: a) the practicality of continuous bias uncooled pixel designs b) optimum skimming implementation and c) the impact of background suppression on temporal and spatial noise ii DESIGN OF PIXEL LEVEL CMOS READOUT CIRCUITRY FOR CONTINUOS BIAS UNCOOLED BOLOMETRIC LWIR FOCAL PLANE ARRAYS By Troy Alexander Chesler Thesis submitted to the Faculty of the Graduate School of the University of Maryland, College Park, in partial fulfillment of the requirements for the degree of [Master of Science] [2004] Advisory Committee: Professor Martin Peckerar, Chair Professor Pamela Abshire Professor Timmer Horiuchi iii © Copyright by [Troy Alexander Chesler] [2004] Acknowledgements 1) Family iv 2) Jon Pfeifer 3) Tyler Erickson 4) Philippe Pouliquen 5) Tobi Delbruck 6) NVESD(Paul Blasé, Dr Paul Norton, Kent McCormack, and Dieter Lohrmann) 7) UMD (Marty, Pam, and Timmer) Lists of Tables, Figures / Illustrations Begin Here v Table of Contents Acknowledgements Table of Contents vi Chapter 1: Uncooled Infrared Imaging Thesis Contributions: Background Origins of Uncooled Thermal Imaging Military & Commercial Developments Bolometer Operation Pulse Biased DC Biased Temperature Sensitive Resistive Materials xvii Vanadium Oxide (VO2) xviii Amorphous Silicon (α-Si) xviii Uncooled Systems: Figures of Merit Responsivity NEP D* NE∆T & TCR Thermal Time Constant xxii Chapter 2: Fundamentals of Infrared Imaging .xxiii Introduction xxiii Wavelength Spectrum & Atmospherics xxvi Readout Systems .xxviii Vdet Readout Process Electronics xxviii Chapter 3: Background Suppression in the LWIR .xxxiii xxxiii Justification for Current Skimming & Charge Subtraction xxxiii Spatial & Temporal Noise .xxxiv Sensitivity & Dynamic Range .xxxvii DC Suppression Concepts xxxix Current Skimming Fundamentals Self-Biased Cascode Origin & Fundamentals xlvi Analysis of Pixel Circuitry DC Bias Point of DI FET Conductances of DI FET DC Bias Point of SCFET Conductances of SCFET Single MOS Skimming Pixel Self-Cascode Skimming Pixel Self-Cascode with MOS Capacitor Pixel Comparisons Charge Subtraction Concept with Non-Linear MOSCAP MOS Capacitor System Circuit Description Chapter 4: Associative Issues & Limitations with Current Skimming lxiii Subthreshold Transistor Mismatch lxiii Subthreshold Region Operation vii Current Mismatch vs Voltage Mismatch lxviii Body Effect in Self-Cascode lxix Effects of MOS Scaling .lxxi Power Supply lxxii Gate Oxide Thickness lxxiii Layout &Geometry of SCFET .lxxiv Noise lxxvii Temporal Noise lxxviii Spatial Noise .lxxviii Sensitivity lxxix NE∆T lxxx Bolometer Bias Variations .lxxxi Chapter 5: Signal & Noise lxxxii Signal lxxxii Bolometer Transfer Function lxxxii Pixel Transfer Function lxxxii Noise Sources lxxxii Flicker Noise .lxxxiii Shot Noise lxxxiv Reset Noise lxxxv Thermal Noise lxxxviii Theoretical Noise Analysis lxxxviii Single MOS .lxxxviii Self-Cascode Current Mode Skimmer .lxxxviii Chapter 6: IC Test CHIP Design lxxxix IRCHIP1 lxxxix Chip Description & Function .lxxxix Simulation & Test Results xcii IRCHIP2 xcix Chip Description & Function xcix Test Results xcix IRCHIP3 xcix Chip Desription & Function xcix Test Results .xcix Future Considerations 100 Conclusion .101 References 102 viii Chapter 1: Uncooled Infrared Imaging Thesis Contributions: • • • Development and demonstration of appropiate scaling techniques for selfbiased cascode transistors Designed a novel long wave infrared readout current skimming pixel specifically for continuous bias uncooled bolometer focal plane arrays Introduced charge subtraction as another alternative for background suppression as well as combining this with current skimming Background Origins of Uncooled Thermal Imaging Feeling heat waves emitted from hot objects yet seeing no visible light gave clues to early scientists that light is a form of radiation and exists beyond our eye’s response range These heat waves emanating from a recently distinguished fire, a hot rock, or molten iron ore elucidated the emissive nature of “invisible”(infrared) light Military & Commercial Developments Before World War II, there had been considerable research for uncooled imaging systems including sensing materials, electrical readout, and system packaging The two most prominent areas of uncooled materials research are 1) ferroelectric & pyroelectric bolometry and 2) resistive bolometry [1] The pyroelectric effect (not covered in this study) is a result of electrical polarization of opposing faces on certain types of polarized crystals that can have a “transient” electrical charge induced by means of a change in temperature [2] The resistive bolometer, which is the detector of choice for this study, is essentially a ix temperature sensitive resistor As the resistor absorbs electromagnetic radiation it heats up and changes its electrical properties thus changing the electrical resistance Usually, the material will be a thin metal or semiconductor film suspended over a air gap to provide adequate thermal isolation and minimize thermal conductance to its surroundings The thin film temperature rises when radiations impinges on the detector element With a rise in detector temperature, if the sensing film is a metal, the resistance increases while semiconductor film’s resistance decreases In the absence of radiation, the detector temperature decreases which causes the resistance to decrease (metal) and increases (semiconductor) [2] For the remainder of this thesis, characterization of the CMOS readout process will focus only the semiconductor resistive bolometric detector Efforts began in the mid 1970’s to create room temperature 2-D imaging arrays for both military and commercial applications At the time, cooled arrays had much better performance However, for most staring applications NE∆T’s (discussed later) of 0.01 K° to 0.1 K° with f/1 optics would be adequate for most military applications [4] 1983 marked the year for Honeywell’s vanadium oxide (VOx) bolometric arrays implementing a solid-state readout This was one of the first attempts of a silicon MEMS device, (Micro-Electro-Mechanical System) which promised to offer a new era of low cost monolithic imaging arrays By implementing silicon micro-machining, the highest thermal isolation could be attained thus leading to high array performance [4] Throughout the 70’s and 80’s, most of this research was classified under DOD guidelines for the military The x US Army Night Vision Laboratory (now NVESD) and DARPA saw a great advantage for developing potentially low-cost monolithic uncooled infrared focal plane arrays Moving from bump bonding the detector array to the readout to a monolithic approach improved the cost and yield of the array An important point that allowed uncooled infrared imaging to flourish from the 80’s, 90’s, and up until 2004 was the rapid improvement of the silicon process technologies (e.g Moore’s Law) The move to using CMOS over mature bipolar readouts provided better cost effective arrays with higher overall performance advantages (e.g lower power consumption) BiCMOS processes are expensive and require several additional mask steps Chief reasons for CMOS over bipolar and BiCMOS for uncooled applications are: 1) effective cost 2) availability 3) yield and 4) well defined and easy access to process parameters The industry standard is currently CMOS, however this does not discount bipolar or BiCMOS readouts for future applications Moore’s Law has scaled the device dimensions to sub-micron levels and now 1000 x 1000 element arrays or greater are realizable today There are have been considerable advancements in MEMS and material science providing extreme precision and high performance out of uncooled infrared focal plane arrays Bolometer Operation The mathematical expressions describing the physics of bolometer operation are not the focus of this thesis The process is governed by several parameters and constants while being controlled by several partial differential xi Chapter 6: IC Test CHIP Design IRCHIP1 Chip Description & Function This first test chip’s goal was to demonstrate the concept of current skimming by utilizing a linear array of self-cascode current mirrors to bias the self-cascode in the pixel The input current was set by an off chip potentiometer whose current was driven through a p-channel current buffer (common gate configuration) The current buffer’s geometry was identical to the direct injection transistor to achieve uniformity and relatively equal currents The diode connected current mirrors generated a voltage drop sufficient to bias the gate of the selfcascode with reasonable accuracy lxxxix Integration Capacitor (Poly2-Poly1) Well Contact Direct Injection Transistor Vref Reset SelfCascode Skimmer Source Follower Substrate Contact Figure 6.2: LWIR direct injection current skimming pixel MOS Capacitor Figure 6.3: LWIR direct injection current skimming pixel with experimental MOS capacitor The MOS capacitor is used as another form of background suppression called charge subtraction xc  13.2u  Mc =  ÷  5.1u   10.2u  Mb =  ÷  25.2u   13.2u  Mc =  ÷  5.1u   10.5u  Mb =  ÷  12.3u   13.2u  Mc =  ÷  5.1u   10.2u  Mb =  ÷  5.1u   13.2u  Mc =  ÷  5.1u   10.2u  Mb =  ÷  5.1u   13.2u  Mc =  ÷  5.1u   10.2u  Mb =  ÷  55.65u  Figure 6.4: Experimental self-cascode transistors with a fixed cascode ratio and a variable bias transistor ratio Common Gate Current Buffer (p-channel) SCFET Current Mirror Array Current Mode Skimmer Figure 6.5: The skimmer is biased by an off-chip resistor Then the current is buffered into a current mirror being divided into 17 paths sensitivity is controlled by the number of current paths in the mirror xci Simulation & Test Results The following self-cascode I-V data was taken from MOSIS run T3AJ Vgs = 600m V in Figure 6.4 The curves (AMI C5N 0.5um) with device dimensions above generated 1.80E-08 were taken at various gate voltages ranging from 500mV to 2V 1.60E-08 1.40E-08 1.20E-08 Mc: 13.2u/5.1u Mb: 10.2u/5.1u 1.00E-08 Ids Mc: 13.2u/5.1u Mb: 10.5u/12.3u Mc: 13.2u/5.1u Mb: 10.2u/25.2u 8.00E-09 Mc: 13.2u/5.1u Mb: 10.2u/55.65u 6.00E-09 4.00E-09 2.00E-09 00 E+ 00 E8 01 00 E -01 20 E + 00 60 E+ 00 E+ 40 E+ 80 E+ 20 E+ 60 E+ 00 E+ 40 E+ 80 E+ 00 0.00E+00 Vds Vgs = 700m V 1.60E-07 1.40E-07 1.20E-07 Ids 1.00E-07 Mc: 13.2u/5.1u Mb: 10.2u/5.1u Mc: 13.2u/5.1u Mb: 10.5u/12.3u 8.00E-08 Mc: 13.2u/5.1u Mb: 10.2u/25.2u Mc: 13.2u/5.1u Mb: 10.2u/55.65u 6.00E-08 4.00E-08 2.00E-08 00 E+ 00 00 E8 01 00 E01 20 E+ 60 E+ 00 E+ 40 E+ 80 E+ 20 E+ 60 E+ 00 E+ 40 E+ 80 E+ 00 0.00E+00 Vds xcii F igure 6.7: Vgs Vgs==500mV 500mV 1.4 0E-09 1.40E- 09 1.2 0E-09 1.20E- 09 1.0 0E-09 1.00E- 09 6.0 0E-10 6.00E- 10 4.0 0E-10 4.00E- 10 2.0 0E-10 2.00E- 10 3.50E+00 3.50E+00 0.00E+0 0.00E+00 0.00 E+0 0.00E+00 Ids Ids 8.0 0E-10 8.00E- 10 Vds Vds xciii Vgs = 800m V 8.00E-07 7.00E-07 6.00E-07 Mc: 13.2u/5.1u Mb: 10.2u/5.1u Mc: 13.2u/5.1u Mb: 10.5u/12.3u 4.00E-07 Mc: 13.2u/5.1u Mb: 10.2u/25.2u Mc: 13.2u/5.1u Mb: 10.2u/55.65u 3.00E-07 2.00E-07 1.00E-07 00 E+ 00 E8 01 00 E -01 20 E +00 60 E + 00 00 E + 00 40 E + 00 80 E +00 20 E + 00 60 E + 00 00 E + 00 40 E + 00 80 E+ 00 0.00E+00 Vds Vgs = 900m V 2.50E-06 2.00E-06 Mc: 13.2u/5.1u Mb: 10.2u/5.1u Mc: 13.2u/5.1u Mb: 10.5u/12.3u 1.50E-06 Mc: 13.2u/5.1u Mb: 10.2u/25.2u Ids Mc: 13.2u/5.1u Mb: 10.2u/55.65u 1.00E-06 5.00E-07 0.00E+00 00 E+ 00 00 E8 01 00 E01 20 E+ 60 E+ 00 00 E+ 40 E+ 00 80 E+ 20 E+ 60 E+ 00 E+ 40 E+ 00 80 E+ 00 Ids 5.00E-07 Vds xciv Time (s) Figurexxx xcv 9.93E-04 8.79E-04 7.64E-04 6.50E-04 5.35E-04 4.20E-04 3.06E-04 1.91E-04 7.66E-05 -3.80E-05 0.8 -1.53E-04 -2.67E-04 -3.82E-04 -4.96E-04 -6.11E-04 -7.26E-04 -8.40E-04 -9.55E-04 Pixel Output (V) 0.9 Current Skimming @ 78.5% (Iskim = 15.7nA, Idi = 20nA, DR = 680mV, tint = 212us) Pixel Output (V) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 xcvi xcvii xcviii IRCHIP2 dlkj Chip Description & Function kjflksdjfkljfks Test Results jhfksfhksdjf IRCHIP3 kfjdslkfjlsdf Chip Desription & Function Fjdslkfjlskdjfldsjfkdflskdf;l Test Results kjfldjfldsfksdfjksd xcix Future Considerations 100 Conclusion 101 References 102 103 .. .DESIGN OF PIXEL LEVEL CMOS READOUT CIRCUITRY FOR CONTINUOS BIAS UNCOOLED BOLOMETRIC LWIR FOCAL PLANE ARRAYS By Troy Alexander Chesler Thesis submitted to the Faculty of the Graduate School of. .. from pixel to pixel and requires (off focal plane) non-uniformity correction methods to keep track of pixel bias levels to interpret the appropriate injection levels Usually off-chip DSP circuitry. .. details of background suppression methods for continuous bias uncooled infrared focal plane arrays, which aim to improve pixel signal-to noise Spatial & Temporal Noise Without careful design,