Overview
Introduction
Throughout the history of human scientific research, nature has inspired numerous significant discoveries The advancement of computer and electronic technologies has increasingly linked scientific endeavors to biology, healthcare, and lifestyle improvements In the realm of artificial intelligence, innovations have led to the development of computers and devices capable of mimicking human abilities such as reading, listening, and thinking Drawing from evolutionary principles, scientists and engineers are creating electronic design techniques that mirror biological processes These techniques utilize evolutionary theory to develop adaptive circuits that can adjust to environmental changes, akin to living organisms Currently, adaptive circuits are extensively utilized in fields such as communications, biomedical engineering, and life sciences.
The rise of adaptive circuits has heightened the significance of low power designs, driven by advancements in VLSI technology and the proliferation of battery-operated systems in computing and telecommunications These developments necessitate lighter, smaller devices with extended operational lifespans Consequently, the trend towards designing low power adaptive circuits is increasingly vital to satisfy this growing demand.
This dissertation investigates low power adaptive circuits across two key domains: a log domain filter designed for audio frequency system identification and a temperature-insensitive oscillator tailored for low power radio frequency communication, including its application in phase-locked loops Detailed discussions are presented in Part.
Contributions
My work in this dissertation can be summarized as follows.
1 Fabricate through MOSIS and test an adaptive first order low pass filter.
2 Investigate the adaptive behavior under the non-ideal condition of a current mirror ratio mismatch.
3 Analyze the harmonic distortion of the first order low pass filter using numerical methods
3 Design, simulate, fabricate through MOSIS and test a low power CMOS temperature sensor for on-chip temperature gradient detection.
4 Design, simulate, fabricate through IBM and test a low power temperature insensitive oscillator.
5 Design, simulate, fabricate through IBM and test a low power phase locked loop based FM receiver at 2.2GHz in collaboration with colleague Bo Li at the University of Maryland.
6 Design, simulate, fabricate through IBM a low power phase locked loop based BFSK receiver at 20GHz
7 Analyze the phase locked loop models numerically using Matlab
AN ADAPTIVE LOG DOMAIN FILTER
AN ADAPTIVE LOG DOMAIN FILTER FOR SYSTEM
Background and System Identification
Adaptive signal conditioning is a crucial tool in scientific and engineering fields, including communications and biomedical engineering It plays a significant role in complex applications by dynamically filtering out noise and enhancing signal quality In system identification, effective control laws leverage limited information to robustly adjust the adaptive system's parameters, ensuring they align with an unknown system.
Several research groups have explored filtering applications utilizing floating gate MOS circuits Hasler et al introduced the auto-zeroing floating gate amplifier (AFGA), highlighting its effectiveness in band pass filter structures with low frequency response Chawla et al developed programmable second-order transconductor-capacitor filters using two floating gate operational transconductance amplifiers (OTAs) Graham et al showcased a programmable array of band pass filters that decompose audio signals and facilitate analog preprocessing prior to digital transformation Fernandez et al described a micro-power low pass filter implemented with floating gate metal oxide semiconductor (FGMOS) transistors, along with a 1.25-V Gm-C filter and a 0.8 V, 360 nW Gm-C biquad Minch advanced circuits and synthesis techniques employing multiple input translinear elements (MITEs) for diverse signal processing applications Additionally, Yamasaki and Shibata reported a high-speed, low-power median filter utilizing a majority voting circuit based on floating gate MOS technology.
[13] reported a 1.2V 5μW class-AB CMOS log domain integrator with multi-decade tuning
Recent advancements in integrated analog adaptive filters have been reported by several research groups Notably, Juan et al and Stanacevic and Cauwenberghs developed analog transversal finite impulse response (FIR) filters that feature adaptive weight adjustments Additionally, Ferrara and Widrow introduced a time-sequenced adaptive filter that enhances least mean square (LMS) adaptive filters for more precise slow adaptation Furthermore, Figueroa et al successfully implemented a 48-tap mixed-signal adaptive FIR filter, achieving a remarkable operating frequency of 200MHz with a power consumption of just 20mW, delivering 19.2 GOPS and a differential output current of 6mA.
Recent advancements in adaptive analog circuits have led to the design of an analog synapse circuit that implements the LMS learning rule, as demonstrated by [18] Kucic et al [19] have developed programmable and adaptive analog filters utilizing arrays of floating gate circuits, which employ matched filtering and weight perturbation algorithms Additionally, Xie and Al-Hashimi [20] introduced an analog adaptive filter designed through a wave synthesis technique These systems predominantly utilize LMS-based adaptation algorithms, which iteratively adjust weights to optimize performance along the error surface The adaptive filters are structured as discrete FIR filters, featuring a tapped delay line and adjustable weights, with outputs determined by a weighted sum of input sequences.
Multiple input translinear elements (MITEs) offer a compact and efficient way to implement log domain filters These devices generate an output current that is an exponential function of the weighted sum of their input voltages By utilizing multiple input floating gate transistors in weak inversion, we can effectively realize these MITE configurations.
A floating gate MOS transistor is a specialized type of MOS transistor with its gate entirely surrounded by an insulator, creating a potential barrier that allows for nonvolatile charge storage Due to the absence of a DC path to ground, external inputs are coupled capacitively This is achieved through linear poly to poly capacitors formed using a second polysilicon layer While charge adjustment can be performed via hot-carrier injection or tunneling, these methods are not essential for this study An ideal N-input MITE's circuit symbol is illustrated in Fig 2.1, with its transfer function defined accordingly.
I 0 exp( 1 1 2 2 )/ (2.1) where I 0 is a pre-exponential scaling current,
In the context of floating gate MOS transistors, the input voltage \( V_i \) is weighted by the dimensionless positive weight \( w_i \), while the threshold voltage \( V_T \) and the subthreshold slope factor \( \kappa \), which is less than 1, play crucial roles in device performance The thermal voltage \( \phi_t \) is defined as \( kT/q \), and the pre-exponential current \( I_0 \) is influenced by several factors including carrier mobility \( \mu \), gate oxide capacitance \( C_{ox} \), the width-to-length ratio \( W/L \), and the subthreshold slope factor \( \kappa \) The primary advantage of employing floating gate MOS transistors in weak inversion for the implementation of MITEs lies in their compatibility with standard CMOS fabrication processes.
Fig 2.1: Circuit symbol for ideal N-input MITE.
The research focuses on creating a low-power adaptive filtering system for effective system identification By utilizing adaptive dynamical system theory, the study develops robust control laws The approach begins with a first-order low-pass filter for reference model estimation, integrating current-mode log domain filter architecture and floating gate MOSFETs operating in subthreshold to achieve precise and stable learning rules for system parameters.
Current-mode log domain filters utilize transistors in weak inversion mode, making them ideal for low power circuit design In this mode, the current through a unit transistor is typically below hundreds of nanoamperes, significantly lower than in strong inversion The gate-to-source voltage drop in weak inversion is around or below the threshold voltage, allowing for the use of low supply voltages and further minimizing power consumption Additionally, the exponential transfer function in weak inversion offers an extended dynamic range and enhanced tunability, contributing to overall efficiency.
The model-based learning method models an unknown system by tuning an adaptive estimator to track the operation of the unknown system as shown in Fig 2.2.
By applying the same input signal to both unknown and adaptive filters, we can generate adaptive updates for system parameters, effectively addressing the classical problem of system identification This approach not only minimizes output error but also allows for the estimation of unknown system parameters Leveraging Lyapunov stability, this method is particularly effective for the adaptive control of analog continuous-time filters These filters provide significant advantages, including reduced filter structures, fewer coefficients, and superior performance compared to discrete FIR filters, making them ideal for modeling similarly complex plants.
Fig 2.2: Model-based learning method for the classical problem of system identification.
We develop control laws for a tunable filter to tackle the classical challenge of system identification, where an input signal is applied to both an unknown system (plant) and an adaptive estimator (model) that estimates the plant's parameters The error, defined as the difference between the plant and the model, is utilized to refine the parameters Our design focuses on adaptive laws that not only ensure the stability of the learning process but also facilitate VLSI implementation.
In the system identification problem, an input signal (u) is simultaneously applied to both the plant and the model filters The error (e1), defined as the difference between the outputs of the plant (x1) and the model (x2), serves as a basis for adjusting the parameters of the model (x3 and x4).
The unknown plant and the adaptive model filters are described by the state- variable representation:
The equations presented describe the relationship between plant output and model output in a control system Specifically, equation (2.3) illustrates that the output of the plant, denoted as x1, is influenced by the plant's cut-off frequency A and gain B, while the input u affects both filters Equation (2.4) indicates that the model output, represented as x2, depends on the estimates of the cut-off frequency x3 and gain x4, along with the input u These relationships are crucial for understanding the dynamics of the system's performance.
To evaluate the performance and stability of the adaptation, we develop an error system that measures the discrepancies between the outputs of the plant and model, as well as the differences between the estimated and actual cut-off frequency and gain.
We focus on adaptive laws that adjust system parameters to ensure all errors diminish over time By examining the dynamics of the error system, we can concentrate on the key aspects of the control problem.
Circuit Implementation, Simulation and Experimentation
3.1.1 MITE Implementation of Log Domain Filters
The log domain MITE filter topology illustrated in Fig 3.1 is designed for a first-order low-pass transfer function, serving both the plant and the filter The labels in parentheses denote the filter variables, while the remaining labels pertain to the plant components.
Log domain filters are an advanced evolution of traditional static translinear circuits, providing a broad tuning range, extensive dynamic range, and efficient low-power performance The circuit depicted in Fig 3.1 facilitates the implementation of both plant and model systems, with model parameters indicated in parentheses for clarity To enhance understanding, cascode transistors are omitted from the illustration In subthreshold operation, the MITE current exhibits an exponential relationship with the summed inputs.
The equation I = 4(3 + gain) = (3.4) illustrates the relationship where m is defined as κq/2kT, representing half the ratio of the subthreshold slope factor κ to the thermal voltage kT/q Additionally, I_p signifies the pre-exponential constant current that is influenced by factors such as carrier mobility μ, gate oxide capacitance C_ox, width-to-length ratio W/L, threshold voltage V_T, subthreshold slope factor κ, and thermal voltage φ_t.
We apply Kirchoff’s Current Law (KCL) at the capacitive node to find the relationship between the MITE currents and the capacitive current:
Since V 2 and V 3 together control a constant current I 3, their time derivatives are opposite in sign but equal in magnitude:
We determine the transfer function for the output current I 4 by differentiating it, then substituting our results from KCL and MITE relationships above:
The first-order low-pass transfer function (3.7) features a cut-off frequency defined by the equation ω = mI τ / C This cut-off frequency is directly proportional to the ratio of bias current to capacitance, allowing for easy tuning by adjusting the bias current Additionally, the gain is an exponential function of the voltage difference between V_gain and V_g_ref, which can also be easily adjusted by varying the V_gain voltage.
The same input current I in is applied to both plant and filter The output of the plant is I p The output of the filter is I f
3.1.2 MITE Implementation of Learning Rules
The plant and model function as first order low pass filters, featuring two adjustable parameters: gain and cut-off frequency We have applied simplified learning rules based on the Lyapunov method, as outlined in Section II These learning rules utilize the system output error and the temporal derivative of the model output as inputs The temporal derivative is calculated using a circuit configuration depicted in Fig 3.2, where a wide range operational transconductance amplifier (OTA) operates as a voltage follower with a capacitive load, generating the necessary output current.
This current relates to the input voltage as
I d d (1 d / m 12 ) 1 f (3.9) where g m 12 is the transconductance of transistors M1 and M2 in the OTA When d m C g s 12 / , the output current is approximately the derivative of the input voltage
Fig 3.2: Circuit for computing temporal derivative with mismatch compensation.
To enhance the performance of the g m 12 large, we utilize input devices close to the threshold Instead of converting the filter output current into voltage, we directly employ the intermediate node voltage V3 as the input for temporal derivative calculations It's important to note that the adaptation rule is defined as f f f p I I KI, where İ = I K V̇.
In the circuit illustrated in Fig 3.2, nodes nd1yank and nd2yank regulate two NMOS transistors that subtract currents from I d 1 and I d 2 to address transistor mismatch The adjusted currents, I d 1 and I d 2, are then forwarded to the subsequent stage of the circuit Ultimately, the derivative circuit produces two output currents, I d 1 and I d 2.
Fig 3.3: Circuit for four quadrant multiplication.
The cut-off frequency learning rule requires a four quadrant multiplication,implemented using the MITE circuit shown in Fig 3.3 with inputs I d 1, I d 2, I p and
I f and outputs I nm 1 and I nm 2 Transistor groups (M1, M2, M4, M6), (M1, M2, M5, M7), (M1, M3, M4, M8) and (M1, M3, M5, M9) form four translinear loops which give: bias d f I I
If we apply KCL at nodes I nm 1 and I nm 2, the difference between the currents flowing in the two nodes can be expressed as:
The update direction for cut-off frequency of the first order low pass filter
3 e x e is given by the current difference between I nm 1 and I nm 2
Figure 3.4 illustrates the schematics for learning rules and summing nodes, with panel (a) depicting the integrator for gain adaptation, where the inputs are the intermediate node voltages Vp_out and Vf_out, resulting in the output voltage Vg_est Panel (b) presents the cascode arrangement utilized in current mirrors to reduce the Early effect and current mismatch, while enhancing the gain for off-frequency adaptation, with inputs consisting of two currents, I nm 1 and I nm 2, and producing the output voltage Vτ_est.
Fig 3.4: MITE implementation of learning rules for gain and cut-off frequency.
In our study, we utilize HSPICE to simulate the circuit with BSIM3v3 models tailored for 0.5μm technology To prevent floating-node issues in the simulator, we implement a technique involving a voltage-controlled voltage source, V_floating_gate, which connects the floating gate to ground via a large resistor, R Since V_floating_gate follows the floating gate voltage, there is no current flow through R This artificial DC path to ground significantly enhances numerical convergence in the HSPICE circuit simulation.
Fig 3.5: Technique used to avoid floating-node problems in the simulator.
Figure 3.6 illustrates the adaptation process using a 10 kHz square wave input signal, with current pulses ranging from 20 nA to 160 nA In panel (a), the error (I_e) between the plant and filter outputs is depicted, while panel (b) presents the actual voltage (V_τ) alongside the estimated voltage (V_τ_est) Panel (c) compares the actual gain (V_gain) with the estimated gain (V_g_est) To evaluate the filter's adaptability, we intentionally varied the plant's cut-off frequency by a factor of 16 and the gain by a factor of 11, resulting in different V_τ values.
I of 40nA from 0-2ms, 80nA from 2-3.5ms, 20nA from 3.5-5ms, 160nA from 5-
6.5ms, and 10nA from 6.5-8 ms The voltage V gain varies as 1.4V from 0-1ms, 1.5V from 1-2.5ms, 1.35V from 2.5-4ms, linearly increases from 1.4V to 1.5V from 4- 5.5ms, linearly decreases from 1.5V to 1.45V from 5.5-7.5ms, and remains constant at 1.45V from 7.5-8ms For all changes in V and V gain , V _ est and V g _ est accurately track the new values respectively I e 0 when V _ est V and V gain V g _ est ref
V g _ is fixed at 1.5 V The adaptation rate depends on signal strength, currents I ga and I a , and capacitors C g and C .
Fig 3.6: Adaptation of gain and cut-off frequency for a 10kHz square wave input.
We conducted simulations of our adaptive system using various input types, including harmonic sine waves with frequencies of 10kHz, 20kHz, 40kHz, and 80kHz, as well as geometrically spaced sine waves The latter comprised a summation of 14 sine waves with a frequency ratio of 2π/5, covering a range from 5kHz to 97kHz.
[26] For those two very different inputs, V _ est accurately tracks V and V g _ est tracks
V gain , and I e approaches zero when adaptation is completed.
Fig 3.7: Die photograph of the chip for the adaptive first order low pass filters.
We present measurements from a first-order adaptive filter fabricated using a commercially available two poly, three metal 0.5 µm CMOS technology The chip features various components, including plant and model filters, learning circuits, and input/output buffers, as depicted in the photomicrograph in Fig 3.7 Specifically, Part A consists of two current mirrors that scale down the input currents for the plant and model filters, while Parts B and C represent the plant and model filters, respectively Part D includes the derivative circuit, and Parts G consist of integration circuits for gain and cut-off frequency learning rules Additionally, Part H is a current output buffer with dual current conveyors for amplifying output currents, and Part I is a voltage output buffer equipped with two wide-range amplifiers to buffer the gain and cut-off frequency control voltages.
The test setup for the adaptive first-order low-pass filters includes a schematic representation of the input voltage-current converter, specifically the Howland current source, along with on-chip current conveyors and output current-voltage converters.
The experimental setup, illustrated in Fig 3.8, involves exposing the chip to UV light prior to each test to eliminate any charges on the floating gate nodes To ensure all transistors function in the subthreshold region, both input and output currents are limited to several hundred nano-amperes An on-chip 50:1 current mirror effectively scales down the input currents, while an off-chip Howland current source, utilizing resistor values of R1 = R2 = R3 = R4 = 97.6 kΩ, is employed to convert input voltages into corresponding input currents.
The resistors generate about 0.7 nA root-mean-square (RMS) noise current at room temperature
Mismatch and Harmonic Distortion Analysis
Fig 4.1: Circuit for computing temporal derivative with mismatch compensation (shown in Chapter 3 as Fig 3.2)
The derivative circuit shown in Fig 4.1 includes two mismatch adjustment NMOS transistors M3 and M4 which provide a constant offset to adjust the currents I d 1 and
I d Thus the actual currents passing on to the multiplier circuits in the next stage are
I d and I d 2 We use the two voltages nd1yank and nd2yank to partially cancel current mirror mismatches in the implementation of learning rules
Fig 4.2: MITE implementation of learning rules for cut-off frequency (shown in Chapter 3 as Fig. 3.4c)
In the implementation of the cut-off frequency learning rule, as illustrated in Fig 4.2, it is important to consider that the circuit's mismatch is primarily due to current mirror discrepancies This results in an actual ratio of 1:x, contrasting with the ideal ratio of 1:1, where x remains a constant close to 1 Without any compensation for this mismatch, the circuit's performance may be adversely affected.
I 2 2 1 / (4.2) where I p is the output current of the plant filter and I f is the output current of the model filter I d 1 and I d 2 are the output currents of the derivative circuit, and c and
I bias are constants When mismatch compensation is introduced as in Fig 4.1, the modified currents I 1 and I 2 that replace the ideal currents I 1 and I 2 are given by:
The equation I 2 = 2 - 2 + 1 - 1 / (4.4) represents the relationship between the currents I ny 1 and I ny 2 flowing in NMOS transistors M3 and M4, respectively, to ground in the temporal derivative circuit illustrated in Fig 4.1, where c' is a constant.
The tail current of the differential pair for the cut-off frequency circuit
I a is constant This equality holds for all values of I p and I f , in particular for I p I f , so
Assuming the adaptation time (t₀) is identical for both scenarios, and that the mismatch compensation from M3 and M4 effectively enables convergence to the same voltage at capacitor Cτ, we can derive significant results.
To simplify our analysis, we focus on the scenario where (I ny 1 > 0, I ny 2 = 0), a condition consistently observed in all tested chips By substituting equations (4.1) to (4.4) into equation (4.7), we can determine the current I ny * 1 that effectively compensates for the current mirror ratio mismatch of 1:x.
1 t bias t p f tail d t t a bias tail d ny dt I I I dt I xI cI dt I I dt x I I
The current difference I 1 I 2 controls the capacitor voltage, which determines the estimated cut-off frequency Assuming an initial capacitor voltage of 0V, we obtain
If we further assume that the plant and model filters share the same DC current level, i.e I p I f I b , we obtain
By substituting (4.9) and (4.10) into (4.8), we obtain
(4.11) where X , Y, and Z are defined as
In ideal matched current mirrors,
In our analysis, we examine three mismatch conditions: x > 1, x < 1, and x = 1 Our primary focus is on the scenario where x > 1, as the outcomes differ significantly when x < 1 Notably, when x = 1, there is no mismatch, leading to an expected result of I * ny 1 being zero.
First we examine the consequences of values for I ny 1I ny * 1 which do not exactly compensate the mismatch Since I ny * 1 0, we know from (6.11) that Z V c _ Y, so
Let us go back to equations (4.7), (4.8) and (4.11) By examining the inequality corresponding with Eqn (4.7) and its effects on Eqns (4.8) and (4.11), we find:
When I ny 1 is too high, the cut-off frequency voltage is underestimated.
Next we consider the effect of a change in gain on the cut-off frequency adaptation Assuming that V _ est tracks V accurately and has converged to V , which implies that
ny ny c ny ny c c c ny ny
V _ _ Therefore an increase in gain causes the cut-off frequency voltage to be overestimated
In this section, we analyze the impact of the cut-off frequency on its adaptation By differentiating equation (4.11), we assume a constant gain, leading to the conclusion that X, Y, and Z remain constant, resulting in Ẋ = Ẏ = Ż = 0.
Therefore V V c _ I ny * 1 , and an increase in the cut-off frequency voltage requires higher compensation current to balance mismatch
Fig 4.3 : Test results of adaptive filter illustrating the case x>1 for mismatch analysis: changes in gain create artifacts in the estimated cut-off frequency (shown in Chapter 3 as Fig 3.10)
Fig 4.4: Test results of adaptive filter illustrating the case 0 1, the estimated cut-off frequency increases alongside the true and estimated gain, while the true cut-off frequency remains unchanged Conversely, the estimated cut-off frequency voltage decreases as the gain diminishes, despite the true cut-off frequency staying constant.
In the range of 0 < x < , the estimated cut-off frequency voltage shows a slight decrease with an increase in gain, while it increases when the gain decreases, despite the actual cut-off frequency remaining constant Table 4.1 provides a summary of the mismatch analysis results across four cases.
Table 4.1 (x1/x 1, gain /gain ) are illustrated by the data in Figs 4.3 and 4.4 at the locations labeled by symbols (*, **, #, ##).
I gain vs V _ est V vs I * ny 1
Table 4.1: Effects of the current mirror ratio mismatch on the estimated cut-off frequency and compensating current
Fig 4.5: Log domain MITE filter topology for a first order low pass transfer function used for both plant and filter (shown in Chapter 3 as Fig 3.1)
The adaptive system depicted in Fig 4.5 utilizes linear filters with transistors M1, M2, M3, and M4 functioning in the subthreshold region An increase in input current causes these transistors to operate at the boundary between subthreshold and above threshold regions, leading to distortion in the filter's output and impacting the system's adaptability In this chapter, we employ Matlab models to analyze the harmonic distortion of the filter during this transitional operating range By using the EKV model to assess transistor behavior at the threshold edge and comparing it with results from both subthreshold and above threshold models, we aim to provide a more precise understanding of the filter's real-world performance.
We define following parameters to illustrate the three transistor models which will be used to analyze the harmonic distortion
V GS gate to source voltage
In subthreshold operation the current of a transistor is an exponential function of voltage as in equation (4.18) Here we take the slope factor as 1 for simplicity. t
In strong inversion saturation operation the current of a transistor follows square law as in equation (4.19)
The operation transfer functions exhibit discontinuity as V GS transitions from below to above the threshold voltage To address this issue, the EKV model has been developed as a mathematical solution A simplified version of the EKV model is presented in equation (4.20).
When w is very small, Taylor series tells us w w w w w w
Substituting equation (4.21) into the EKV model (4.20) reveals its consistency with the subthreshold model (4.18) This agreement occurs when the gate to source voltage V GS is approximately equal to the threshold voltage V T, ensuring that both x and w remain sufficiently small.
While when x is large, so that 2 1 x e
The EKV model, as defined by Equation (4.20), aligns with the transfer function in strong inversion saturation, as indicated in Equation (4.22) For consistency, the gate-to-source voltage (V GS) must significantly exceed the threshold voltage (V T), ensuring that the parameter x is sufficiently large This model remains continuous across the entire spectrum of V GS values, offering accurate estimations for both subthreshold and above-threshold ranges Consequently, the EKV model is particularly useful for evaluating circuits that operate in moderate inversion.
4.2.2 Circuit Behavior Using Different Transistor Models
Two parameters are defined below for simplicity to analyze the circuit behavior using the three transistor models.
4.2.2.1 Low pass filter in subthreshold as designed
In this study, we employ the subthreshold model (4.18) to analyze the circuit depicted in Fig 4.5, focusing on transistors M1, M2, M3, and M4, which are operated within the subthreshold region The MITE currents through these transistors can be expressed individually, highlighting their respective contributions to the overall circuit performance.
(4.28)The exponential equations form a relationship among the four MITE currents as
(4.29) which gives an expression of current flowing in transistor M2
The derivative of the output current I out can be calculated from equation (4.28) as
The equation (4.31) can be used to calculate the derivative of V 2 as below since the sum of V 2 and V 3 yields a constant current I in equation (4.27). out out
We apply Kirchoff’s Current Law (KCL) at the capacitive node and obtain
By substituting the expression of V 2 in equation (4.32) and I 2 in equation (4.30) to equation (4.33), a first order differential equation of the output current is derived as out
The above equation (4.34) has a Laplace form of
The transfer function of the filter, as described in Equation (4.35), operates under the condition of all transistors functioning in weak inversion This configuration results in a first-order low-pass filter, which is integral to the adaptive system The gain of this low-pass filter is represented as -2.
K V e and the cut-off frequency is
2 2 Circuit behavior using simplified EKV model
In this analysis, we employ a simplified EKV model to assess the circuit depicted in Fig 4.5, focusing on the operation of transistors M1, M2, M3, and M4 in moderate inversion The MITE currents for these transistors are derived using equations (4.23) and (4.24), allowing for a clearer understanding of their behavior within the circuit.
The exponential equations form a relationship among the four MITE currents as
The derivative of the output current I out can be calculated from equation (4.39) as
K V out out out out out
The equation (4.42) can be used to calculate the derivative of V 2 as below since the sum of V 2 and V 3 yields a constant current I in equation (4.38).
We apply Kirchoff’s Current Law (KCL) at the capacitive node and obtain
Now we substitute the expression of V 2 in equation (4.43) and I 2 in equation (4.41) to equation (4.44).
I out out ref in g gain out out
A LOW POWER TEMPERATURE INSENSITIVE OSCILLATOR
Introduction and Previous Work
Smart dust refers to a network of miniature micro-electro-mechanical systems (MEMS) sensors capable of detecting various environmental factors such as light, temperature, and vibrations These sensors, comparable in size to a grain of sand or a dust particle, can form highly flexible, ultra-low power networks when grouped together Their potential applications are vast, including climate control systems and military uses for detecting enemy movements, poisonous gases, or radioactivity.
Modern radio frequency integrated circuits enable low power wireless communication networks, which prioritize efficient signal transmission and reception These devices must also be affordable, compact, and energy-efficient to ensure long battery life The Smart Dust research project is dedicated to designing low power RF transceiver systems that meet these essential criteria.
Transceiver systems are classified by their modulation schemes, with amplitude-shift-keying (ASK), on-off-keying (OOK), and frequency-shift-keying (FSK) being the most common OOK is a specific form of ASK that eliminates the carrier signal when transmitting a zero, making it a popular choice due to its simplicity and low implementation costs This method also enables the transmitter to conserve power by idling during the transmission of a zero.
The OOK transceiver system comprises a transmitter and a receiver block, each consisting of an RF part and a baseband part The baseband section operates at standard CMOS technology, eliminating the need for high-frequency operations In the transmitter, the baseband part compresses, encodes, and modulates signals before passing them to the RF part, which multiplies the signals with a high-frequency carrier, amplifies them, and transmits them via an antenna Conversely, the receiver block captures signals from the antenna, reduces noise, amplifies the received signals, and translates them to baseband frequency Finally, the baseband part demodulates, decodes, and decompresses the signals for further processing.
FSK modulation is recognized for its superior performance against interfering signals, although its implementation can be complex and costly To ensure precise frequency control, a phase locked loop (PLL) is commonly utilized in the process.
A phase locked loop (PLL) is a negative feedback control system that generates a signal maintaining a fixed relationship to a reference signal's phase It adjusts the frequency of a controlled oscillator to match the input signals in both frequency and phase PLLs are widely used in radio, telecommunications, and computing, serving functions such as generating stable frequencies, recovering signals from noisy channels, and distributing clock timing pulses in digital logic designs like microprocessors.
This section of the research focuses on two primary objectives: the development of oscillators for ultra-low power On-Off Keying (OOK) transmitter systems operating in the 2.2GHz frequency band, and the design of Phase-Locked Loops (PLLs) for Frequency Shift Keying (FSK) receiver systems The PLL design is a collaborative effort with Bo Li and targets both the 2.2GHz and 20GHz frequency bands.
5.1.2.1 Temperature insensitive oscillators for OOK transmitter systems
The objective of this project is to develop carrier frequency generation circuits for an ultra-low power On-Off Keying (OOK) transceiver system This involves creating a voltage-controlled oscillator that offers frequency tunability around 2.2 GHz Additionally, the circuit must maintain stable output frequency despite varying environmental conditions, including temperature and humidity fluctuations.
Crystal oscillators are renowned for their exceptional frequency stability, making them essential in devices that require a consistent frequency output, such as watches, clocks, radios, computers, and cell phones These oscillators utilize the mechanical resonance of a vibrating piezoelectric crystal, primarily quartz, to generate a precise electrical signal Quartz crystals are produced for a wide frequency range, from tens of kilohertz to tens of megahertz, with the resonant frequency influenced by factors like size, shape, elasticity, and material sound speed However, despite their reliability, quartz crystal oscillators have limitations in frequency range and tunability, rendering them unsuitable for applications like voltage-controlled oscillators (VCOs) operating around 2.2 GHz.
Currently, the commonly used LC tank oscillators consume power in milli-watts and large chip area due to the planar layout of the inductor in integrated circuit.
Recent advancements in voltage-controlled oscillators (VCOs) have shown significant improvements in power consumption and die area Andreani et al developed a low-power LC quadrature VCO that operates at 25mA from a 2V supply, occupying approximately 0.8mm² of die area Tiebout introduced a differentially tuned quadrature VCO with low phase noise, achieving a total power dissipation of 20mW at 2.5V, with a die area of around 1.1mm² Zanchi et al presented a 2V, 2.5GHz VCO featuring a wideband low noise automatic amplitude control loop, consuming only 7mA Tsang and EL-Gamal designed an efficient LC-based 12GHz VCO with a current consumption of 7.7mW and a compact die area of 0.24mm² Additionally, Hajimiri and Lee showcased a 1.8GHz LC oscillator that dissipates just 6mW using on-chip spiral inductors.
[34] presented an 800MHz low noise low power VCO with AAC consuming 1.6mA from a 2.7V power supply
A CMOS ring oscillator serves as a compact and energy-efficient alternative, exemplified by the 1GHz injection-locked design by Betancourt-Zamora et al., which operates at just 350μW and occupies a mere 0.012mm² of die area.
Recent advancements in CMOS voltage-controlled oscillators (VCOs) have led to significant improvements in power efficiency and speed A study revealed a low-power, high-speed CMOS VCO that consumes just 7.01mW while occupying a die area of 5231μm² Additionally, researchers Severino de Paula et al showcased a high swing, low power CMOS differential VCO with a compact chip area of 2520μm² and a power consumption of 11.38mW Furthermore, Yan and Luong introduced a 900-MHz CMOS low-phase-noise VCO that operates at a power dissipation of 15.4mW and occupies a minimal die area of approximately 0.013 mm².
Recent advancements in voltage-controlled oscillators (VCOs) include a low phase noise 2.0V 900MHz CMOS VCO that operates at 18.95mW and occupies 6750μm² of chip area Additionally, Park and Kim introduced a low-noise 900MHz VCO that draws 10mA from a 3V power supply and has a compact die area of just 0.01mm² While some earlier ring oscillator designs may consume power in the milliwatt range due to varying amplifier structures, they still achieve significant savings in chip area compared to traditional LC tank oscillators.
CMOS ring oscillators, while beneficial for their smaller size and lower power consumption, exhibit frequency variations due to the temperature sensitivity of CMOS transistors As illustrated in Fig 5.3, simulation results reveal that a three-stage current-starved ring oscillator operates at different frequencies across a temperature range of 0°C to 50°C This frequency instability limits the applicability of CMOS ring oscillators in precise channel-selected wireless communication.
Fig 5.3: The simulation result of a currents-starved ring oscillator at temperatures 0°C, 10°C, 20°C, 30°C, 40°C and 50°C.
We present a temperature-insensitive ring oscillator designed using CMOS technology, which significantly reduces power consumption compared to LC tank oscillators through an integrated temperature adaptive block Simulation results indicate that the circuit successfully oscillates at a target frequency of 2.2GHz across a temperature range of 0°C to 50°C Furthermore, experimental findings demonstrate a tenfold improvement in frequency stability from 5°C to 65°C with compensation, while consuming at least an order of magnitude less power than existing temperature-compensated voltage-controlled oscillators.
A Low Power Temperature Insensitive Oscillator Using CMOS Transistors
Fig 6.1: The schematic of the current-starved ring oscillator.
The current-starved ring oscillator, illustrated in Fig 6.1, consists of three inverting stages that facilitate oscillation generation In this configuration, transistors M4 and M5 function as inverters, while transistors M3 and M6 serve as current sources, regulating the current supplied to M4 and M5 The input control voltage, Vbias, determines the drain currents (ID) of transistors M1 and M2, which in turn influences the oscillation frequency of the voltage-controlled oscillator (VCO) To enhance power efficiency, the current ID is mirrored in a scale of 1:n across each inverting stage.
The inverting stage transistors are meticulously sized to achieve a switching point at half the power supply voltage, ensuring equal noise margins This design symmetry in the rising and falling edges enhances phase noise performance by reducing fluctuations.
1 f corner frequency [63] The W/Ls of transistors M1 and M2 are much smaller than those of other current source transistors, which limits the power dissipation
In an inverting stage, we consider the total capacitive load, denoted as Ctot, and the switching point, referred to as Vsp The duration required to charge Ctot from zero volts to the switching point voltage Vsp, using a constant current of nID, can be calculated accordingly.
While the time it takes to discharge Ctot from the power supply voltage Vdd to Vsp is given by
The oscillating frequency of the current-starved ring oscillator is
When the power supply voltage Vdd and the capacitive load Ctot are fixed, the oscillating frequency is proportional to the current flowing in each inverting stage
The output of a current-starved ring oscillator is typically buffered using an inverter However, connecting a large load capacitance to the oscillator's output can greatly impact the oscillation frequency and may even reduce the oscillator's gain to the point of stopping the oscillation entirely.
The average power dissipation is calculated based on the average current drawn from the power supply, Vdd For the three inverting stages, the total average current can be expressed as osc dd tot osc dd tot avg C V f.
So the total average power consumed by the current-staved ring oscillator is
P avg dd avg D tot dd osc 1
To optimize the design of a target oscillating frequency with a fixed power supply voltage (Vdd), it is essential to minimize gate capacitance, as this significantly reduces power consumption Additionally, employing smaller transistors for M1 and M2 further contributes to saving bias power.
The current-starved ring oscillator circuit is ideal for low power consumption and compact size, making it suitable for a 2.2GHz On-Off Keying (OOK) transmitter and a 2.2GHz Frequency Modulation (FM) receiver However, the oscillation frequency is constrained by the limitations of the fabrication process.
Fig 6.2: A simple 3-stage inverter-based ring oscillator in 0.13àm IBM 8RF LM process
To analyze the frequency limit of a circuit, we begin with a basic three-stage inverter-based ring oscillator, where each inverter introduces a delay time \( t \), resulting in a frequency of \( 1/(2kt) \) To achieve higher frequencies, it is essential to minimize delay and reduce the number of stages, with \( k=3 \) being the minimum for oscillation The design features PMOS and NMOS transistors with a channel length of 120nm and a PMOS width set to three times that of the NMOS for optimal signal symmetry The intrinsic switching speed of the MOSFET is influenced by the process characteristic time constant, with resistance inversely related to transistor width and capacitance directly proportional to it, maintaining a constant intrinsic speed However, the behavior of short-channel MOSFETs is more complex than the basic square law transfer function suggests Simulation results indicate that the oscillation frequency of the three-stage oscillator initially rises with increasing NMOS width \( w \) due to enhanced current availability for charge and discharge, but eventually declines as gate capacitance becomes the dominant factor.
Fig 6.3: Relationship between oscillation frequency and NMOS transistor width in a 3-stage inverter ring oscillator in 0.13àm IBM 8RF LM process.
The bias current (nID) in the current-starved ring oscillator is designed to reduce power consumption in the inverters while allowing frequency control through the voltage Vbias As illustrated in Fig 6.4, the oscillation frequency of the oscillator varies with changes in bias currents Specifically, Fig 6.4(a) shows the effect of varying the width of the NMOS transistors (e.g., M6), while Fig 6.4(b) demonstrates the impact of adjusting the voltage Vbias Initially, the oscillation frequency increases with rising bias current, peaking when the inverters are fully powered However, the bias current cannot infinitely increase the inverter's power, thus limiting the oscillation frequency to under 4GHz due to the constraints of the basic inverter ring structure By adjusting the transistor sizes or employing multi-finger transistors, the frequency can potentially reach around 7GHz; however, this design is not suitable for ultra-high frequency applications such as a 20GHz FM receiver.
Fig 6.4: The oscillation frequency of the current-starved ring oscillator with the change of bias current.
In Chapter 5, we mentioned an equation about temperature dependence of gate voltage of a saturated NMOS transistor:
V 1 (5.2) where V GSF ,I DSF is the common intercept point for transfer functions of the transistor at different measured temperatures VT is the threshold voltage temperature coefficient
In a designed circuit with a fixed current mirror ratio n, capacitive load Ctot, and power supply voltage Vdd, it is essential to maintain a consistent drain current I D for transistors M1 and M2 despite temperature variations to achieve a stable oscillating frequency, as outlined in Equation (6.3) The parameters V GSF, I GSF, α VT, and I D of transistor M2 ensure that the gate voltage V bias varies linearly with temperature T, facilitating the maintenance of a target frequency Simulation results corroborate this relationship, as demonstrated in Fig 6.5, which illustrates the necessary gate voltages V bias for generating a 2.2GHz oscillation across different temperatures.
Fig 6.5: The required gate voltages V bias to generate a 2.2GHz oscillation at temperatures 0°C, 10°C, 20°C, 30°C, 40°C and 50°C.
The temperature sensor developed in Chapter 5 produces an output voltage that is directly proportional to temperature By utilizing this output voltage, we can create the necessary gate voltage (V bias) through the construction of a temperature-independent linear gain block, as illustrated in Fig 6.6.
Fig 6.6: The temperature adaptive block consisting of a temperature sensor and a temperature independent linear gain circuit
Transistors M1 and M2 operate in saturation region Ignore the channel modulation, the current flowing in transistor M1 is
I (6.6) and the drain current of transistor M2 is
The Kirchhoff’s current law tells us these two currents IM1 and IM2 are equal, which gives thn temp thp bias dd p p p n n n
Recall that in the model we used to derive Equation (5.2), we assume the mobility of carriers as:
Substitute Equation (6.9) to Equation (6.8), we obtain a positive constant on the left side Assume the positive constant is x, then thp dd thn temp bias xV xV V V
Assume the transfer function of the temperature sensor is aT b
V temp (6.11) where a and b are positive constants Also recall the thermal effect on threshold voltage we used in the model is
Substitute Equations (6.11) and (6.12) to Equation (6.10), we obtain
The voltage Vbias can be expressed as a linear function of temperature T, where the slope can be adjusted through tuning Additionally, the intercept of this expression can be modified by altering the N-well potential Vb, utilizing the body effect on the threshold voltage.
In radio frequency testing, the most widely-used probe has an impedance of 50Ω.
To optimize power transfer and reduce reflections from the probe, it is essential to match the output impedance to that of the probe, necessitating an output buffer with a 50Ω impedance This is achieved using a source follower circuit combined with a suitable resistor, as illustrated in Fig 6.7 An inverter serves as a buffer to mitigate the effects of a large capacitive load The power dissipation of the output buffer correlates with the power delivered to the subsequent stage; for an output power of -13dBm, the simulated power consumption is approximately 1.7mW.
Fig 6.7: The output buffer for impedance matching.
Figures 6.8 and 6.9 illustrate the DC temperature sweep, with Figure 6.8 depicting the output voltage (V_temp) of the temperature sensor in relation to temperature (T), and Figure 6.9 showing the output voltage (V_bias) of the temperature adaptive block against temperature (T) Both output voltages demonstrate strong linearity with temperature changes When comparing Figure 6.9 to Figure 6.5, it is evident that V_bias has been effectively calibrated to meet the temperature insensitivity criteria.
Fig 6.8: Temperature sensor output voltage V temp with respect of temperature T.
Fig 6.9: temperature adaptive block output voltage Vbias with respect of temperature T.
The output voltage spectrum (Vout) is displayed in Fig 6.10 at various temperatures: 0°C, 10°C, 20°C, 30°C, 40°C, and 50°C The circuit maintains a steady target frequency of 2.2GHz, facilitated by the temperature adaptive block The current-starved oscillator, paired with a load inverter, consumes approximately 300μW of power, while the temperature adaptive block dissipates 32μW.
Low Power Phase Locked Loop Based FM Receivers
7.1 A Low Power 2.2GHz Phase Locked Loop used for FM Receiver
The FM receiver structure utilizing phase locked loops (PLL) is depicted in Fig 5.4, highlighting the initial low noise amplifier (LNA) stage along with the PLL and output amplifier for 2.2GHz wireless communication Additionally, Fig 7.1 presents the block diagram of the PLL and output amplifier, illustrating their integration in the receiver system.
Fig 7.1: The block diagram of the PLL and output amplifier
A Phase-Locked Loop (PLL) consists of three main components: a mixer, a low pass filter, and a voltage-controlled oscillator (VCO) The mixer and low pass filter function together as a phase detector, converting the phase difference between the input signal and the feedback signal into a voltage signal (V) When the PLL is locked, the feedback signal frequency (ω_fb) aligns with the input signal frequency (ω_in), ensuring accurate signal tracking.
The voltage difference V_pd is directly proportional to the frequency of the feedback signal ω_fb, allowing it to carry frequency information from the input signal ω_in This information is subsequently amplified to produce the output voltage V_out This section details the circuit design for each block illustrated in Fig 7.1, developed in collaboration with Bo Li from the University of Maryland.
The phase detector, designed in collaboration with my colleague Bo Li, features a single branch mixer and a low pass filter The mixer operates by multiplying the two input signals, V in and VCO out, to extract phase difference information To enhance the signal quality, the low pass filter effectively reduces high-frequency noise from the phase difference output The circuit schematic of the phase detector is illustrated in Fig 7.2.
Fig 7.2: The schematic of the phase detector used in 2.2GHz low power PLL
The mixer consists of three transistors operating within a single current branch from Vdd The RF input signal from the LNA, coupled with AC, is supplied to the two inputs, V in 1 and V in 2, along with the output from the VCO Based on Kirchhoff’s current law, the currents through transistors M1 and M2 are identical Assuming both transistors M1 and M2 are in the saturation region and neglecting the channel length modulation of M2, the current can be defined accordingly.
is the electron mobility and C ox is the gate oxide capacitance
W are width to length ratio of the transistor M1 and M2 V T is the threshold voltage of theNMOS transistor is the channel length modulation parameter.
Substitute equation (7.2) to equation (7.1), the current across transistor M1 is rewritten as
In equation (7.3), the electron mobility , the gate oxide capacitance C ox , the width to length ratios
W , threshold voltage V T and the channel length modulation parameter can be taken as constants With proper low pass filtering, only the low frequency term 1 1 2
The implementation of multiplying the two inputs, V in 1 and V in 2, is facilitated by the resistor R2 located at the top of the current branch This configuration converts the current I, as described in equation (7.3), into the corresponding output voltage.
The cascode transistor M3, along with the low pass filter formed by resistor R3 and capacitor C2, enhances the amplification of low frequency signals while attenuating high frequency harmonics The small signal equivalent circuit for transistor M3 is depicted in Fig 7.3, where R_in represents the output resistance observed from the source of transistor M3 towards transistor M2, and r_o denotes the channel length modulation resistance of transistor M3 This analysis was conducted in collaboration with colleague Bo Li.
Fig 7.3: Small signal equivalent circuit of transistor M3 in the schematic of the phase detector
Transistor M3 here serves as a common gate amplifier The load at the drain of the transistor is defined as
The small signal voltage gain defined as
For low frequency harmonics, resistance dominates at the load so that
Since g m r 0 1, the small signal voltage gain can be approximated as low R
For high frequency harmonics, capacitance dominates at the load so that
C t is the total capacitance at the drain of transistor M3 The small signal voltage gain can be rewritten as
t in m t in t in gs high m
The common gate amplifier using transistor M3 is engineered to achieve significant gain at low frequencies while minimizing gain at high frequencies, as indicated by equations (7.7) and (7.9) This design allows transistor M3 to effectively amplify low-frequency signals while simultaneously filtering out high-frequency noise prior to the low pass filter.
The single branch phase detector is notable for its low power consumption, as it draws only one current from the power supply (Vdd) to perform mixing, amplification, and filtering functions It utilizes a small transistor to handle both input signals, effectively managing large resistive and small capacitive loads Additionally, the input signal from the low-noise amplifier (LNA) to the phase detector employs an AC coupling structure, with the bias voltage (V ctrl) regulating its operation.
The phase detector generates a DC current that adjusts its output voltage, which is then input into the Voltage-Controlled Oscillator (VCO) to modify the Phase-Locked Loop (PLL) free-running frequency By tuning the bias voltage (V_ctrl), the RF input signal's frequency can be shifted between different channels The performance of the phase detector is primarily influenced by the power supply voltage (V_dd) and the bias voltage (V_ctrl) This research was conducted in collaboration with Bo Li from the University of Maryland and is currently under review for publication.
The starved CMOS ring oscillator is favored in low power PLL designs due to its micro-watt power consumption, compact size, and simplicity Its large output swing facilitates easier locking and a wider lock-in frequency range for the phase detector In contrast, most on-chip inductors at 2.2GHz have a quality factor below 20, leading to higher milli-watt power consumption and larger chip areas in LC oscillators Additionally, ring oscillator-based VCOs can operate over a broader frequency range compared to their LC counterparts This work aims to achieve extremely low power consumption while maintaining acceptable phase noise for PLL applications.
Fig 7.4: The schematic of the current starved ring oscillator
The current starved ring oscillator, depicted in Fig 7.4, serves as an insensitive voltage-controlled oscillator (VCO) with a distinct voltage-to-frequency relationship By adjusting the transistor parameters, we achieve a VCO oscillation frequency of 2.2GHz at an input voltage of approximately 0.6V, which is half of the Vdd It is crucial to consider the voltage-to-frequency relationship alongside the phase detector design, as the output DC voltage from the phase detector is linked to the VCO's free-running frequency.
The output amplifier design, illustrated in Fig 7.5, features a two-stage amplifier configuration that utilizes a common-source differential pair followed by a common-source amplifier To enhance bandwidth, cascode transistors are incorporated in both gain stages This output amplifier achieves a gain of 50 at a frequency of 16MHz while maintaining a low power consumption of just 139 µW.
Fig 7.5: The schematic of the output amplifier
All the circuits of the phase detector, current starved ring oscillator and the output amplifier are simulated using Cadence RFDE simulator with the IBM 0.13àm 8RF
In our simulation of the phase detector, we utilized two input signals with different frequencies but the same phase: a -35dBm RF signal at 2.2GHz and a rectangular wave at 2.195GHz oscillating between 0 and 1.2V This setup effectively tested the circuit's multiplying and low pass filtering capabilities The output harmonics, detailed in Table 7.1 and illustrated in Fig 7.2, revealed that the most significant harmonic, aside from the DC component of 0.605, was 0.011 at 5MHz, representing the frequency difference between the two input signals Additionally, a second harmonic was observed at 2.2GHz with an amplitude of 7.739e-5, which is less than 1% of the amplitude at 5MHz Overall, the circuit successfully calculated the frequency difference while effectively dampening other frequency harmonics.
The phase detector is tested using two input signals at a frequency of 2.2GHz with varying phases A -35dBm RF input and a pulse oscillating from 0 to 1.2V are introduced to the circuit The results, illustrated in Fig 7.6, demonstrate a correlation between the phase detector's voltage output and the input RF signal's variable phase, ranging from 0.254 to 3.364 radians As the phase difference changes, the output voltage varies from a maximum of 0.604V to a minimum of 0.568V, indicating that the output is a sinusoidal function of the phase difference Notably, the voltage output is monotonic within half cycles, allowing for consistent conversion of the phase difference into these monotonic half cycles Consequently, the voltage output effectively indicates the phase difference detected by the phase detector circuit.