Adaptive Data Analysis and Processing Technology (ADAPT) for Spacecraft Carl S Mills*, Kim R Fowler, M Ann Garrison-Darrin, Harry A C Eaton, *NASA - Langley Research Center Johns Hopkins University - Applied Physics Laboratory Many NASA Earth Science Enterprise (ESE) science themes have identified instrument options and associated system requirements that require on-board satellite data processing and intelligent sensor control to reduce system development and operations cost while returning improved data and associated geophysical parameters required for future science needs Adaptive computing technology applied to flight instruments and systems can enable future missions by providing efficient development of on board processing and control systems that are reconfigurable in flight This reconfigurable processing technology provides the flexibility of a general-purpose processor running software with the performance of a dedicated hardware processor The Adaptive Data Analysis and Processing Technology (ADAPT) project is a collaborative effort between NASA Langley Research Center (LaRC) and the Johns Hopkins University Applied Physics Laboratory (JHU/APL) to develop a prototype reconfigurable processor utilizing stateof-the-art field programmable gate array (FPGA) technology The architecture of the ADAPT prototype (figure below) was designed so that it could be used either in a Compact PCI (CPCI) backplane or in standalone mode A Xilinx Virtex-II 2V1000 device is used as the reconfigurable processing element Multiple I/O pins from the Virtex-II are available through a high-density micro-coax connector at the front of the 3U CPCI card as well as several additional pins on the J2 connector of the CPCI interface 128K x 32 bits of external SRAM is available to the Virtex-II device for data storage A direct data path from the Virtex-II to the CPCI bus is available for communication with a host processor Since the configuration memory for the Virtex-II FPGA is based on SRAM, and in the space environment SRAM is susceptible to Single Event Upsets (SEUs), a method to mitigate the risk associated with SEUs was developed The SEU mitigation strategy is implemented in the Supervisor FPGA, an antifuse based device An additional anti-fuse based FPGA implements the 32-bit CPCI interface Due to its general-purpose design, the ADAPT hardware enables a capability for on-board processing that is applicable to a broad set of high data rate applications For demonstration purposes, the project developed algorithms and configuration programs for the ADAPT hardware that enabled it to meet the processing requirements of two of ESE’s high priority instrument options: microwave radiometers for soil moisture measurements and Fourier Transform Spectrometers (FTS) for atmospheric composition measurements Instrument Interface, 192-pin connector 128Kx32 SRAM Xilinx Virtex-II Million-gate FPGA FLASH Memory Holds multiple Xilinx FPGA configurations CompactPCI J2 Connector provides additional I/O capability CompactPCI J1 Connector for Host interface Supervisor FPGA (Actel A54SX32) performs continuous Xilinx configuration checking Host FPGA (Actel A54SX32) implements 32-bit CompactPCI interface POC: Carl S Mills Electronic Systems Branch, Systems Engineering Competency NASA Langley Research Center (LaRC) Mail Stop 488 Hampton, VA 23681 Tel.: (757) 864-1672 Fax: (757) 864-7944 Email: c.s.mills@larc.nasa.gov Kim R Fowler 11100 Johns Hopkins Road, Room 13-S108 Laurel, MD 20723-6099 Tel.: (240) 228-8215 Fax: (240) 228-7061 Email: kim.fowler@jhuapl.edu ... Connector provides additional I/O capability CompactPCI J1 Connector for Host interface Supervisor FPGA (Actel A54SX32) performs continuous Xilinx configuration checking Host FPGA (Actel A54SX32)