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Luận văn tốt nghiệp thạc sĩ GVHD: PGS TS hoàng trang

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  • Luận văn tốt nghiệp thạc sĩ                                                       GVHD: PGS TS hoàng trang

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I H C QU C GIA TP HCM I H C BÁCH KHOA -o0o - HÀ NAM ANH THI T K B THU D LI U V I 7.2 GBPS TRÊN CÔNG NGH 18nm FinFET A 7.2 GBPS RECEIVER DESIGN IN PHY SIMULATED WITH ALL PVTS IN 18nm FinFET Chuyên ngành: K thu nt Mã s : 8520203 LU TP H CHÍ MINH, tháng 01 2022 Lu t nghi p Th GVHD: PGS.TS Hồng Trang C HỒN THÀNH T I: I H C BÁCH KHOA Cán b -HCM ng d n khoa h c : PGS.TS Hoàng Trang Cán b ch m nh n xét : TS Hu nh Phú Mi ng Cán b ch m nh n xét : TS Nguy Lu c b o v t i Tr ng ng i h c Bách Khoa, HQG Tp HCM 2022 Thành ph n H i ng nh giá lu n v n th c s g m: Ch t ch: TS Tr n Hoàng Linh : TS Nguy ng Ph n bi n 1: TS Nguy Ph n bi n 2: TS Hu ng y viên: TS Bùi Tr ng Tú Xác nh n c a Ch t ch H i ng ngành sau lu n v n ã c s a ch a (n u có) CH T CH H NG h giá LV ng Khoa qu n lý chuyên NG KHOA NT PGS.TS Hoàng Trang i Lu t nghi p Th GVHD: PGS.TS Hoàng Trang I H C QU C GIA TP.HCM I H C BÁCH KHOA C NG HÒA XÃ H I CH T NAM c l p - T - H nh phúc NHI M V LU C H tên h c viên: Hà Nam Anh MSHV: 1970424 09/09/1997 Chuyên ngành: K thu I n t Mã s : 8520203 TÀI: THI T K B THU D LI U V I 7.2 GBPS TRÊN CÔNG NGH 18nm FinFET (A 7.2 GBPS RECEIVER DESIGN IN PHY SIMULATED WITH ALL PVTS IN 18nm FinFET) II NHI M V VÀ N I DUNG: Th c hi n thi t k b thu v i t 7.2 Gbps 18nm FinFET PDK mô ph ng Cadence tools III NGÀY GIAO NHI M V : 22/02/2021 IV NGÀY HOÀN THÀNH NHI M V : 05/12/2021 V CÁN B NG D N: PGS.TS Hoàng Trang Tp HCM, ngày 15 tháng CÁN B NG D N CH NHI M B O PGS.TS Hoàng Trang NG KHOA N- NT ii Lu t nghi p Th GVHD: PGS.TS Hoàng Trang L IC L u tiên em g i l i c n th y PGS.TS ng d em hoàn thi m ch SAVARTI , h tr em v v t ch t s d ng tools t s n tình giúp t k vi Trong trình th c hi n lu t nghi p, nh n th g ng h t g ki n th c v n h n h p nên v n cịn nhi u thi u sót, mong th y (cơ) góp ct c th c hi n mơ ph is ng d n c a th y cô b môn nt ih c vi t b i tay em_ Hà Nam Anh_H c viên sau i h c i h c Bách Khoa không chép t vi t cá nhân hay t ch c khác M t l n n a, em xin chân thành c First of all, I would like to thank Assoc.Prof.Dr Hoang Trang who have wholeheartedly guided me to complete this thesis I would also like to thank the SAVARTI IC design company for helping and supporting me in terms of facilities In the process of completing my graduation thesis, I realized that I have tried my best Due to my limited knowledge, there are still many shortcomings Therefore, your suggestions will make my thesis better The thesis was simulated under the guidance of the teachers of electronics at the University of Technology and the SAVARTI company Beside that, the report has been written by me and has not received any previous academic credit at this or any other institution Sincerely! Tp H Chí Minh, ngày 15 tháng 2022 H c viên Hà Nam Anh iii Lu t nghi p Th GVHD: PGS.TS Hồng Trang TĨM T T LU Trong nh u c a công ngh s n xu n t , h n ch v thi t b bán d n, thi t k m ch CMOS nhi u ng d ng có th m t thách th c T p tích h p nhi n thi t k chip nh ng y u t th thách Nhi u gi có th m t s c thu nh ch n rò t t c v m này, k u th h công ngh CMOS m i v i hi u t tr i [1] - Transistor hi u Không gi c nhu c u c a y u t c Transistors thu nh l i làm cho CMOS v n tiêu th su uc a c Transistors Th r thi t b CMOS s gi i quy cao, ng Fin (FinFET) u trúc ph ng c c g i Transistors ng, m r ng theo chi u th ba C u trúc m i c bao b c xung quanh b i l p n môi, h n ch hi u ng kênh d n dòng rò r th t ng c a FinFET r t gi ng v gi i pháp t t nh thi t b ng Vì v y, cơng ngh Fin- t c coi rị r Transistors kênh ng n thay th c p trên, ng d ng c a công ngh FinFET ngày i 22nm [2] V i nhi tr nên ph bi c tích h p nhi th p bao g m liên k d ng v i t u thi t k t u t d li u cao hàng ng thi t b cao công su t cao (HSIO) HSIO h tr cho nhi u ng n tho i thông minh, thi t b c k t n i di u cu i khác Internet of Things (IoT) M c thi t k t n r t nhi u thách th c M t nh ng thách th c l n HSIO l p v t lý (PHY) - trung tâm c a b t k gi i pháp k t n i [3-4] Thi t k PHY có th lo i b nhi u n hình gi m hi ng g p k t n i liên k t gi a máy phát máy thu MIPI D-PHY m t ví d n hình c c phát hành b i MIPI h tr Camera Serial Interface (CSI-2) Display Serial Interface (DSI) v i kênh d n ng n d n dài [5-9] Do suy hao th p 1.1 ch h tr t b t n s th p [10], MIPI D-PHY phiên b n 1.0 phiên b n d li thi t k ng K t phiên m k thu t MIPI D-PHY h tr t n 4,5 Gbps / v i s tr giúp c a k thu t thi t k cân b ng hi u ch p cho s m t mát n kênh l ch kênh d n suy hao m t v d li u lên l làm iv Lu t nghi p Th gi m ch GVHD: PGS.TS Hoàng Trang ng tín hi u b gây b i Skin effects, Attenuation, Dispersion and Reflections dây d n PCB [11-12] thi t k khôi ph c d li u c n thi Có nhi u cách ti p c khôi ph c d li u M t s Time Linear Equalization (CTLE) cung c l i bi n d ng kênh d n [13] N c bi t bù l i s m t mát d ng Continuous t ns ch ng l i s suy hao l ic , corner SS (ch m - ch m) [14-16] Lý cho v ki n ng v c CMOS l n áp cao (VDDIO Typical m t ki n trúc m i v i th ng cao ngu n cung c p kh c ph c v c CMOS nh vi c s d ng này, Lu xu t ng th p ngu n cung c n áp Typical) ct cao nh t thi t k , Lu 7.2 Gbps/làn ng l i hi u qu xu t s d ng b thu d a b chuy sang k thu t s (ADC-based Receiver) - cho phép x lý tín hi u k thu t s ph c t p, linh ho ib x cân b ng tín hi u có th d dàng h tr u ch nâng cao [17] Lu c xây d ng t ch ph n I, nguyên lý thi t k c trình bày c trình bày ph n II k t qu mô ph ng Receiver ADC V, cu i cùng, ph n k t lu n Ph n gi i thi c trình bày l t ph n IV c trình bày trong ph n VI v Lu t nghi p Th GVHD: PGS.TS Hoàng Trang ABSTRACT In the early days, due to the restriction on the semi-conductor devices, the CMOS circuit design in many applications could be a challenge High-speed, low power, and more integrated on-chip design are the top priority factors of this challenge Many solutions have been proposed to be able to meet the demands of these factors and one of them is scaling down the transistor size Unfortunately, the leakage current in the CMOS devices will increase while the transistor size is scaling down and the CMOS still, therefore, consumes power in the shutmode operation even with process nodes below 5nm To solve this drawback, a new generation of CMOS technology with superior performance [1] - Fin Field Effect Transistor (FinFET), has been researched Unlike the planar structure of MOSFET, FinFET, also known as multi-gate MOS transistors, extends in a third dimension The wrapped-around gate structure provides a less channel-length modulation and lowers subthreshold leakage Besides, the working principle of a FinFET is very similar to a conventional MOSFET Thus, Fin-FET technology is considered to be the best solution to optimize the leakage in short channel transistors and is gradually replacing the CMOS devices below 22nm [2] With many advantages as mentioned above, the appli-cations of FinFET technology are becoming widespread and more integrated with much high-speed and low power design including the high-speed input/output (HSIO) links The HSIO supports many applications with multiple Gbps data rates such as smartphones, mobile-connected devices, and other endpoints on the Internet of Things (IoT) Although it has been designed for a long time, it still has a lot of challenges One of the major challenges in HSIO is the physical layer (PHY) - the heart of any interconnection solution [3-4] The PHY design could cancel typical noise impairments and reduce other non-idealities usually encountered on a transmitter-to-receiver interconnect The MIPI D-PHY is a typical example of PHY released by the mobile industry processor interface (MIPI), to support the Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols with the short channel, the standard channel and the long channel [6-9] Due to low attenuation at low frequency [10], the MIPI D-PHY specification in version 1.0 and version 1.1 only supports data rates up to Gbps/lane and 1.5 Gbps/lane, respectively Since version 1.2, to speed up the chip design, the MIPI D-PHY specification supports data rates up to 4.5 Gbps/lane with the help of the design techniques of equalization and skew calibration to compensate for channel insertion loss and skew among channels Thus, the loss of channel is a significant issue reducing signal quality caused by skin effects, attenuation, dispersion, and reflections on PCB traces [11-12] and the data recovery design is necessary to compensate for the channel loss There are many approaches to data recovery One of them is using the Continuous Time Linear Equalization (CTLE) provided the peaking gain at Nyquist frequency to counter the channel loss and distortion [13] But the bandwidth and the gain of the conventional CTLE are not enough, especially at SS (slow - slow) corner [14] The main reason for this problem would be the use of the conventional architecture with a large CMOS size, high threshold voltage, and high voltage ome this problem, this paper proposed a novel architecture with folded cascode CTLE based on the core devices vi Lu t nghi p Th GVHD: PGS.TS Hoàng Trang where the devices have a small CMOS size, low threshold voltage, and low voltage supply -speed In addition, in order to achieve above 7.2 Gbps/lane as well as bring the highest efficiency in design, the Thesis proposed to use a receiver based on an analog to digital converter (ADC based Receiver) - enables complex digital signal processing and more flexible with DSP processors for signal equalization, and can easily support advanced modulation schemes [17] The rest of the paper is organized as follows The introduction is shown in section I, the design principles of Receiver and ADC are shown in section II and III, respectively Accordingly, the simulation results of Receiver and ADC are shown in sections IV and V, respectively Finally, the conclusion is shown in section VI vii Lu t nghi p Th GVHD: PGS.TS Hoàng Trang L I ih c khác c th c hi n c vi t b i tay em_ Hà Nam Anh_H c viên sau i h c Bách Khoa không chép t vi t cá nhân hay t ch c c th c hi n mô ph is ng d n c a th y cô b môn i h c Bách Khoa công ty SAVARTI nt Các tài li u tham kh nt c trích d nh c a b n M t l n n a, em xin chân thành c The thesis has been written by me and has not received any previous academic credit at this or any other institution The thesis was simulated under the guidance of the teachers of electronics at the University of Technology and the SAVARTI company The references have been clearly cited in accordance with the regulations of the Department of Electronics Technology Sincerely! Tp H Chí Minh, ngày 15 2022 H c viên Hà Nam Anh viii Lu t nghi p Th GVHD: PGS.TS Hoàng Trang M CL C I GI I THI U 1.T ng quan v CMOS 1.1 L ch s phát tri n CMOS 1.2 Nguyên lý ho 1.3 Quy trình s n xu T ng n c a MOSFET n c a MOSFET n FinFET T ng quan v PHY 3.1 c v PHY 3.2 T ng quan v Receiver 10 3.3 T ng quan v ADC-based Receiver 11 3.4 Nguyên lý v Receiver 12 3.5 M t s thông s khác c a Recceiver 13 3.5.1 Pseudorandom binary sequence 13 3.5.2 Các thông s c a CTLE 13 3.5.3 Các thông s EYE Diagram 14 3.6 T ng quan v ADC 15 3.6.1 Gi i thi u v ADC 15 3.6.2 Phân lo i ADC 16 3.6.3 Các thông s ADC 18 II NGUYÊN LÝ THI T K RECEIVER 23 Input signal 24 Termination block (HSRX_Term) 25 Protect block (HSRX_diffbuff) 26 Continuous time linear equalization block (HSRX_CTLE) 27 Gain buffer block (HSRX_singbuff) 30 ix Lu t nghi p Th M GVHD: PGS.TS Hồng Trang t k có t it th c t c a MIPI ver 2.1 ng dây truy i gi ng so v i MIPI specs r ng c jitter Thi t k i sai s ngõ ph c 19.63ps t i corner t nh K t lu n: Toàn b h th l c n ngõ t i 14% c a UI c 14% jitter/UI Con s i giá tr c a MIPI spec b i h th ng ch th c hi n is c 13.88ps n giá tr ngõ c h tr b i nh ng kh i l 62 Lu t nghi p Th GVHD: PGS.TS Hồng Trang V THI T K VÀ MƠ PH NG SAR_ADC Thi t k mô ph u d a Cadence tool version 6.1.3 c th c hi n TSMC 180nm Comparator l a t ng ti n khu i Hình 5.1 K t qu mô ph ng preamplifier ct Av V l i c a m ch s gi m xu ng K t qu mô ph ng: 22,19dB; BW 310, 4Mhz, UBW 7,863Ghz l i 22,19dB s không th c B ng vi c m c cascade t ng ta có: Hình 5.2 K t qu mô ph ng preamplifier m c cascade 63 Lu t nghi p Th GVHD: PGS.TS Hoàng Trang K t qu mô ph n Av 111dB; BW 98,51Mhz, UBW 6,873Ghz K t qu t so v i tính tốn Hình 5.3 Mơ ph ng tran v Nh n th y b so sánh b delay 19ns B 100uV, 32Mhz ub tk so sánh u t chu kì ti p theo b so sánh ho Output signal Output signal c mô ph ng d a AC Signal Ramp Signal Tín hi u AC Signal có t n s 48177.083333Hz, DC Voltage 0.9V, AC Voltage 0,675V Tín hi u Ramp có time 384us ng v i 1024 mã code 64 Lu t nghi p Th GVHD: PGS.TS Hồng Trang Hình 5.4 Output signal with high frequency AC Signal Hình 5.5 Output signal with high frequency AC Signal 65 Lu t nghi p Th GVHD: PGS.TS Hồng Trang Hình 5.6 Output signal with Ramp Signal Hình 5.7 Output signal with Ramp Signal 66 Lu t nghi p Th GVHD: PGS.TS Hoàng Trang FFT plot of the output m c ta th c hi n l y m u 2048 l n qua công th c: Fin M * Fs N 32 10 12 2048 37 578125 12 48177, 0833Hz th c hi n FFT, M s nguyên t th c hi n s l n c a d u vào Fin, Fs t n s l y m u, N s m FFT c n l y m u Hình 5.8 FFT Plot v m Signal to noise vs Signal to noise and distortion ratio (SNR vs SNDR) Export thông s t c SNR=59.48dB; SNDR=59.4dB D Spurious free dynamic range (SFDR) c SFDR=76dB 67 Lu t nghi p Th ENOB GVHD: PGS.TS Hoàng Trang Effective number of bits (ENOB) SNDR 1.76 6.02 59.4 1.76 6.02 9.59 Bits Differential nonlinearity (DNL): Hình 5.9 DNL Integral Nonlinearity (INL) Hình 5.10 INL 68 Lu t nghi p Th GVHD: PGS.TS Hồng Trang Cơng su t tiêu tán Th c hi n mơ ph c: Hình 5.11 Giá tr t c th i c a dòng di n v i ngu n 1.8V Giá tr itt n t c th i: 2,89366mA Giá tr ptt u.itt 1,8 2,89366 n trung bình: Hình 5.12 Giá tr n theo th i gian v i ngu n 1.8V S d ng cơng c Tools v tính giá tr I 5, 21mW n, hàm i c: 648,948uA 69 Lu t nghi p Th GVHD: PGS.TS Hồng Trang Hình 5.13 Hàm tính giá tr n v i ngu n 1.8V Power U I 1,8.648,948 1,17mW Giá tr FOM Power 2ENOB fs 10 u su t SAR ADC: 1,17.10 29,59.2.106 759 fJ / conv So sánh k t qu v i m t s báo khác B ng 13 So sánh k t qu ADC v i m t s báo khác 70 Lu t nghi p Th GVHD: PGS.TS Hoàng Trang VI K T LU N NG PHÁT TRI N Hi n t t k chip ch y t v it 4.5 Gbps yêu c u 10% jitter theo UI (t c kho ng 22.22 ps jitter) cho toàn b h th ng [5] Lu c hi c thi t k b câng b ng tín hi u v i: 7.2Gbps it cao nh t c a MIPI) 6.1mW công su t tiêu tán 19.63ps jitter t i worst case corner SS (14% c a UI v i t n s 3.6Ghz) Thi t k xu c 4.26GHz peaking frequency 16.91 dB peaking gain Các k t qu ch n ngõ c a CTLE is c h tr b i nh ng block cịn l Ngồi ra, lu c hi n thi t k m t ADC cơng su t th có th s d h tr CTLE: phân gi i 2MS/s t l ym u 1.17mW công su t tiêu tán DNL, INL th p (nh Bài c xu t b n t i h i ngh ATC 2021: A study of 10-bit 2-MS/s Successive Approximation Register ADC with low power in 180nm technology 2021 International Conference on Advanced Technologies for Communications (ATC), Ho Chi Minh City, Vietnam, 2021 Bên c tài v c ti p t i CTLE ADC nói n m t s thi t k c tiêu s hoàn thi n m t Receiver hoàn ch nh 71 Lu t nghi p Th GVHD: PGS.TS Hoàng Trang DANH M C CÁC CƠNG TRÌNH KHOA H C N A Ha, and T Hoang -bit 2-MS/s Successive Approximation Register ADC with low power in 180nm technology 2021 International Conference on Advanced Technologies for Communications (ATC), Ho Chi Minh City, Vietnam, 2021 72 Lu t nghi p Th GVHD: PGS.TS Hoàng Trang TÀI LI U THAM KH O [1] W P Maszara, and M Challenges - Technology and Circuit Design 2013 Proceedings of the ESSCIRC (ESSCIRC), Bucharest, Romania, 2013, pp 3-8 [2] S Verma, S L Tripathi, and M nFET device Using Qualitative Approach for Low-Power applications 2019 Devices for Integrated Circuit (DevIC), Kalyani, India, 2019, pp 84-88 [3] F E Rangel-Patiño, J E Rayas-Sánchez, A Viveros-Wacher, E A Vega-Ochoa1, and N, -Speed Links Receiver Optimization in Post-Silicon Validation Exploiting Broyden-based Input Space Mapping Conference on Numerical Electromagnetic 2018 IEEE MTT-S International and Multiphysics Modeling and Optimization (NEMO), Reykjavik, Iceland, 2018 [4] F E Rangel-Patiño, J E Rayas-Sánchez, and N Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation 2018 IEEE International Test Conference (ITC), Phoenix, AZ, USA, 2018, pp 1-10 [5] MIPI Alliance Specification for D-PHY, version 2.1, Dec 2016 [6] P Lee, and Y -PHY Transceiver Bridge Chip With Level-Dependent Equalization IEEE Transactions on Circuits and Systems II: Express Briefs, 2017, pp 1-5, DOI: 10.1109/TCSII.2019.2962839 [7] T Kim, J Hwang, S Lee, S Chun, S Ryu, S Lee, H Cho, W Tak, Y Kim, H Lee, H Pae, H Lim, and J -Gb/s dual-mode receiver with MIPI D-PHY and C- PHY interfaces for mobile display drivers Journal of the Society for Information Display, pp 1-13, 2020, DOI:10.1002/jsid.916 [8] P Lee, and Y -Gbps Receiver Bridge Chip with Auto-skew Calibration for MIPI D-PHY Interface IEEE Transactions on Consumer Electronics, 2019, pp 484- 492, DOI: 10.1109/TCE.2019.2942503 [9] P Lee, H Lee, Y Kim, H Hong, and Y -Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2 Transactions on Consumer Electronics, 2017, pp IEEE 209-215, DOI: 10.1109/TCE.2017.014908 73 Lu t nghi p Th GVHD: PGS.TS Hoàng Trang [10] E -J Kim, H -Y Park, C K Ahn, S -I Lim, and S physical l IEEE Trans Consum Electron., vol 56, no 3, pp 1196 1203, Aug 2010 [11] Y Choi and Y -Gb/s Receiver with a Continuous-Time Linear Equalizer and 1-Tap Decision-Feedback Equalizer 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, CO, USA, 2015 [12] S Wu, Q Wang, N Ning, and J -speed MIPI Receiver Bandwidth Expanding in a 90 nm CMOS Process 2016 IEEE International Nanoelectronics Conference (INEC), Chengdu, China, 2016 [13] -Time Linear Equalizers Using Model Order Reduction Techniques, -EPEP Electrical Performance of Electronic Packaging, San Jose, CA, USA, 2008, pp 187-190 [14] M Grigoryan, A Atanesyan, G Hakoby and S Harutyunyan 2020 IEEE 40th International Conference on Electronics and Nanotechnology (ELNANO), Kyiv, Ukraine, 2020, pp 374-377 [15] S Gondi, and B Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers, Journal of Solid-State Circuits, vol 42, pp 1999-2011, 2007 [16] B Razavi, Design of Analog CMOS Integrated Circuits, 2nd Edition New York, US: McGraw Hill, 2017 [17] S Palermo, S Hoyos, A Shafik, E Z Tabasy, S Cai, S Kiran, and K ADC-Based Receivers for High-Speed Electrical and Optical Links, IEEE Communications Magazine, vol 54, pp 168-175, 2016 [18] H E Weste, and D M Harris, CMOS VLSI Design : A Circuits and Systems Perspective Macquarie University and The University of Adelaide, 2009 [19] F Ohnhäuser, Analog-Digital Converters for Industrial Applications Including an Introduction to Digital-Analog Converters Springer, 2015 [20] J van de Plassche, High-speed and High-Resolution Analog-To-Digital and DigitalTo-Analog Converters Eindhoven, Dutch: Technische Universiteit Eindhoven, 1992 [21] H Nguyen Minh, D Nguyen Quoc, and T A Design of 10-bit 25-MS/s SAR ADC Using Separated Clock Frequencies with High Speed Comparator in 180nm 74 Lu t nghi p Th CMOS 2015 GVHD: PGS.TS Hoàng Trang International Conference on Advanced Technologies for Communications (ATC), Ho Chi Minh, Viet Nam, 2015 [22] R Hedayati, ntation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology, Master s Thesis, Linkopin university, Sweden, 2011 [23] S Chang, Member, G Huang, and Y A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure, IEEE Journal of Solid-State Circuits, vol 45, pp 731-740, 2010 [24] V A Low Power 10-bit SAR ADC in a 45nm CMOS process Master s Thesis, Faculty of Electrical Engineering, Mathematics and Computer Science Electronic Instrumentation Laboratory, Delft University of Technology, Dutch, 2012 [25] D Moni, High-Speed and Low-Power Dynamic Latch Comparator 2012 International Conference on Devices, Circuits and Systems (ICDCS), Tamil Nadu, India, 2012 [26] G D Colleta, et al IEEE 3rd Latin American Symp Circuits and Systems,pp 1-4, 2012, DOI: 10.1109/LASCAS.2012.6180319 [27] W Hu et al., -bit Single-Ended Ultra Low Power SAR ADC with Novel DAC Switching Method and Counter Based Digital Control Circuitry IEEE Trans Circuits and Systems, vol 60, no 7, pp 17261740, 2013 [28] C Perumal Design of A Successive Approximation (Sar) Adc in 65 nm Technology PhD Dissertation, Department of Electrical and Information Technology Faculty of Engineering, LTH, Lund University SE-221 00 Lund, Sweden [29] Study of Various ADCs and Compare Their Performance and Parameters, International Journal of Advanced Engineering Research and Technology, Vol 3, Iss 3, March 2015 75 Lu t nghi p Th GVHD: PGS.TS Hoàng Trang LÝ L CH TRÍCH NGANG H tên: Hà Nam Anh 09/09/1997 a ch liên l c: E3- Chí Linh, P10, TP V ng Tàu O 2015- i h c Bách Khoa H Chí Minh Q TRÌNH CƠNG TÁC 2019-2022: Công ty thi t k vi m ch SAVARTI 76 ... CÁN B NG D N: PGS. TS Hoàng Trang Tp HCM, ngày 15 tháng CÁN B NG D N CH NHI M B O PGS. TS Hoàng Trang NG KHOA N- NT ii Lu t nghi p Th GVHD: PGS. TS Hoàng Trang L IC L... nghi p Th GVHD: PGS. TS Hoàng Trang C HOÀN THÀNH T I: I H C BÁCH KHOA Cán b -HCM ng d n khoa h c : PGS. TS Hoàng Trang Cán b ch m nh n xét : TS Hu nh Phú Mi ng Cán b ch m nh n xét : TS Nguy Lu... ch a (n u có) CH T CH H NG h giá LV ng Khoa qu n lý chuyên NG KHOA NT PGS. TS Hoàng Trang i Lu t nghi p Th GVHD: PGS. TS Hoàng Trang I H C QU C GIA TP.HCM I H C BÁCH KHOA C NG HÒA XÃ H I CH T NAM
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