Tài liệu High-Level Synthesis pptx

[...]... for High-Level Synthesis Joonhwan Yi and Hyukmin Kwon, Telecommunication R&D, Samsung Electronics Co High-level synthesis technology and its automation tools have been in the market for many years However the technology is not mature enough for industry to widely accept it as an implementation solution Here, our viewpoints regarding high-level synthesis are presented The languages that a high-level synthesis. .. the most difficult problems for our high-level synthesis engineers is that the code changes and additional information needed for desired RTL designs are not clearly defined yet Behaviorally identical two high-level codes usually result in very different RTL designs with current high-level synthesis tools Recall that RTL designs also impose many coding rules for logic synthesis and lint tools exist for... information about them We think high-level synthesis is one of the most important enabling technologies that fill the gap between the integration capacity of modern semiconductor processes and the design productivity of human Although high-level synthesis is suffering from several problems mentioned above, we believe these problems will 1 User Needs 11 be overcome soon and high-level synthesis will prevail in... efforts in the domain, though we have made a reasonable attempt to document important technical developments in the history of high-level synthesis Keywords: High-level synthesis, Scheduling, Resource allocation and binding, Hardware modeling, Behavioral synthesis, Architectural synthesis 2.1 Introduction Modern integrated circuits have come to be characterized by the scaling of Moore’s law which essentially... a high-level synthesis tool needs to provide ways to describe both block bodies and block interfaces properly Generally speaking, high-level synthesis tools need to support common syntaxes and commands of C/C++/SystemC that are usually used to describe the hardware behavior at the algorithm level They include arrays, loops, dynamic memories, pointers, C++ classes, C++ templates, and so on Current high-level. .. design systems, available at http://www.calypto.com/products/index.html A Rajawat, M Balakrishnan, A Kumar, Interface synthesis: issues and approaches, Int Conf on VLSI Design, pp 92–97, 2000 Chapter 2 High-Level Synthesis: A Retrospective Rajesh Gupta and Forrest Brewer Abstract High-level Synthesis or HLS represented an ambitious attempt by the community to provide capabilities for “algorithms to gates”... design for testability (DFT) of the generated RTL designs should be taken into account in high-level synthesis Otherwise, the generated RTL designs cannot be tested and thus cannot be implemented Secondly, automatic design constraint generation is necessary for gate-level synthesis and timing analysis A high-level synthesis tool should learn all the timing behavior of the generated RTL designs such as... the future directions in which they wish to see the high-level synthesis evolves like multi-clock domain support, block interface synthesis, joint optimisation of the datapath and control logic, integration of automated testing to the generated hardware or efficient taking into account of the target implementation technology for ASICs and FPGAs in the synthesis process Pascal Urard STMicroelectronics... exist for checking those rules Likewise, a set of well defined C/C++/SystemC coding rules for high-level synthesis should exist So far, this problem is handled by a brute-force way and well-skilled engineers are needed for better quality of results One of the most notable limitations of the current high-level synthesis tools is not to support multiple clock domain designs It is very common in modern... Yi and Hyukmin Kwon Telecommunication R&D, Samsung Electronics Co., South Korea Alexandre Gouraud France Telecom R&D P Coussy and A Morawiec (eds.) High-Level Synthesis c Springer Science + Business Media B.V 2008 1 2 P Urard et al Keywords: High-level synthesis, Productivity, ESL, ASIC, SoC, FPGA, RTL, ANSI C, C++, SystemC, VHDL, Verilog, Design, Verification, IP, TLM, Design space exploration, Memory, .