Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. ANALOG BEHAVIORAL MODELING WITH THE VERILOG-A LANGUAGE Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. ANALOG BEHAVIORAL MODELING WITH THE VERILOG-A LANGUAGE by Dan FitzPatrick Apteq Design Systems, Inc. and Ira Miller Motorola KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. eBook ISBN: 0-306-47918-4 Print ISBN: 0-7923-8044-4 ©2003 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print ©1998 Kluwer Academic Publishers All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: http://kluweronline.com and Kluwer's eBookstore at: http://ebooks.kluweronline.com Dordrecht Disk only available in print edition Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Contents 1 Introduction 1.2 1.3 Motivation Product Design Methodologies The Role of Standards 1.3.1 Verilog-A as an Extension of Spice 1.4 The Role of Verilog-A 1.4.1 Looking Ahead to Verilog-AMS 2 Analog System Description and Simulation 2.1 2.2 Introduction Representation of Systems 2.2.1 2.2.2 2.2.3 Anatomy of a Module Structural Descriptions Behavioral Descriptions 2.3 Mixed-Level Descriptions Refining the Module 2.4 Types of Analog Systems Conservative Systems Branches v 1 1 3 7 8 9 10 11 11 12 13 14 16 19 22 25 25 26 2.3.1 2.4.1 2.4.2 1.1 Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Analog Behavioral Modeling With the Verilog-A Language 2.4.3 Conservation Laws In System Descriptions 2.4.4 Signal-Flow Systems 2.5 Signals in Analog Systems 2.5.1 2.5.2 2.5.3 Access Functions Implicit Branches Summary of Signal Access 2.6 Probes, Sources, and Signal Assignment 2.6.1 2.6.2 2.6.3 Probes Sources Illustrated Examples 2.7 Analog System Simulation 2.7.1 Convergence 3 Behavioral Descriptions 3.1 3.2 3.3 Introduction Behavioral Descriptions 3.2.1 Analog Model Properties Statements for Behavioral Descriptions 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 Analog Statement Contribution Statements Procedural or Variable Assignments Conditional Statements and Expressions Multi-way Branching 3.4 Analog Operators 3.4.1 3.4.2 3.4.3 Time Derivative Operator Time Integral Operator Delay Operator 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 Transition Operator. Slew Operator Laplace Transform Operators Z-Transform Operators Considerations on the Usage of Analog Operators 3.5 Analog Events 3.5.1 3.5.2 Cross Event Analog Operator Timer Event Analog Operator 3.6 Additional Constructs 3.6.1 Access to Simulation Environment vi 27 29 29 31 32 33 33 34 35 37 38 40 41 41 42 43 45 45 47 48 49 51 53 53 55 57 58 62 64 68 74 74 75 78 80 80 Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Contents 3.6.2 3.6.3 3.6.4 Indirect Contribution Statements Case Statements Iterative Statements 3.7 Developing Behavioral Models 3.7.1 3.7.2 3.7.3 Development Methodology System and Use Considerations Style 4 Declarations and Structural Descriptions 4.1 4.2 4.3 Introduction Module Overview 4.2.1 4.2.2 4.2.3 Introduction to Interface Declarations Introduction to Local Declarations Introduction to Structural Instantiations Module Interface Declarations 4.3.1 Port Signal Types and Directions 4.3.2 Parameter Declarations 4.4 Local Declarations 4.5 Module Instantiations 4.5.1 4.5.2 4.5.3 Positional and Named Association Example Assignment of Parameters Connection of Ports 5 Applications 5.1 5.2 Introduction Behavioral Modeling of a Common Emitter Amplifier 5.2.1 5.2.2 5.2.3 5.2.4 Functional Model Modeling Higher-Order Effects Structural Model of Behavior Behavioral Model 5.3 A Basic Operational Amplifier 5.3.1 5.3.2 Model Development Settling Time Measurement 5.4 Voltage Regulator 5.4.1 Test Bench and Results 81 83 83 84 84 85 86 87 87 87 90 91 92 93 93 96 98 99 100 102 104 107 107 108 112 114 116 118 122 122 127 129 133 vii Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Analog Behavioral Modeling With the Verilog-A Language 5.5 QPSK Modulator/Demodulator 5.5.1 5.5.2 Modulator Demodulator 5.6 Fractional N-Loop Frequency Synthesizer 5.6.1 5.6.2 5.6.3 5.6.4 Digital VCO Pulse Remover Phase-Error Adjustment Test Bench and Results 5.7 Antenna Position Control System 5.7.1 5.7.2 5.7.3 5.7.4 5.7.5 Potentiometer DC Motor Gearbox Antenna Test Bench and Results Appendix A Lexical Conventions and Compiler Directives A.1 Verilog-A Language Tokens A.1.1 White Space A.1.2 Comments A.1.3 Operators A.1.4 Numbers A.1.5 Conversion A.1.6 Identifiers, Keywords and System Names A.1.7 Escaped Identifiers A.1.8 Keywords A.1.9 Verilog-A Keywords A.1.10Math Function Keywords A.1.11Analog Operator Keywords A.1.12System Tasks and Functions A.2 Compiler Directives A.2.1 ‘define and ‘undef A.2.2 ‘ifdef, ‘else, ‘endif A.2.3 ‘include A.2.4 ‘resetall viii 137 137 140 143 145 147 149 150 153 154 154 155 156 157 159 159 159 160 160 161 162 162 162 162 163 163 164 165 165 165 166 167 168 Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Contents Appendix B System Tasks and Functions B.1 B.2 B.3 B.4 B.5 B.6 B.7 Introduction Strobe Task B.2.1 Examples File Output Simulation Time Probabilistic Distribution Random Simulation Environment Appendix C Laplace and Discrete Filters C.1 C.2 Introduction Laplace Filters C.2.1 laplace_zp C.2.2 laplace_zd C.2.3 laplace_np C.2.4 laplace_nd C.3 Discrete Filters C.3.1 zi_zp C.3.2 zi_zd C.3.3 zi_np C.3.4 zi_nd C.4 Verilog-A MATLAB Filter Specification Scripts Appendix D Verilog-A Explorer IDE D.1 D.2 Introduction Installation and Setup D.2.1 Overview of the Distribution D.2.2 Executable and Include Path Setup D.2.3 Overview of the IDE Organization D.3 Using the Explorer IDE D.3.1 Opening and Running an Existing Design D.3.2 Creating a New Designs 169 169 169 170 170 171 171 172 173 175 175 175 175 176 177 177 178 178 179 179 180 181 185 185 187 187 188 189 191 192 198 ix Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Analog Behavioral Modeling With the Verilog-A Language Appendix E Spice Quick Reference E.1 E.2 E.3 Introduction Circuit Netlist Description Components E.3.1 E.3.2 Elements Semiconductor Devices and Models E.4 Analysis Types E.4.1 E.4.2 E.4.3 E.4.4 Operating Point Analysis DC Transfer Curve Analysis Transient Analysis AC Small-signal Analysis 199 199 200 201 201 203 204 204 204 204 205 x Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. [...]... that system In an analog HDL such as Verilog-A, behavioral descriptions map directly to the mathematical relationships of the system Both the structural and behavioral abstractions of system definitions share the signals of the system Signal definitions in Verilog-A have their basis in both the requirements of their usage for behavioral descriptions and the underlying requirements of analog simulation... methodologies, the Verilog-A language allows utilization of existing frameworks, libraries, models, and training 1.4 The Role of Verilog-A The Verilog-A language allows the description of analog and/or mixed-signal systems with varying amounts of detail The analog behavioral capability allows the designer to span the abstraction levels, allowing direct access to the underlying technology while maintaining the. .. (LRM) by the OVI Verilog-A Technical Subcommittee These design objectives of the Verilog-A language were considered in the context of meeting the goals of the use model of the language, including: Enable the communication of high-level design information including electronic and electro-mechanical or other system aspects Apply behavioral approaches in the design at the architectural level Encourage the. .. uses of analog behavioral modeling with the Verilog-A language In doing so, an overview of Verilog-A language constructs as well as applications using the xiii Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark Verilog-A HDL language are presented In addition, the book is accompanied by the Verilog-A Explorer IDE (Integrated Development Environment), a limited capability Verilog-A. .. designed to provide an outline of the Verilog-A language in terms of structural and behavioral definitions In Chapter 3 we investigate more thoroughly the behavioral aspects of the Verilog-A language, while Chapter 4 does the same for the structural constructs within the language Chapter 5 brings these concepts together in a variety of applications presented in their entirety The appendices provide detailed... group of the Open Verilog International (OVI) organization The LRM Version 1.0, August 1, 1996 is not yet fully defined and is subject to change As such, the material in this book focuses on the core aspects of the Verilog-A language as presented in the LRM and the work within the OVI Verilog-A Technical Subcommittee The goal of this book is to provide the designer a brief introduction into the methodologies... to the designer and/or model developer with enough capability to learn analog behavioral modelling with the Verilog-A language The Verilog-A Explorer IDE incorporates context sensitive editors, waveform display, and simulator based on Spice3 from the University of California Berkeley along with Apteq Design Systems’s Spice Analog HDL Extension Kernel and Verilog-A compiler integrated In addition, the. .. syntax and semantics of the Verilog HDL language for the description and simulation of analog and mixed-signal systems from behavioral to the circuit level A comprehensive set of objectives for the Verilog-A language definition were gathered by the OVI Verilog-A committee and incorporated into the OVI Design Objective Document (DOD) These objectives were used in developing the Verilog-A Language Reference... Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark Introduction Among multiple groups participating in the design, accuracy in the representation of the design is crucial as the complexity of the development, as well as the diversity in the tools, becomes greater The sequential nature of the product development process has a two-fold impact in that steps within the process typically... this example, these signals are the indicated by the identifiers dout and din The module also defines any directionality associated with those connection points (in Listing 2.1, the connection points dout and din are defined as inout or bidirectional), as well as the type of the analog signals (electrical) The other facet of the interface declarations are parameter definitions which allow the characterization . purchase PDF Split-Merge on www.verypdf.com to remove this watermark. ANALOG BEHAVIORAL MODELING WITH THE VERILOG-A LANGUAGE Please purchase PDF Split-Merge. focuses on the core aspects of the Verilog-A language as presented in the LRM and the work within the OVI Verilog-A Technical Subcommittee. The goal of