© 2002 by CRC Press LLC 6 Multilevel Converters 6.1 Introduction 6.2 Multilevel Voltage Source Modulation 6.3 Fundamental Multilevel Converter Topologies Diode-Clamped Multilevel Converters • Flying-Capacitor Multilevel Converters • Cascaded H-Bridge Multilevel Converters • Multilevel H-Bridge Converters 6.4 Cascaded Multilevel Converter Topologies Cascaded Multilevel Converters • Cascaded Multilevel H-Bridge Converters 6.5 Multilevel Converter Laboratory Examples Three-Level Diode-Clamped Inverter • The Cascade-3/2 Inverter • The Cascade-5/3H Inverter 6.6 Conclusion 6.1 Introduction Multilevel power conversion was first introduced 20 years ago [1]. The general concept involves utilizing a higher number of active semiconductor switches to perform the power conversion in small voltage steps. There are several advantages to this approach when compared with traditional (two-level) power conversion. The smaller voltage steps lead to the production of higher power quality waveforms and also reduce the dv / dt stresses on the load and reduce the electromagnetic compatibility (EMC) concerns. Another important feature of multilevel converters is that the semiconductors are wired in a series-type connection, which allows operation at higher voltages. However, the series connection is typically made with clamping diodes, which eliminates overvoltage concerns. Furthermore, since the switches are not truly series connected, their switching can be staggered, which reduces the switching frequency and thus the switching losses. One clear disadvantage of multilevel power conversion is the larger number of semiconductor switches required. It should be pointed out that lower voltage rated switches can be used in the multilevel converter and therefore the active semiconductor cost is not appreciably increased when compared with the two- level case. However, each active semiconductor added requires associated gate drive circuitry and adds further complexity to the converter mechanical layout. Another disadvantage of multilevel power con- verters is that the small voltage steps are typically produced by isolated voltage sources or a bank of series capacitors. Isolated voltage sources may not always be readily available and series capacitors require voltage balance. To some extent, the voltage balancing can be addressed by using redundant switching states, which exist due to the high number of semiconductor devices. However, for a complete solution to the voltage-balancing problem, another multilevel converter may be required [2–4]. In recent years, there has been a substantial increase in interest in multilevel power conversion. This is evident by the fact that some Institute of Electrical and Electronic Engineers (IEEE) conferences are Keith Corzine University of Wisconsin–Milwaukee © 2002 by CRC Press LLC now holding entire sessions on multilevel converters. Recent research has involved the introduction of novel converter topologies and unique modulation strategies. Some applications for these new converters include industrial drives [5–7], flexible AC transmission systems (FACTS) [8–10], and vehicle propulsion [11, 12]. One area where multilevel converters are particularly suitable is that of medium-voltage drives [13]. This chapter presents an overview of multilevel power conversion methods. The first section describes a general multilevel power conversion system. Converter performance is discussed in terms of voltage levels without regard to the specific topology of the semiconductor switches. A general method of multilevel modulation is described that may be extended to any number of voltage levels. The next section discusses the switching state details of fundamental multilevel converter topologies. The concept of redundant switching states is introduced in this section as well. The next section describes cascaded multilevel topologies, which involve alternative connections of the fundamental topologies. The final section shows example multilevel power conversion systems including laboratory measurements. 6.2 Multilevel Voltage Source Modulation Before proceeding with the discussion of multilevel modulation, a general multilevel power converter structure will be introduced and notation will be defined for later use. Although the primary focus of this chapter is on power conversion from DC to an AC voltages (inverter operation), the material presented herein is also applicable to rectifier operation. The term multilevel converter is used to refer to a power electronic converter that may operate in an inverter or rectifier mode. Figure 6.1 shows the general structure of the multilevel converter system. In this case, a three-phase motor load is shown on the AC side of the converter. However, the converter may interface to an electric utility or drive another type of load. The goal of the multilevel pulse-width modulation (PWM) block is to switch the converter transistors in such a way that the phase voltages v as , v bs , and v cs are equal to commanded voltages , , and . The commanded voltages are generated from an overall supervisory FIGURE 6.1 Multilevel converter structure. v as ∗ v bs ∗ v cs ∗ dc dc as as bs bs cs cs © 2002 by CRC Press LLC control [14] and may be expressed in a general form as (6.1) (6.2) (6.3) where is a voltage amplitude and θ c is an electrical angle. To describe how the modulation is accom- plished, the converter AC voltages must be defined. For convenience, a line-to-ground voltage is defined as the voltage from one of the AC points in Fig. 6.1 ( a , or b , or c ) to the negative pole of the DC voltage (labeled g in Fig. 6.1). For example, the voltage from a to g is denoted v ag . It is important to note that the converter has direct control of the voltages v ag , v bg , and v cg . The next step in defining the control of the line-to-ground voltages is expressing a relationship between these voltages and the motor phase voltages. Assuming a balanced wye-connected load, it can be shown that [15] (6.4) Because an inverse of the matrix in Eq. (6.4) does not exist, there is no direct relationship between commanded phase voltages and line-to-ground voltages. In fact, there are an infinite number of voltage sets { v ag v bg v cg } that will yield a particular set of commanded phase voltages because any zero sequence components of the line-to-ground voltages will not affect the phase voltages according to Eq. (6.4). In a three-phase system, zero sequence components of { v ag v bg v cg } include DC offsets and triplen harmonics of θ c . To maximize the utilization of the DC bus voltage, the following set of line-to-ground voltages may be commanded [16] (6.5) (6.6) (6.7) where m is a modulation index. It should be noted that the power converter switching will yield line-to- ground voltages with a high-frequency component and, for this reason, the commanded voltages in Eqs. (6.5) to (6.7) cannot be obtained instantaneously. However, if the high-frequency component is neglected, then the commanded line-to-ground voltages may be obtained on a fast-average basis. By substitution of Eqs. (6.5) to (6.7) into Eq. (6.4), it can be seen that commanding this particular set of line-to-ground voltages will result in phase voltages of (6.8) (6.9) (6.10) v as ∗ 2 v s ∗ θ c ()cos= v bs ∗ 2 v s ∗ θ c 2 π 3 – cos= v cs ∗ 2 v s ∗ θ c 2 π 3 + cos= v s ∗ v as v bs v cs 1 3 21– 1– 1– 21– 1– 1– 2 v ag v bg v cs = v ag ∗ v dc 2 1 m θ c ()cos m 6 3 θ c ()cos–+= v bg ∗ v dc 2 1 m θ c 2 π 3 – cos m 6 3 θ c ()cos–+= v cg ∗ v dc 2 1 m θ c 2 π 3 + cos m 6 3 θ c ()cos–+= v ˆ as mv dc 2 θ c ()cos= v ˆ bs mv dc 2 θ c 2 π 3 – cos= v ˆ cs mv dc 2 θ c 2 π 3 + cos= © 2002 by CRC Press LLC where the symbol denotes fast-average values. By comparing Eqs. (6.8) to (6.10) with Eqs. (6.1) to (6.3), it can be seen that the desired phase voltages are achieved if (6.11) It should be noted that in H-bridge-based converters, the range of line-to-ground voltage is twice that of converters where one DC voltage supplies all three phases (as in Fig. 6.1). The modulation method here can accommodate these converters if the modulation index is related to the commanded voltage magnitude by (6.12) The modulation process described here may be applied to H-bridge converters by substituting m H for m in the equations that follow. The benefit of including the third harmonic terms in Eqs. (6.5) to (6.7) is an extended range of modulation index [16]. In particular, the range of the modulation index is (6.13) It is sometimes convenient to define a modulation index that has an upper limit of 100% or (6.14) The next step in the modulation process is to define normalized commanded line-to-ground voltages, which will be referred to as duty cycles. In terms of the modulation index and electrical angle, the duty cycles may be written: (6.15) (6.16) (6.17) To relate the duty cycles to the inverter switching operation, switching states must be defined that are valid for any number of voltage levels. Here, the switching states for the a -, b -, and c -phase will be denoted s a , s b , and s c , respectively. Although the specific topology of the multilevel converter is covered in the next section, it may be stated in general for an n -level converter that the AC output consists of a number of ˆ m 22v s ∗ v dc = m H 2 v s ∗ v dc = 0 m 2 3 ≤≤ m 3 2 m= d a 1 2 1 m θ c ()cos m 6 3 θ c ()cos–+= d b 1 2 1 m θ c 2 π 3 – cos m 6 3 θ c ()cos–+= d c 1 2 1 m θ c 2 π 3 + cos m 6 3 θ c ()cos–+= © 2002 by CRC Press LLC voltage levels related to the switching state by (6.18) (6.19) (6.20) As can be seen, a higher number of levels n leads to a larger number of switching state possibilities and smaller voltage steps. An overall switching state can be defined by using the base n mathematical expression (6.21) Figure 6.2 shows the a-phase commanded line-to-ground voltage according to Eq. (6.5) as well as line- to-ground voltages for two-level, three-level, and four-level converters. In each case, the fast-average of v ag will equal the commanded value . However, it can be seen that as the number of voltage levels increases, the converter voltage yields a closer approximation to the commanded value, resulting in lower harmonic distortion. The next step in multilevel modulation is to relate the switching states s a , s b , and s c to the duty cycles defined in Eqs. (6.14) through (6.16). Here, the multilevel sine-triangle technique will be used for this purpose [17, 18, 19]. The first step involves scaling the duty cycles for the n-level case as (6.22) (6.23) (6.24) The switching state may then be directly determined from the scaled duty cycles by comparing them to a set of high-frequency triangle waveforms with a frequency of f sw . For an n-level converter, n − 1 triangle waveforms of unity amplitude are defined. As an example, consider the four-level case. Figure 6.3a shows the a-phase duty cycle and the three triangle waveforms offset so that their peaks correspond to the nearest switching states. In general, the highest triangle waveform has a minimum value of (n − 2) and a peak value of (n − 1). The switching rules for the four-level case are fairly straightforward and may be specifically stated as (6.25) Figure 6.3b shows the resulting switching state based on the switching rules. As can be seen, the form is similar to that of Fig. 6.2d and, therefore, the resulting line-to-ground voltage according to Eq. (6.17) will have a fast-average value equal to its commanded value. These switching rules may be extended to v ag s a v dc n 1–() s a 0, 1, … n 1–()== v bg s b v dc n 1–() s b 0, 1, … n 1–()== v cg s c v dc n 1–() s c 0, 1, … n 1–()== sw n 2 s a ns b s c ++= v ag ∗ d am n 1–()d a = d bm n 1–()d b = d cm n 1–()d c = s a 0 d am v tr1 < 1 v tr1 d am v tr2 <≤ 2 v tr2 d am v tr3 <≤ 3 v tr3 d am ≤ = © 2002 by CRC Press LLC any number of levels by incorporating the appropriate number of triangle waveforms and defining switching rules similar to Eq. (6.25). It should be pointed out that the sine-triangle method is shown here since it is depicts a fairly straightforward method of accomplishing multilevel switching. In practice, the modulation is typically implemented on a digital signal processor (DSP) or erasable programmable logic device (EPLD) without using triangle waveforms. One common method for implementation is space-vector modulation [20–22], which is a method where the switching states are viewed in the voltage reference frame. Another method that may be used is duty-cycle modulation [23], which is a direct calculation method that uses duty cycles instead of triangle waveforms and is more readily implementable on a DSP. It is also possible to perform modulation based on a current-regulated approach [22, 24], which is fundamentally different than voltage-source modulation and results in a higher bandwidth control of load currents. FIGURE 6.2 Power converter line-to-ground output voltages. ag dc ag dc ag dc ag dc © 2002 by CRC Press LLC 6.3 Fundamental Multilevel Converter Topologies This section describes the most common multilevel converter topologies. In particular, the diode-clamped [25–28], flying capacitor [29, 30], cascaded H-bridge [31–33], and multilevel H-bridge [34] structures are described. In each case, the process of creating voltage steps is illustrated and the relation to the generalized modulation scheme in the previous section is defined. For further study, the reader may be interested in other topologies not discussed here, such as the parallel connected phase poles [35], AC magnetically combined converters [36, 37], or soft-switching multilevel converters [38]. Diode-Clamped Multilevel Converters One of the most common types of multilevel topologies is the diode-clamped multilevel converter [25–28]. Figure 6.4 shows the structure for the three-level case. Comparing this topology with that of a standard two-level converter, it can be seen that there are twice as many transistors as well as added diodes. However, it should be pointed out that the voltage rating of the transistors is half that of the transistors in a two-level converter. Although the structure appears complex, the switching is fairly straightforward. Figure 6.5 shows the a-phase leg of the three-level diode clamped converter along with the corresponding switching states. Here, it is assumed that the transistors act as ideal switches and that the capacitor voltages are charged to half of the DC-link voltage. As can be seen in Fig. 6.5b, in switching state s a = 0, transistors T a3 and T a4 are gated on and the output voltage is v ag = 0. Similarly, switching state s a = 2 involves gating on transistors T a1 and T a2 and the output voltage is v ag = v dc . These switching states produce the same voltages as a two-level converter. Switching state s a = 1 involves gating on transistors T a2 and T a3 as shown in Fig. 6.5c. In this case, the point a is connected to the capacitor junction through the added diodes and the output voltage is v ag = v dc /2. Note that for each of the switching states, the transistor blocking voltage is one half the DC-link voltage. When compared with the two-level converter, the additional voltage level allows the production of line-to-ground voltages with lower harmonic distortion, as illustrated in Fig. 6.2. Furthermore, the switching losses for this converter will be lower than that of a two-level converter. Switching losses are reduced by the lower transistor blocking voltage and increased by the higher number of transistors. However, it can be seen by inspection of Figs. 6.2 and 6.5 that each transistor is switching only during a portion of the period of d a , which again reduces the switching losses. Maintaining voltage balance on the capacitors can be accomplished through selection of the FIGURE 6.3 Four-level sine-triangle modulation technique. a a m tr3 tr2 tr1 © 2002 by CRC Press LLC FIGURE 6.4 Four-level converter topology. FIGURE 6.5 Three-level converter switching states. as as cs bs dc a1 a2 a3 a4 ag dc dc dc dc dc dc ag ag ag a a a dc © 2002 by CRC Press LLC redundant states [27]. Redundant switching states are states that lead to the same motor voltages, but yield different capacitor currents. As an example, consider the three-level converter redundant switching states sw = 24 and sw = 9 shown in Fig. 6.6. It can be shown through Eq. (6.4) that either switching state will produce the same voltages on the load (assuming the capacitor voltages are nearly balanced). However, from Fig. 6.6 it can be seen that the current drawn from the capacitor bank will be different in each case. In particular, if the a-phase current is positive, the load will discharge the capacitor that it is connected to. In this case, the load should be connected across the capacitor with the highest voltage. On the other hand, if the a-phase current is negative, it will have a charging effect and the load should be connected across the capacitor with the lowest voltage. Therefore, capacitor voltage balancing through redundant state selection (RSS) is a straightforward matter of selecting between the redundant states based on which capacitor is overcharged with respect to the other and the direction of the phase currents. This infor- mation may be stored in a lookup table for inclusion in the modulation scheme [25, 27]. Figure 6.7 shows a block diagram of how an RSS table may be included in the modulation control. There, the modulator determines the desired switching states as described in the previous section. The desired switching state as well as the capacitor imbalance and phase current direction information are used as inputs to the lookup table, which determines the final switching state. As a practical matter, this table may be implemented in a DSP along with the duty-cycle calculations or may be programmed into an EPLD as a logic function. FIGURE 6.6 Redundant switching state example. FIGURE 6.7 Redundant switching state example. c2 as c2 as c1 c1 as as s * *** c a x c12 c12 c1 c1 c2 c2 xs xs bc abc abc a b c © 2002 by CRC Press LLC Figure 6.8 shows the topology for the four-level diode-clamped converter. Proper operation requires that each capacitor be charged to one third of the DC-link voltage. The transistor switching is similar to that of a three-level converter in that there are (n − 1) adjacent transistors gated on for each switching state. The switching results in four possibilities for the output voltage v ag = {0 v dc v dc v dc }. In this topology, each transistor need only block one third of the DC-link voltage. The diode-clamped concept may be extended to a higher number of levels by the expansion of the capacitor bank, switching transistors, and clamping diodes. However, there are some practical problems with diode-clamped converters of four voltage levels or more. The first difficulty is that some of the added diodes will need to block (n − 2)/ (n − 1) of the DC-link voltage [28]. As the number of levels is increased, it may be necessary to connect clamping diodes in series to block this voltage. It should also be pointed out that capacitor voltage balance through RSS works well for the three-level topology, but for converters with a higher number of voltage levels there are not enough redundant states to balance the capacitor voltages when the modulation index becomes greater than 60% [27]. In these cases, another multilevel converter, such as a multilevel rectifier [25] of multilevel DC-DC converter [25] must be placed on the input side for voltage balance. Flying-Capacitor Multilevel Converters Figure 6.9 shows one phase of a three-level flying-capacitor multilevel converter. The general concept behind this converter is that the added capacitor is charged to one half of the DC-link voltage and may be inserted in series with the DC-link voltage to form an additional voltage level [29, 30]. Figure 6.10 shows how this is accomplished through the transistor switching. As can be seen, switching states s a = 0 and s a = 2 involve gating on the two lower and upper transistors as was done with the diode-clamped structure. In this topology, there are two options for switching to the state s a = 1, as can be seen in Fig. 6.10c. The capacitor voltage may be either added to the converter ground or subtracted from the DC- link voltage. In essence, there is switching redundancy within the phase leg. Since the direction of the current through the capacitor changes depending on which redundant state is selected, the capacitor FIGURE 6.8 Four-level converter topology. 3 a1 b1 a2 b2 a3 b3 c1 as as cs bs c2 c3 a4 a5 a6 0 b6 c6 b4 c4 c5 b5 1 dc 2 1 3 2 3 m [...]... 5th European Conference on Power Electronics and Applications, Brighton, U.K., 1993, 134 8 Seki, N and Uchino, H., Converter configurations and switching frequency for a GTO reactive power compensator, IEEE Trans Ind Appl., 33, 1011, 1997 9 Chen, Y., Mwinyiwiwa, B., Wolanski, Z., and Ooi, B T., Regulating and equalizing DC capacitive voltages in multilevel statcom, IEEE Trans Power Delivery, 12, 901,... Phoenix, 1999, 1964 24 Marchesoni, M., High-performance current control techniques for applications to multilevel highpower voltage source inverters, IEEE Trans Power Electron., 7, 189, 1992 © 2002 by CRC Press LLC 25 Corzine, K A., Delisle, D E., Borraccini, J P., and Baker, J R., Multi-level power conversion: present research and future investigations, in Proc All Electric Ship Conference, IMarE, Paris,... converter topologies for improved power quality in DC traction, in Proc ISIE, IEEE, Warsaw, 1996, 802 29 Tourkhani, F., Viarouge, P., and Meynard, T A., A simulation-optimization system for the optimal design of a multilevel inverter, IEEE Trans Power Electron., 14, 1037, 1999 30 Yuan, X and Barbi, I., Zero-voltage switching for three-level capacitor clamping inverter, IEEE Trans Power Electron., 14, 771,... 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Multilevel PWM methods at low modulation indices, IEEE Trans Power Electron., 15, 719, 2000 19 Menzies, R W., Steimer, P., and Steknke, J K., Five-level GTO inverter for large induction motor drives, IEEE Trans Ind Appl., 30, 1994 20 Liu, H L and Cho, G H., Three-level space vector PWM in low index modulation region avoiding narrow pulse problem, IEEE Trans Power Electron., 9, 481, 1994 21 Lee, Y H., Suh, B... algorithm is effective 6.6 Conclusion This chapter has presented an overview of multilevel power conversion Multilevel voltage-source modulation was introduced and formulated in terms of a per-phase switching state which related to the converter line-to-ground voltage Several topologies for performing multilevel power conversion were presented and the switching states were defined to match that of the... method for a four-level inverter, in Proc Electric Power Applications, IEE, 1995, 390 5 Tenconi, S M., Carpita, M., Bacigalupo, C., and Cali, R., Multilevel voltage source converter for medium voltage adjustable speed drives, in Proc ISIE, IEEE, Athens, 1995, 91 6 Osman, R H., A medium-voltage drive utilizing series-cell multilevel topology for outstanding power quality, in Proc IAS, IEEE, Phoenix, 1999,... 1993, 1246 36 Iturriz, F and Ladoux, P., Phase-controlled multilevel converters based on dual structure associations, IEEE Trans Power Electron., 15, 92, 2000 37 Masukawa, S and Iida, S., A method of reducing harmonics in output voltages of a double-connected inverter, IEEE Trans Power Electron., 9, 543 38 Yamamoto, M., Hiraki, E., Iwamoto, H Sugimoto, S., Kouda, I., and Nakaoka, M., Voltage-fed NPC soft-switched... ratio of three is used for each cell added, the number of voltage levels for a given number of cells may be computed as n = (3) p (6.28) Besides an improvement in power quality, the DC voltage ratio used in Table 6.2 will also split the power conversion process into a high-voltage, low-switching frequency converter and a low-voltage, highswitching frequency converter [33] For this type of converter,... Philadelphia, 2000 41 Corzine, K A., Sudhoff, S D., and Whitcomb, C A., Performance characteristics of a cascaded twolevel converter, IEEE Trans Energy Conversion, 14, 433, 1999 42 Hart, D W., Introduction to Power Electronics, Prentice-Hall, Upper Saddle River, NJ, 1997, chap 8 © 2002 by CRC Press LLC . perform the power conversion in small voltage steps. There are several advantages to this approach when compared with traditional (two-level) power conversion increase in interest in multilevel power conversion. This is evident by the fact that some Institute of Electrical and Electronic Engineers (IEEE) conferences