... make ease-of-use tradeoffs in favor of core users.Because FPGAs are malleable andFPGA SoC design is so new, I wanted an interface that can evolve to addressnew requirements without invalidat-ing ... word), all decodedfrom AN 15:0, WORDN, and READN.MEMCTRL manages transfers onthe on-chip data bus D15:0 and theexternal data bus XD7:0 by assertingvarious tri-state output enables (xT)and ... inter-rupts, insert wait states, and so forth.EXTERNAL RAMThe external RAM is a classic32-KB fast asynchronous SRAM with a 15-ns access time (tAA). Its pins in- clude A1 4:0 (address), D7:0 (data in/ out),...