ARM System Developer’s Guide phần 4 docx
ARM System Developer’s Guide phần 4 docx
... 0x0016e797, 0xf4898d60, 0x0 043 ace2
DCD 0xed7303b6, 0x006f2109, 0xe6c2b 448 , 0x0099574f
DCD 0xe070381c, 0x00c2615f, 0xda 740 da7, 0x00ea4f72
DCD 0xd4c77b03, 0x0111307e, 0xcf 647 4a9, 0x0137124d
DCD 0xca4587e7, ... 0x57
DCB 0x55, 0x52, 0x50, 0x4e, 0x4c, 0x49, 0x47, 0x45
DCB 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x3a, 0x38, 0x36
DCB 0x 34, 0x32, 0x31, 0x2f, 0x2d, 0x2c, 0x2a, 0x29
DCB 0x27, 0x26, 0x 2...
ARM System Developer’s Guide phần 3 docx
... instructions:
sat_correlate_v3
STR r 14, [r13,# -4] ! ; stack lr
MOV r12,#0 ;a=0
sat_v3_loop
LDRSH r3,[r0],#2 ; r3 = *(x++)
LDRSH r 14, [r1],#2 ; r 14 = *(y++)
SUBS r2,r2,#1 ; N and set flags
1 64 Chapter 6 Writing and Optimizing ARM ... to
checksum_next_packet
STMFD r13!,{r4,r 14} ; save r4, lr on the stack
SUB r13,r13,#8 ; create two stacked variables
ADD r0,r13, #4 ; r0 = &N, N st...
ARM System Developer’s Guide phần 6 docx
... EQU FRAME_R0 +4
FRAME_R2 EQU FRAME_R1 +4
FRAME_R3 EQU FRAME_R2 +4
FRAME_R4 EQU FRAME_R3 +4
FRAME_R5 EQU FRAME_R4 +4
FRAME_R6 EQU FRAME_R5 +4
FRAME_R7 EQU FRAME_R6 +4
FRAME_R8 EQU FRAME_R7 +4
FRAME_R9 EQU ... Process control block.
Offset Registers
0—
4 r 14
−8 r13
−12 r12
−16 r11
−20 r10
− 24 r9
−28 r8
−32 r7
−36 r6
40 r5
44 r4
48 r3
−52 r2
−56 r1
−60 r0
− 64 pc + 4
−68 spsr...
ARM System Developer’s Guide phần 1 ppt
... Units 46 1
13.1 Protected Regions 46 3
13.2 Initializing the MPU, Caches, and Write Buffer 46 5
13.3 Demonstration of an MPU system 47 8
13 .4 Summary 48 7
Chapter
14
Memory Management Units 49 1
14. 1 ... an MMU 49 2
14. 2 How Virtual Memory Works 49 3
14. 3 Details of the ARM MMU 501
14. 4 Page Tables 501
14. 5 The Translation Lookaside Buffer 506
14. 6 Domains and Memo...
ARM System Developer’s Guide phần 2 ppsx
... increment after Rn Rn +4
∗
N − 4 Rn + 4
∗
N
IB increment before Rn + 4 Rn + 4
∗
NRn+ 4
∗
N
DA decrement after Rn − 4
∗
N + 4 Rn Rn − 4
∗
N
DB decrement before Rn − 4
∗
NRn− 4 Rn − 4
∗
N
Example
3.17
In ... MVN instruction.
4. 1 Thumb Register Usage
4. 2 ARM- Thumb Interworking
4. 3 Other Branch Instructions
4. 4 Data Processing Instructions
4. 5 Single-Register Lo...
ARM System Developer’s Guide phần 5 ppt
... 22.0
ARM9 TDMI 7.0 4. 8 8.3 22.0
StrongARM 4. 8 3.8 5.2 16.5
ARM9 E 2.5 1.3 4. 3 8.0
XScale 1.8 1.3 3.7 7.7
Table 8.10 ARM FFT benchmarks.
16-bit complex FFT (radix -4) ARM9 TDMI (cycles/FFT) ARM9 E ... (cycles/FFT) ARM9 E (cycles/FFT)
64 point 3,5 24 2 ,48 0
256 point 19,5 14 13,1 94
1,0 24 point 99, 946 66,196
4, 096 point 48 7,632 318,878
302 Chapter 8 Digital Signal Proc...
ARM System Developer’s Guide phần 7 pdf
... ARM9 26EJ-S,
ARM1 022E, ARM1 026EJ-S, StrongARM, XScale
Flush data cache MCR p15, 0, Rd, c7, c6, 0 ARM9 20T, ARM9 22T, ARM9 26EJ-S, ARM9 40 T,
ARM9 46 E-S, ARM1 022E, ARM1 026EJ-S,
StrongARM, XScale
Flush instruction ... XScale
Flush instruction cache MCR p15, 0, Rd, c7, c5, 0 ARM9 20T, ARM9 22T, ARM9 26EJ-S, ARM9 40 T,
ARM9 46 E-S, ARM1 022E, ARM1 026EJ-S,
StrongARM, XSc...
ARM System Developer’s Guide phần 8 pdf
... 0xFFFF0000
15612 2 347 8910 0
MCWRS
31
ARM7 20T
161112 2378910 0
IMCRS
31
ARM9 20T, ARM9 22T, ARM9 26EJ-S, ARM1 026EJ-S
13
V
14
13
V
14 54
11
161112 2378910 0
IMCRS
31
ARM1 022E
13
V
14
54
W
Figure 14. 13 CP15:c1 ... invalidate
ARM9 20T, ARM9 22T, ARM9 26EJ-S,
ARM1 022E, ARM1 026EJ-S,
StrongARM, XScale
Invalidate I
TLB by line
MCR p15, 0, Rd, c8, c5, 1 virtual address
to i...
ARM System Developer’s Guide phần 9 doc
... Rn if ! specified
{IA|FD} Rn Rn + N *4 - 4 Rn + N *4
{IB|ED} Rn + 4 Rn + N *4 Rn + N *4
{DA|FA} Rn - N *4 + 4 Rn Rn - N *4
{DB|EA} Rn - N *4 Rn - 4 Rn - N *4
N = the number of registers in <register_list>
start ... do not use pc in the register list.
Examples
LDMIA r4!, {r0, r1} ; r0=∗r4, r1=∗(r4 +4) , r4+=8
LDMDB r4!, {r0, r1} ; r1=∗(r4 -4) , r0=∗(r4-8), r4-=8
LDMEQFD sp...
ARM System Developer’s Guide phần 10 ppsx
... cycle early.
6 24 Appendix A ARM and Thumb Assembler Instructions
Table A.16 Predefined expressions.
Variable Value
{ARCHITECURE} The ARM architecture of the CPU (“4T” for ARMv4T)
{ARMASM_VERSION} ... 16-bit integer (aligned to 2 bytes)
DCD & 4 32-bit integer (aligned to 4 bytes)
DCQ 8 64- bit integer (aligned to 4 bytes)
DCI 2 or 4 integer defining an ARM or Thumb instructio...
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