the PCI Bus demystified phần 6 pdf

... information. Finally, the last two bytes of the header are a pointer to a PCI data structure. The reference point for this pointer is the beginning of the ROM image. Figure 6- 10 shows the PCI Data Structure ... identifying the bus number and device number, an Interrupt Routing Table Entry supplies two values for each of the four PCI bus interrupt lines. The IRQ b...

Ngày tải lên: 07/08/2014, 11:22

... monopolize the bus. This violates the low-latency spirit of the PCI spec. On the other hand, the specification does allow the notion of bus parking.” The arbiter may be designed to “park” the bus on ... While the choice of a default master is up to the system designer, the specification recommends parking on the last master that acquired the bus. PCI Bus...

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... immediately issues a retry to the master and begins executing the transaction internally. This allows the bus to be used by other masters while the target is busy. PCI Bus Demystified 39 least significant ... phase, another higher priority master may request the bus causing the arbiter to remove GNT# from the agent in the process of stepping. Since the stepping age...

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... access a 64 -bit memory address space. PCI Bus Demystified 63 64 -bit Bus Figure 4-4 shows a 64 -bit transaction. A 64 -bit master asserts REQ64# at the same time as FRAME# in clock 2. In this case the selected ... two optional signals; REQ64# and ACK64#. PCI Bus Demystified 60 supply the interrupt vector. The C/BE# bus indicates which bytes of the interrupt v...

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... specifications. PCI Bus Demystified 85 66 MHz PCI 66 MHz operation is defined in a way that allows 33 MHz cards to coexist with 66 MHz cards in much the same way that 32-bit cards coexist with 64 -bit ... will the system run at 66 MHz. M66EN is an input to the clock generation circuit. If M66EN is low, the clock reverts to 33 MHz. Clock Specification Table 5-8 shows the...

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... bridge hierarchy. Host -PCI Bridge Memory CPU Host Bus PCI Device PCI- PCI Bridge 1 PCI- ISA Bridge PCI- PCI Bridge 2 PCI Device PCI Device PCI Bus 0 ISA Bus PCI Bus 1 PCI Bus 2 PCI Option Card Cache Legacy Device 137 Chances ... sees the transaction. Bridge 3 passes the transaction Figure 8-5: Bus number registers. Host Bridge 0 CPU Host Bus PCI Device...

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... the rotation repeats for the next four slots. PCI Bus Demystified Figure 9 -6: Required interrupt routing. Backplane Design Rules In the course of developing the CompactPCI specification, extensive ... developing the CompactPCI spec. CompactPCI supports both 32- and 64 -bit implementations at up to 33 MHz clock frequency for the full eight slots and 66 MHz over a maximum o...

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... termination of the bus signals. CompactPCI 169 ■ Power up the slot ■ Deassert RST# and connect the slot to the bus, in either order. ■ Change the optional slot state indicator to show that the slot ... insertion event the system activates the software connection process for the inserted board. For an extraction event the system activates the PCI Bus Demystified...

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... (1) +Vio (1) 60 ACK64# REQ64# 61 +5V +5V 62 +5V +5V KEYWAY, 64 Bit Spacer 63 Reserved Gnd 64 Gnd C/BE[7] 65 C/BE [6] C/BE[5] 66 C/BE[4] +Vio (1) 67 Gnd PAR64 68 AD [63 ] AD [62 ] 69 AD [61 ] Gnd 70 +Vio ... Serial Bus (USB), 7 Vital Product Data (VPD), 111–115 VESA Local Bus, 10–11 64 –bit operation: AD [63 :32], 63 ACK64, 62 C/BE[7:4], 62 PAR64, 63 REQ64, 62 66 MH...

Ngày tải lên: 07/08/2014, 11:22

... to the problem of maintaining mission- critical systems by allowing modules to be swapped while the system is running. PCI Bus Demystified Chapter 10: Hot Plug and Hot Swap 166 PCI Hot Plug 166 Hot ... Features 56 Interrupt Handling 56 The Interrupt Acknowledge Command 59 “Special” Cycle 60 64 -bit Extensions 62 Summary 66 Chapter 5: Electrical and Mechanical Issues 67...

Ngày tải lên: 07/08/2014, 11:22