... 1-bit error 0 .51 mW 2-bit error 1.25mW Cell area 0. 251 mm2 Table 2. Performance of a high-speed and self-adaptive DEC BCH decoder 5. LDPC ECC in NAND flash memory As raw BER in NAND flash increases ... NOR Flash Memories , IEEE Trans. on Circuits and Systems II, vol .56 , no.11, pp.8 65- 869, Nov. 2009. X. Wang, D. Wu, C. Hu, et al., “Embedded High-Speed BCH Decoder for New Generation NOR Flash ... (see Figure 5) . The main purpose of the out-place scheme is to avoid block erasure during every update process. Fig. 5. The out-place updating scheme in the flash memory. Flash Memories...