The Atmel ATmega328 microcontroller is equipped with a flexible and powerful ADC system. It has the following features [Atmel]:
• 10-bit resolution
• ±2 least significant bit (LSB) absolute accuracy
• 13 ADC clock cycle conversion time
• 6 multiplexed single ended input channels
Analog reference signal
Analog input signal
Comparator
Controller Digital-to-analog converter
Serial digital output Start
Conversion
Successive-approximation converter
Figure 5.7: Successive-approximation ADC.
• Selectable right or left result justification
• 0 to Vcc ADC input voltage range
Let’s discuss each feature in turn. The first feature of discussion is “10-bit resolution.” Reso- lution is defined as:
Resolut ion = (VRH − VRL)/2b
VRH andVRLare the ADC high and low reference voltages. Whereas, “b” is the number of bits available for conversion. For the ATmega328 with reference voltages of 5 VDC, 0 VDC, and 10-bits available for conversion, resolution is 4.88 mV. Absolute accuracy specified as±2 LSB is then±9.76 mV at this resolution [Atmel].
It requires 13 analog-to-digital clock cycles to perform an ADC conversion.The ADC system may be run at a slower clock frequency than the main microcontroller clock source. The main microcontroller clock is divided down using the ADC Prescaler Select (ADPS[2:0]) bits in the ADC Control and Status Register A (ADCSRA). A slower ADC clock results in improved ADC accuracy at higher controller clock speeds.
The ADC is equipped with a single successive-approximation converter. Only a single ADC channel may be converted at a given time. The input of the ADC is equipped with an six input
analog multiplexer. The analog input for conversion is selected using the MUX[3:0] bits in the ADC Multiplexer Selection Register (ADMUX).
The 10-bit result from the conversion process is placed in the ADC Data Registers, ADCH and ADCL. These two registers provide 16 bits for the 10-bit result. The result may be left justified by setting the ADLAR (ADC Left Adjust Result) bit of the ADMUX register. Right justification is provided by clearing this bit.
The analog input voltage for conversion must be between 0 and Vcc volts. If this is not the case, external circuitry must be used to insure the analog input voltage is within these prescribed bounds as discussed earlier in the chapter.
5.5.1 BLOCK DIAGRAM
The block diagram for the ATmega328 ADC conversion system is provided in Figure5.8. The left edge of the diagram provides the external microcontroller pins to gain access to the ADC. The six analog input channels are provided at ADC[5:0] and the ADC reference voltage pins are provided at AREF and AVCC. The key features and registers of the ADC system previously discussed are included in the diagram.
5.5.2 REGISTERS
The key registers for the ADC system are shown in Figure5.9. It must be emphasized that the ADC system has many advanced capabilities that we do not discuss here. Our goal is to review the basic ADC conversion features of this powerful system. We have already discussed many of the register setting already. We will discuss each register in turn [Atmel].
5.5.2.1 ADC Multiplexer Selection Register (ADMUX)
As previously discussed, the ADMUX register contains the ADLAR bit to select left or right justification and the MUX[3:0] bits to determine which analog input will be provided to the analog- to-digital converter for conversion. To select a specific input for conversion is accomplished when a binary equivalent value is loaded into the MUX[3:0] bits. For example, to convert channel ADC7,
“0111” is loaded into the ADMUX register. This may be accomplished using the following C instruction:
ADMUX = 0x07;
The REFS[1:0] bits of the ADMUX register are also used to determine the reference voltage source for the ADC system. These bits may be set to the following values:
• REFS[0:0] = 00: AREF used for ADC voltage reference
• REFS[0:1] = 01: AVCC with external capacitor at the AREF pin
• REFS[1:0] = 10: Reserved
Figure 5.8: Atmel AVR ATmega328 ADC block diagram. (Figure used with permission of Atmel, Incorporated.)
ADC Multiplexer Selection Register - ADMUX
7 0
7 0
7 0
ADC Data Register - ADCH and ADCL (ADLAR = 0)
15 8
ADCH ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
ADC9 ADC8
--- --- --- --- --- ---
REFS1 REFS0 ADLAR --- MUX3 MUX2 MUX1 MUX0 ADC Control and Status Register A - ADCSRA
ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0
7 0
ADC Data Register - ADCH and ADCL (ADLAR = 1)
15 8
ADCH ADCL
ADC7 ADC6 ADC5 ADC4 ADC3 ADC2
ADC1 ADC0
ADC9 ADC8
--- --- --- --- --- ---
Figure 5.9: ADC Registers. Adapted from Atmel.
• REFS[1:1] = 11: Internal 1.1 VDC voltage reference with an external capacitor at the AREF pin
5.5.2.2 ADC Control and Status Register A (ADCSRA)
The ADCSRA register contains the ADC Enable (ADEN) bit. This bit is the “on/off ” switch for the ADC system. The ADC is turned on by setting this bit to a logic one. The ADC Start Conversion (ADSC) bit is also contained in the ADCSRA register. Setting this bit to logic one initiates an ADC. The ADCSRA register also contains the ADC Interrupt flag (ADIF) bit. This bit sets to logic one when the ADC is complete. The ADIF bit is reset by writing a logic one to this bit.
The ADC Prescaler Select (ADPS[2:0]) bits are used to set the ADC clock frequency. The ADC clock is derived from dividing down the main microcontroller clock. The ADPS[2:0] may be set to the following values:
• ADPS[2:0] = 000: division factor 2
• ADPS[2:0] = 001: division factor 2
• ADPS[2:0] = 010: division factor 4
• ADPS[2:0] = 011: division factor 8
• ADPS[2:0] = 100: division factor 16
• ADPS[2:0] = 101: division factor 32
• ADPS[2:0] = 110: division factor 64
• ADPS[2:0] = 111: division factor 128 5.5.2.3 ADC Data Registers (ADCH, ADCL)
As previously discussed, the ADC Data Register contains the result of the ADC. The results may be left (ADLAR=1) or right (ADLAR=0) justified.