- Thiết kế mạch d_fipflop tích cực sườn lên , không có reset - Sử dụng khối always @*
- Đầu vào là clk ,d - Đầu ra là q
- Dut
+ module
+)Module: reg_file -Yêu cầu
-DUT Code:
module reg_file #(
parameter B=8, W=2
) (
input wire clk, input wire wr_en,
input wire [W-1:0] w_addr, r_addr, input wire [B-1:0] w_data,
output wire [B-1:0] r_data );
reg [B-1:0] array_reg [2**W-1:0];
always @(posedge clk) if(wr_en)
array_reg[w_addr] <= w_data;
assign r_data = array_reg[r_addr];
endmodule + Testbench :
`timescale 1 ps/ 1 ps module tb_reg_file();
reg eachvec;
reg clk;
reg [1:0] r_addr;
reg [1:0] w_addr;
reg [7:0] w_data;
reg wr_en;
wire [7:0] r_data;
reg_file i1 (
.clk(clk),
.r_addr(r_addr), .r_data(r_data), .w_addr(w_addr),
.w_data(w_data), .wr_en(wr_en) );
initial begin
clk=0; wr_en=0;w_addr=2'd1;r_addr=2'd2;w_data=2'd5;
#10 wr_en=1;
$display("Running testbench");
end
always #5 clk=~clk;
always #5 w_addr=w_addr+1;
//always #5 wr_en=wr_en+1;
always #5 r_addr=r_addr+1 ; always #5 w_data=w_data+1;
always // optional sensitivity list // @(event1 or event2 or .... eventn) begin
// code executes for every event on sensitivity list // insert code here --> begin
@eachvec;
// --> end end endmodule
Mô phỏng
3.2 Thiết kế mạch Free-run-shif-reg.
Code:
module free_run_shift_reg1
#(parameter N=8) ( input wire clk, reset, input wire s_in, output wire s_out, output wire [N-1:0] q, output reg [N-1:0] r_reg, output wire [N-1:0] r_next );
// reg [N-1:0] r_reg;
//wire [N-1:0] r_next;
always @(posedge clk, posedge reset) if (reset)
r_reg <=0;
else
r_reg <= r_next;
assign r_next = {s_in , r_reg [N-1: 1]};
assign q=r_reg;
assign s_out = r_reg[0];
endmodule
TestBench : `timescale 1 ps/ 1 ps
module free_run_shift_reg1_vlg_tst();
// constants // general purpose registers
reg eachvec;
// test vector input registers reg clk;
reg reset;
reg s_in;
// wires wire [7:0] q;
wire s_out;
// assign statements (if any) free_run_shift_reg1 i1 (
// port map - connection between master ports and signals/registers .clk(clk),
.q(q),
.reset(reset), .s_in(s_in), .s_out(s_out) );
initial begin clk=1;
forever #5 clk=~clk;
end
initial begin
#5 reset=1;
#15 reset=0; s_in=1;
$display("Running testbench");
end always // optional sensitivity list // @(event1 or event2 or .... eventn) begin
// code executes for every event on sensitivity list // insert code here --> begin
@eachvec;
// --> end end
endmodule
Mô phỏng
3.3 Thiết kế mạch univ-shift-reg
-Code
module univ_shift_reg #(parameter N=8) ( input wire clk, reset, input wire [1:0] ctrl, input wire [N-1:0] d, output wire [N-1:0] q );
reg [N-1:0] r_reg, r_next;
always @(posedge clk, posedge reset) if (reset)
r_reg <= 0;
else
r_reg <= r_next;
always @*
case (ctrl)
2'b00: r_next = r_reg;
2'b01: r_next = {r_reg[N-2:0], d[0]};
2'b10: r_next = {d[N-1],r_reg[N-1:1]};
default: r_next = d;
endcase
assign q = r_reg;
endmodule TestBench
module tb_univ_shift_reg();
parameter N=8;
reg clk,reset;
reg [1:0] ctrl;
reg [N-1:0] d;
wire [N-1:0] q;
reg [N-1:0] r_reg, r_next;
univ_shift_reg dut( .q(q), .d(d), .ctrl(ctrl), .clk(clk), .reset(reset));
initial begin
clk=0; reset=0;ctrl=2'b00;
d=8'b00000000;
r_reg =8'b11110000;
r_next=8'b10101000;
end
initial forever #5 clk=~clk;
initial forever #10 reset=~reset;
initial forever #15 ctrl=ctrl+1;
initial forever #60 d=d+1;
endmodule
Mô Phỏng
3.4. Thiết kế mạch Free-run-bin-counter Code
module free_run_bin_counter
#( parameter N=8) (
input wire clk, reset, output wire max_tick, output wire [N-1:0] q );
reg [N-1:0] r_reg;
wire [N-1: 0] r_next ;
always @(posedge clk, posedge reset) if (reset)
r_reg <= 0 ; // {N{lb 'O}}
else
r_reg <= r_next;
assign r_next = r_reg + 1;
assign q = r_reg;
assign max_tick = (r_reg==2**N-1) ? 1'b1 : 1'b0;
endmodule
TestBench
`timescale 1 ps/ 1 ps
module free_run_bin_counter_vlg_tst();
// constants // general purpose registers
reg eachvec;
// test vector input registers reg clk;
reg reset;
// wires wire max_tick;
wire [7:0] q;
// assign statements (if any) free_run_bin_counter i1 (
// port map - connection between master ports and signals/registers .clk(clk),
.max_tick(max_tick), .q(q),
.reset(reset) );
initial begin
clk =0;
forever #5 clk=~clk;
end
initial begin
reset=1;
#20 reset=0;
// code that executes only once // insert code here --> begin
// --> end
$display("Running testbench");
end always // optional sensitivity list // @(event1 or event2 or .... eventn) begin
// code executes for every event on sensitivity list // insert code here --> begin
@eachvec;
// --> end end
endmodule Mô phỏng
3.4 Thiết kế mạch univ-bin-counter.
Code
module univ_bin_counter
#(parameter N=8) (
input wire clk, reset,
input wire syn_clr , load, en, up, input wire [N-1:0] d,
output wire max_tick, min_tick, output wire [N-1:0] q
);
reg [N-1:0] r_reg, r_next;
always @(posedge clk, posedge reset) if (reset)
r_reg <= 0;
else
r_reg <= r_next;
always @*
if (syn_clr) r_next = 0;
else if (load) r_next = d ; else if (en & up) r_next = r_reg + 1;
else if(en & ~up) r_next = r_reg - 1;
else
r_next = r_reg;
assign q = r_reg;
assign max_tick = (r_reg==2**N-1) ? 1'b1 : 1'b0;
assign min_tick = (r_reg==0) ? 1'b1 : 1'b0;
endmodule
+) TestBench `timescale 1 ps/ 1 ps
module univ_bin_counter_vlg_tst();
// constants // general purpose registers
reg eachvec;
// test vector input registers reg clk;
reg [7:0] d;
reg en;
reg load;
reg reset;
reg syn_clr;
reg up;
// wires wire max_tick;
wire min_tick;
wire [7:0] q;
// assign statements (if any) univ_bin_counter i1 (
// port map - connection between master ports and signals/registers .clk(clk),
.d(d), .en(en), .load(load),
.max_tick(max_tick), .min_tick(min_tick), .q(q),
.reset(reset), .syn_clr(syn_clr), .up(up)
);
initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;d=8'b0;en=0;load=1;up=0;syn_clr=1;
#20 reset=0; syn_clr=0;load=0;
// code that executes only once // insert code here --> begin
// --> end
$display("Running testbench");
end always #5 d=d+1;
always #15 en=en+1;
//always #10 load=load+1;
always #20 up=up+1;
always // optional sensitivity list // @(event1 or event2 or .... eventn) begin
// code executes for every event on sensitivity list // insert code here --> begin
@eachvec;
// --> end end
endmodule
Mô Phỏng
3.5 Thiết kế mạch mod-m-counter.
Code
module mod_m_counter
# (
parameter N=4, // number of b i t s in c o u n t e r M=10 // mod-M
) (
input wire clk, reset, output wire max_tick, output wire [N-1:0] q ) ;
reg [N-1:0] r_reg;
wire [N-1:0] r_next ;
always @ ( posedge clk , posedge reset ) if (reset)
r_reg <= 0 ; else
r_reg <= r_next;
assign r_next = (r_reg==(M-1)) ? 0 : r_reg + 1;
assign q = r_reg;
assign max_tick = (r_reg==(M-1)) ? 1'b1 : 1'b0;
endmodule
TestBench
module tmod_m_counter;
reg clk, rst;
wire max_tick;
wire [3:0] q;
mod_m_counter #(4, 10) dut(q, max_tick, clk, rst);
always begin clk = 1'b0;
#2 clk = 1'b1;
#2;
end
initial begin rst = 1'b1;
#5 rst = 1'b0;
end