4.3 FEEDBACK DEMODULATORS: THE PHASE-LOCKED LOOP
4.3.3 Phase-Locked Loop Operation in the Acquisition Mode
In the acquisition mode we must determine that the PLL actually achieves phase lock and the time required for the PLL to achieve phase lock. In order to show that the phase error signal tends to drive the PLL into lock, we will simplify the analysis by assuming a first-order PLL for which the loop filter transfer function𝐹 (𝑠) = 1or𝑓(𝑡) = 𝛿(𝑡). Simulation will be used for higher-order loops. Using the general nonlinear model defined by (4.102) withℎ(𝑡) = 𝛿(𝑡)and applying the sifting property of the delta function yields
𝜃(𝑡) = 𝐾𝑡∫
𝑡sin[𝜙(𝛼) − 𝜃(𝛼)]𝑑𝛼 (4.141)
Taking the derivative of𝜃(𝑡)gives 𝑑𝜃
𝑑𝑡 = 𝐾𝑡sin[𝜙(𝑡) − 𝜃(𝑡)] (4.142)
ψ ψ
ψ
∆ω
∆ω +Kt
∆ω–Kt ss d /dt
A B
Figure 4.22
Phase-plane plot for sinusoidal nonlinearity.
Assume that the input to the FM modulator is a unit step so that the frequency deviation𝑑𝜙∕𝑑𝑡 is a unit step of magnitude2𝜋Δ𝑓 = Δ𝜔. Let the phase error𝜙(𝑡) − 𝜃(𝑡)be denoted𝜓(𝑡). This yields
𝑑𝜃 𝑑𝑡 = 𝑑𝜙
𝑑𝑡 − 𝑑𝜓
𝑑𝑡 = Δ𝜔 −𝑑𝜓
𝑑𝑡 = 𝐾𝑡sin 𝜓(𝑡), 𝑡≥0 (4.143) or
𝑑𝜓
𝑑𝑡 + 𝐾𝑡sin 𝜓(𝑡) = Δ𝜔 (4.144)
This equation is shown in Figure 4.22. It relates the frequency error and the phase error and is known as a phase plane.
The phase plane tells us much about the operation of a nonlinear system. The PLL must operate with a phase error𝜓(𝑡)and a frequency error𝑑𝜓∕𝑑𝑡that are consistent with (4.144).
To demonstrate that the PLL achieves lock, assume that the PLL is operating with zero phase and frequency error prior to the application of the frequency step. When the step in frequency is applied, the frequency error becomesΔ𝜔. This establishes the initial operating point, point 𝐵in Figure 4.22, assumingΔ𝜔 > 0. In order to determine the trajectory of the operating point, we need only recognize that since𝑑𝑡, a time increment, is always a positive quantity,𝑑𝜓must be positive if𝑑𝜓∕𝑑𝑡is positive. Thus, in the upper half plane𝜓 increases. In other words, the operating point moves from left-to-right in the upper half plane. In the same manner, the operating point moves from right-to-left in the lower half plane, the region for which 𝑑𝜓∕𝑑𝑡is less than zero. Thus, the operating point must move from point𝐵to point𝐴. When the operating point attempts to move from point𝐴by a small amount, it is forced back to point𝐴. Thus, point𝐴is a stable operating point and is the steady-state operating point of the system. The steady-state phase error is𝜓𝑠𝑠, and the steady-state frequency error is zero as shown.
The preceding analysis illustrates that the loop locks only if there is an intersection of the operating curve with the𝑑𝜓∕𝑑𝑡 = 0axis. Thus, if the loop is to lock,Δ𝜔must be less than 𝐾𝑡. For this reason,𝐾𝑡is known as thelock range for the first-order PLL.
The phase-plane plot for a first-order PLL with a frequency-step input is illustrated in Figure 4.23. The loop gain is 2𝜋(50), and four values for the frequency step are shown:
Δ𝑓 = 12, 24, 48, and 55 Hz. The steady-state phase errors are indicated by𝐴, 𝐵, and𝐶 for frequency-step values of 12, 24, and 48 Hz, respectively. ForΔ𝑓 = 55, the loop does not lock but forever oscillates.
A mathematical development of the phase-plane plot of a second-order PLL is well beyond the level of our treatment here. However, the phase-plane plot is easily obtained, using
120 108 96 84 72 60 48 36 24 12 0
0 A B C π 2π
Phase error, radians
Frequency error, Hz
Figure 4.23
Phase-plane plot for first-order PLL for several step function frequency errors.
computer simulation. For illustrative purposes, assume a second-order PLL having a damping factor𝜁 of 0.707 and a natural frequency𝑓𝑛of 10 Hz. For these parameters, the loop gain 𝐾𝑡 is 88.9, and the filter parameter𝑎is 44.4. The input to the PLL is assumed to be a step change in frequency at time𝑡 = 𝑡0. Four values were used for the step change in frequency Δ𝜔 = 2𝜋(Δ𝑓). These wereΔ𝑓 = 20, 35, 40, and 45 Hz.
The results are illustrated in Figure 4.24. Note that forΔ𝑓 = 20Hz, the operating point returns to a steady-state value for which the frequency and phase error are both zero, as should be the case from Table 4.4. For Δ𝑓 = 35 Hz, the phase plane is somewhat more complicated. The steady-state frequency error is zero, but the steady-state phase error is
80
60
40
20
−20 0 0
2π 4π 6
Phase error, radians
π 8π 10π
∆ f = 35 Hz
∆ f = 20 Hz
f = 40 Hz
∆ f = 45 Hz
Frequency error, Hz
∆
Figure 4.24
Phase-plane plot for second-order PLL for several step function frequency errors.
2𝜋 rad. We say that the PLL has slipped one cycle. Note that the steady-state error is zero mod(2𝜋). The cycle-slipping phenomenon accounts for the nonzero steady-state phase error.
The responses forΔ𝑓 = 40and 45 Hz illustrate that three and four cycles are slipped, respec- tively. The instantaneous VCO frequency is shown in Figure 4.24 for these four cases. The cycle-slipping behavior is clearly shown. The second-order PLL does indeed have an infinite lock range, and cycle slipping occurs until the phase error is within𝜋rad of the steady-state value.
COMPUTER EXAMPLE 4.4
A simulation program is easily developed for the PLL. We simply replace the continuous-time integrators by appropriate discrete-time integrators. Many different discrete-time integrators exist, all of which are approximations to the continuous-time integrators. Here we consider only the trapesoidal approximation.
Two integration routines are required; one for the loop filter and one for the VCO. The trapezoidal approximation is
y[n] = y[n-1] + (T/2)[x[n] + x[n-1]]
wherey[n]represents the current output of the integrator,y[n-1]represents the previous integrator output,x[n]represents the current integrator input,x[n-1]represents the previous integrator input, andTrepresents the simulation step size, which is the reciprocal of the sampling frequency. The values ofy[n-1]andx[n-1]must be initialized prior to entering the simulation loop. Initializing the integrator inputs and outputs usually result in a transient response. The parameternsettle, which in the simulation program to follow, is set equal to 10% of the simulation run length, allows any initial transients to decay to negligible values prior to applying the loop input. The following simulation program is divided into three parts. The preprocessor defines the system parameters, the system input, and the parameters necessary for execution of the simulation, such as the sampling frequency. The simulation loop actually performs the simulation. Finally, the postprocessor allows for the data generated by the simulation to be displayed in a manner convenient for interpretation by the simulation user. Note that the postprocessor used here is interactive in that a menu is displayed and the simulation user can execute postprocessor commands without typing them. The simulation program given here assumes a frequency step on the loop input and can therefore be used to generate Figures 4.24 and 4.25.
%File: c4ce4.m
%beginning of preprocessor
clear all %be safe
fdel = input(‘Enter frequency step size in Hz > ’);
n = input(‘Enter the loop natural frequency in Hz > ’);
zeta = input(‘Enter zeta (loop damping factor) > ’);
npts = 2000; %default number of simulation points
fs = 2000; %default sampling frequency
T = 1/fs;
t = (0:(npts-1))/fs; %time vector
nsettle = fix(npts/10) %set nsettle time as 0.1*npts Kt = 4*pi*zeta*fn; %loop gain
a = pi*fn/zeta; %loop filter parameter filt in last = 0; filt out last=0;
vco in last = 0; vco out = 0; vco out last=0;
%end of preprocessor
%beginning of simulation loop for i=1:npts
if i < nsettle
80 70 60 50 40 30 20 10 –10
Time (a) –20 t0
0
VCO frequency
80 70 60 50 40 30 20 10 –10
Time (b) –20 t0
0
VCO frequency
80 70 60 50 40 30 20 10 –10
Time (c) –20 t0
0
VCO frequency
80 70 60 50 40 30 20 10 –10
Time (d) –20 t0
0
VCO frequency
Figure 4.25
Voltage-controlled frequency for four values of the input frequency step. (a) VCO frequency for Δ𝑓 = 20Hz. (b) VCO frequency forΔ𝑓 = 35Hz. (c) VCO frequency forΔ𝑓 = 40Hz. (d) VCO frequency forΔ𝑓 = 45Hz.
fin(i) = 0;
phin = 0;
else
fin(i) = fdel;
phin = 2*pi*fdel*T*(i-nsettle);
end
s1=phin - vco out;
s2=sin(s1); %sinusoidal phase detector s3=Kt*s2;
filt in = a*s3;
filt out = filt out last + (T/2)*(filt in + filt in last);
filt in last = filt in;
filt out last = filt out;
vco in = s3 + filt out;
vco out = vco out last + (T/2)*(vco in + vco in last);
vco in last = vco in;
vco out last = vco out;
phierror(i)=s1;
fvco(i)=vco in/(2*pi);
freqerror(i) = fin(i)-fvco(i);
end
%end of simulation loop
%beginning of postprocessor
kk = 0;
while kk == 0
k = menu(‘Phase Lock Loop Postprocessor’,...
‘Input Frequency and VCO Frequency’,...
‘Phase Plane Plot’,...
‘Exit Program’);
if k == 1
plot(t,fin,t,fvco)
title(‘Input Frequency and VCO Frequency’) xlabel(‘Time - Seconds’)
ylabel(‘Frequency - Hertz’) pause
elseif k == 2
plot(phierror/2/pi,freqerror) title(‘Phase Plane’)
xlabel(‘Phase Error / pi’) ylabel(‘Frequency Error - Hz’) pause
elseif k == 3 kk = 1;
end end
%end of postprocessor
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