Phong e:."teh 1116 t:.t kie'll truc th6ng lJua c:lu tr(ie x,ie d.illh call true eua thue th~ ~U' d~l11g e:le khai 0,10 ella c:."te pldn tt! thlll1h ph[ill \'il cae phicn b,111 eua cae phiin tu thill1h phan. Cue mel hi cau true eh{ra danh ",:.\.ch eae philll tu
hO<)t d<)ng c[{)ng thoi Vi:l licll ket giil"a ule ph:ln tu do, Vi Ul,J, khi ta m6 1<"1 C:'\U truc cua m<wh c<)ng m(ll bit FULL_ADDER. M:'.lch feLL_ADDER dti'(/e Ihi6"1 ke tren co' s('j c:te thLll1h pllan Ii:I HALf< _ADDER viI OR_GATE. Clu true dlfl/e thie't he' ella m:.lch e~)ng I1H)t oit chua hai m:.lch nt'ra tong \'il llH)t phiin tU'logie eo ball l~l OICGalc, C.i.c phiin tu nily licn kc"t voi nhau btmg e.:ie tin hicu. I~ '0 ~N3 HA2 Sum ~ -. - - > - i c '"
Il"Ilih 6.N CIU In.k (', lillIe kitn (nk ell~l
m;.lch C011i! 1l1(1( bit ell<! h,1I till hitu.
architecture STRUCTURE of f<ULL ADDER is
component IIALF _ADDER
}lort ( L ILl: in BIT; Carry,Sum : out BIT );
end compunent: compunent OR_GATE
hegin
port ( LJ. L2: in nIT; 0: uut IllT ):
end component signal N l,N2.N3 : BIT;
HA I : HALF_ADDER port map ( A, 13, N L 1\2 ); HA2: HALP _ADDER port map ( N2. Cin. N3. Sum ): ORI : OICC;ATE port map (NL N3. Cout):
end STRUCfURE;
Khi d(l phlie li.\P ella thie"1 ke' lang iC:n. ni1a thiet ke tlllIong ph[m Uieh h¢ th6ng th~l!lh nhung h¢ thong con. eie h¢ Ih6ng con Ilay li~n kc"t ch(lt ehe theo ehCre n[lllg lrong thanh phiin eua h¢ thong t6ng the. Moi h¢ thong con le.ti Cl) th(~ dtfqe pilan tach thimh nhu'ng phan h¢ 6 111ue th,rp h<Jn niJa. Trong ngoll ngu' VHDL o' mCfe eao nh:;t eua Ihie"t ke nguai la slf dl;lIlg m6 hinh kicn tnk theo ['hong deh du true eua tlWe Ih~. Ciu true nay se g01l1 t;)p hqp phi":n lxin eua de ['him h~ ke"! noi v0i nhau bang de dU'ung Illl hi¢u.
Moi phien bi111 ella Ih;'lllh phiin mi.lCh du\l"C m6 t.i b,\ng de h(lp den trong hicu lhell e[iu true \"(5i e<.te licil klYt cUu v;:\O V~I lien kc"! (bu ra du"U"c 1116 Iii ro rimt-!. eic phien IX"1ll thilnil ph:in ph.-li lUang thfch \'6i e.te t1We th':. Cic time the ni\y -.;0 mi.) lei de chu'e nimg eua Ih~lJ1h plliln mach btmg cae mil hlllh ki61 Iruc theo bi':u dl~n e{lu Irue hO(1( h~lllh vi. Vi du, d6i \"()'i m<..\Ch u)ng m(ll bit ella hili tin iliell. ta co m'.leh eQng "i,: dU"eJe X[IY dvng tu Iwi 1n'.lCh !lila tClng "il In(lt phrin tu OR. Khi d6 theo de m() 1,\ kicn true ella cae Ihve the bang e.ie m(l t,i cAu true. thve the H;LL_ADDER c1uqe t,.\O b()'i hili lime the HALf_ADDER V~I lll(lt tlH.re the Ol-COATE. Trong d{l tlwc til': HALF_ADDER co the c1w;/C xtty dL.rng til cae philn tu XOR V~l AND.
\IJ{) t.l th~re th~ HALf_ADDER theo cflu Irue tu de rlltin Ill" AND "i\
XDR,
entity HALf_ADDER is
purt ( 10, I I : in BIT: S, CO : out IllT ); end HALf-_ ADDER;
an:hitecturc STRUCTURE of HALf_ADDER is
component XOR_GATE
begin
end component
component Al'!D2_GATE
purt ( 10. II , in IllT; 0; uut lllT ); end component:
U L XOICGATE port map ( Ill. I I. S ); \]2, AND2JiATE port map (IO.lI. CO); end STRUC[URE;
Moi thimh ph.'in cua tlwc the' neu tren co the xu)' dl!ng tu cae th~rc the kh,\c m6 1,'1 de chue nang ella cluing. Vi dl,l phiin tt'r XOR_.GATE etl the dll'9\: m6 t:1 theo h:mh vi nh\1 sau.
entity XOR-GATE~
port ( 10. 1\ , in BIT; S. CO ; out fliT ); end XOR_GATE;
architecture BEHAVIOR of XOR_GATE is hcgin
0<= 10 xor 1\ arfer \0 ns: end BEflA Y[OR;
Bicu dicn e:'lu true cua Gte phii.ll cap thiel 1<.6 <'mh hu'ong tai qua trlnh phan tach thiet kc·. Di6u n£1.),' XUi!1 phat tu e{le d~tc diem ella b~ Ih6ng ctlfl)'e thiet kc. 6 tn('11 tnue phan dlp b[il
k)l, h~ thong c1u'ge dlu t'.IO bdi de lien ke't ella nhCrng Ih111lh phfin 6 mue dang xc\. Bi6u elien cUu true ella kicn true ehu'a danh siich cae h('1p (kn. 6 Illt:l'e thfip nh[it ella qu,i trlnh phall t{lch. ta ph:li 1110 la h:l1lh vi Clla cae ph fin It'r nam trang thiet kc c'5 muc nay. Qm\. Irlnh phan cap co the bieu oien dU'oi d'.ll1g cay phan
.~
,
M6 hinh hoa hanh vi
Hinh 6.9 ely p\l,ln dp L"~U dlC11 kic'n Inle ella JllO hl11h tl11CI kt'.
c:t'p ( hinh 5.9 ). T'.li mue Ihap nhfit ella phan cap, ta phli 1116 hi hi1l1h vi ella cae th~t'e the thea trinh tl! ma 1116 hinh lTIi.ICh ,..,e dU\1C mo ph('mg.
3. Cae g6i thiet kc
M~le dfch ehfnh ella cae g<11 la 1(lp h\1p cae phan tll' C<1 the dllllg chung giiJa hal llOZIC nhicu c10n vi thiel kc. Mt)t goi bao gom hai th~ll1h phan: ph{in khai h,io goi va ph[in Ih[lll goi.
Ph[in khai bao g6i chua tXt ca cac khai hao cua mqi tcn. (\;"hLrng len nily .'ie dm/c cae don vi thiet kc dung den khi SLf dung g6i. Tht'mg tlnii'mg: ph[\n khai h<'lo chua m(lt so ki~u clt11i¢u chung, ceie ht1ng \"~11ll6 1;1 ella dc chVtmg tdnb COil.
Ph:ill lh,tn gai baa gom eac ph,ill th,in CU<.I cac cilu'tmg trlnh CO])
ilia t,i trong ph[in khai hao goi. Phan thfm n~IY 1~1 :in d6i \'oi hen ngo~li. Phi\n than ella goi khong bftt hut)c ph,li co n6u khong e(l ehvOIlg trlllh con dU\1C 1116 1:1 trong g(li.
Vi cll.t, ta co khai bao g6i nhu sau. Cioi nay khaJ hilO 111~'it StS ki~u. hic'n, h,lng V,I chunng trinh con.
pllckage EX_PKG is
subtype INT8 is INTEGER range 0 to 255 constant ?ERO : INT8 :=0 :
(.'onstant MAX : INT8 := 100;
procedure Increemcnt ( variable count: inout Il'\T8 ) end EX-PKG.
Do trong khai h'\.o co thu lL.lc Inen:cll1cnt nell 1<1 dn phili e6 th{lll ellil g()i tuong ling v6i khaJ hilO ~oi trcn.
package body EX-PKU is
procedure lnercemcnt ( v41riable Dala: inout INT8 ) is begin
end if
if ( Count >= MAX) then Count := ZERO: else
Count := Coullt + 1· end Incrccm..:nt;
4. C{lC cau hlnh
M{)t tlwe the co the: co mot Y(li kicn tnk. Trong qu,i trlnh thle"1 k0", la co the" dn phai Iht1 nghi¢m llH)1 \"ll.i bicn the elld Ihict kc btmg deh slr d~ll1g «te
kien true kh{le nhau. Ciu hinh 1& thtmh phtin cd b:m ella dan V! thiet kl:". elll hlnh eho phep gtm de phien ban eua thl!C the yito nhCrng kicn Ink kh,\c nhau. Glu hlnh el"mg eo the duc.~e Sli" dung de thay the" me)t deh nhanh ch6ng de ph;\n Ill' ella thlle the trong bicu Jicn cau trlK ella thic"t kc'.
CU ph,ip ella 1116 ta eAu 1Il11h:
C()nfi~unltion '(;/I_cditldll/l of f(;/I_1Iu/C_lh(;"is
\ pltci"ll_ khoi -'h/O _Clio _ uilt-'u'nh \
fOI' title ,(/ oi(l kh()"i
\ m(lIlr_d(use I
{ ((ic_pllltll 1/1 (11(1 C{]II-'Iillh I
end for;
Vi tu pillin Jlul/Ju/o _ Clia __ c(/'lI_hillil eho phep du hlnh Slr dl!ng de phfil1 tll trong de goi vii de tlnl'vicn.
Vi tv dlk rd Cli(/JI/()I" X<.lc d(nh cau hioh eho hin Irl\C eoa Ihue Ih~. Vi d~1
Configuration FADD_CONFIG of FULL_ADDER is [or STRUCHJRE
for HAl. HAL HALF_ADDER
use entity WORK.HALF _ADDER(STRlICTURE)
[or ORI: OR_GATE usc entity WORK.lJRJiATE;
end for
end FADD_CONFIG; hung cau hlnh nay, chung ta thay:
STRUcnJRE ehi to'i kien true eoa thl!c Ih6 FULL_ADDER dUde (Ut cau hlnh.
HA 1 V:l HAl: Iii cae t1we the gan voi thl!C the HALF _ADER ella kicn tn.k STRUCTURE Hong thu \'i~n WORK.