cisc and risc in computer organization and architecture

... operand is included in the instruction Address of operand is included in the instruction Operand is in a memory location whose address is in the register specified in the instruction Operand is in ... book is intended for students in computer engineering, computer science, and electrical engineering The material covered in the book is suitable for a onesemester course on Computer Organization ... addressing the issue of storing and retrieving information into and from memory, followed by a discussion on a number of different addressing modes We also explain instruction execution and sequencing...

Ngày tải lên: 19/09/2013, 15:53

... identify the module issuing the interrupt? § How you deal with multiple interrupts? • i.e an interrupt handler being interrupted Identifying Interrupting Module (1) § Different line for each module ... IRQ7 8086 INTR ISA Bus Interrupt System § ISA bus chains two 8259As together § Link is via interrupt § Gives 15 lines • 16 lines less one for link § IRQ is used to re-route anything trying to use ... module in turn • Slow • Priority is established by the order in which module are polled Identifying Interrupting Module (2) § Daisy Chain or Hardware poll • Interrupt Acknowledge sent down a chain...

Ngày tải lên: 05/11/2013, 22:15

... re-linking and re-loading § Lends itself to sharing among processes § Lends itself to protection § Some systems combine segmentation with paging Required Reading § Stallings chapter § Stallings, ... Error detection and response Accounting O/S as a Resource Manager Types of Operating System § § § § Interactive Batch Single program (Uni-programming) Multi-programming (Multi-tasking) Early Systems ... I/O § Interrupts • Allows for relinquishing and regaining control Multi-programmed Batch Systems § I/O devices very slow § When one program is waiting for I/O, another can use the CPU Single...

Ngày tải lên: 12/12/2013, 09:15

... Moterola 680x0 (Mac), and most RISC are big-endian § Internet is big-endian • Makes writing Internet programs on PC more awkward! • WinSock provides htoi and itoh (Host to Internet & Internet to Host) ... Divide Signed Integer Floating point ? May include • Increment (a++) • Decrement (a ) • Negate (-a) Logical § Bitwise operations § AND, OR, NOT Conversion § E.g Binary to Decimal Input/Output ... arbitrary binary contents Integer - single binary value Ordinal - unsigned integer Unpacked BCD - One digit per byte Packed BCD - BCD digits per byte Near Pointer - 32 bit offset within segment...

Ngày tải lên: 12/12/2013, 09:15

... to find operand § Hence slower Indirect Addressing Diagram Instruction Opcode Address A Memory Pointer to operand Operand Register Addressing (1) § § § § § Operand is held in register named in ... Operand Indirect Addressing (1) § Memory cell pointed to by address field contains the address of (pointer to) the operand § EA = (A) • Look in A, find address (A) and look there for operand ... programming or compiler writing • N.B C programming ü register int a; § c.f Direct addressing § § § § Register Addressing Diagram Instruction Opcode Register Address R Registers Operand Register Indirect...

Ngày tải lên: 12/12/2013, 09:15

... loaded with address of interrupt handling routine Next instruction (first of interrupt handler) can be fetched Data Flow (Interrupt Diagram) Prefetch § § § § Fetch accessing main memory Execution ... instruction Decode instruction Calculate operands (i.e EAs) Fetch operands Execute instructions Write result § Overlap these operations Timing of Pipeline Branch in a Pipeline Dealing with Branches ... pointing to: • Process control blocks (see O/S) • Interrupt Vectors (see O/S) § N.B CPU design and operating system design are closely linked Example Register Organizations Foreground Reading...

Ngày tải lên: 12/12/2013, 09:15

... points Example of supporting line for two convex hulls Partitioning a set of points using four extreme points Angles among points and the Points in labeled with Illustration of contact points and ... Proximity indexing Euler tour of a tree Preorder-inorder traversal Merging preorder and inorder traversals Finding distances in a directed graph List ranking with a balanced subset Embedding a list in ... configuration and graph Broadcasting on an R-Mesh Permutation routing Adding bits addition on an R-Mesh Examples of and Neighbor localization example Chain sorting Concatenating lists in chain sorting...

Ngày tải lên: 01/06/2014, 07:46

... Network Outline of the Book (1) • • • • • • • • Computer Evolution and Performance Computer Interconnection Structures Internal Memory External Memory Input/Output Operating Systems Support Computer ... CPU CPU Computer Arithmetic and Login Unit Registers I/O System Bus Memory CPU Internal CPU Interconnection Control Unit Structure - The Control Unit Control Unit CPU Sequencing Login ALU Internal ... smart devices or other computers Control • Something needs to monitor operation and maintain control of data processing, data storage, and data movement • Automated control of computer s resources...

Ngày tải lên: 02/07/2014, 04:21

... http://www.di.uminho.pt William Stallings, “ Computer Organization and Architecture 5th Ed., 2000 , § Increasing Speed § Increasing Number of I/O Ports § Increasing Memory Size § Increasing Cost § ... computer components, to the increasing use of parallel organization concepts in combining those components In spite of the variety and pace of change in the computer field, certain fundamental concepts ... http://www.shore.net/~ws PROJECTS FOR TEACHING COMPUTER ORGANIZATION AND ARCHITECTURE For many instructors, an important component of a computer organization and architecture course is a project or...

Ngày tải lên: 14/08/2014, 14:20

... Pins - includes clock and reset § Address and Data Pins - 32 time-multiplexed lines for addresses and data, plus lines to interpret and validate these § Interface Control Pins - control timing ... interrupt handler routine • Multiple interrupts o Can be handled by disabling some or all interrupts Disabled interrupts generally remain pending and are handled sequentially o Can be handled by ... line: polling - when line goes high, CPU polls devices to determine which caused interrupt § Multiple lines: addressable interrupts - combination of lines indicates both interrupt and which device...

Ngày tải lên: 14/08/2014, 14:20

... Cache Main Memory Cache Registers Universidade Minho – Dep Informática - Campus de Gualtar – 4710-057 Braga - PORTUGAL- http://www.di.uminho.pt William Stallings, “ Computer Organization and Architecture ... Universidade Minho – Dep Informática - Campus de Gualtar – 4710-057 Braga - PORTUGAL- http://www.di.uminho.pt William Stallings, “ Computer Organization and Architecture 5th Ed., 2000 , § Inversely proportional ... updateable in place - writing uses ordinary bus control, address, and data lines Universidade Minho – Dep Informática - Campus de Gualtar – 4710-057 Braga - PORTUGAL- http://www.di.uminho.pt William...

Ngày tải lên: 14/08/2014, 14:20

... line can be in one of states: § Modified - The line in the cache has been modified and is available only in this cache § Exclusive - The line in the cache is the same as that in main memory and ... not present in any other cache § Shared - The line in the cache is the same as that in main memory and may be present in another cache § Invalid - The line in the cache dopes not contain valid data ... Universidade Minho – Dep Informática - Campus de Gualtar – 4710-057 Braga - PORTUGAL- http://www.di.uminho.pt William Stallings, “ Computer Organization and Architecture 5th Ed., 2000 , II THE COMPUTER...

Ngày tải lên: 14/08/2014, 14:20

... ACK’ receiving the data s • Buffer in I/O module compensates for speed differences • Point-to-Point and Multipoint Configurations o Point-to-point interface § provides a dedicated line between ... Pointers - starting and ending points of the process in memory (used for memory management • Context Data - processor register values • The OS maintains state information for each process in ... not o Handles the interrupt Universidade Minho – Dep Informática - Campus de Gualtar – 4710-057 Braga - PORTUGAL- http://www.di.uminho.pt William Stallings, “ Computer Organization and Architecture ...

Ngày tải lên: 14/08/2014, 14:20

... IEEE Standard for Floating Point Arithmetic o Infinity § Most operations involving infinity yield infinity § Signs obey usual laws § -infinity -infinity yields -infinity and +infinity +infinity ... + infinity and -infinity § Result is rounded up toward positive infinity or Result is rounded down toward negative infinity § Useful in implementing interval arithmetic * every calculation in ... http://www.di.uminho.pt William Stallings, “ Computer Organization and Architecture 5th Ed., 2000 , The Instruction Cycle (11.3) • Review: Basic instruction cycle contains the following sub-cycles...

Ngày tải lên: 14/08/2014, 14:20

... CENTRAL PROCESSING UNIT 10 11 12 Reduced Instruction Set Computers (RISCs) (5-Jan-01) Introduction • RISC is one of the few true innovations in computer organization and architecture in the last ... the CPU and its interaction with memory § Operands used - types of operands and their frequency of use Determine memory organization and addressing modes § Execution Sequencing - determines the ... rearrange instructions to avoid the idle Superpipelining • A superpipelined architecture is one that makes use of more, and finer-grained, pipeline stages Universidade Minho – Dep Informática...

Ngày tải lên: 14/08/2014, 14:20

... http://www.di.uminho.pt William Stallings, “ Computer Organization and Architecture 5th Ed., 2000 , § Increasing Speed § Increasing Number of I/O Ports § Increasing Memory Size § Increasing Cost § ... computer components, to the increasing use of parallel organization concepts in combining those components In spite of the variety and pace of change in the computer field, certain fundamental concepts ... http://www.shore.net/~ws PROJECTS FOR TEACHING COMPUTER ORGANIZATION AND ARCHITECTURE For many instructors, an important component of a computer organization and architecture course is a project or...

Ngày tải lên: 14/08/2014, 20:21

... Pins - includes clock and reset § Address and Data Pins - 32 time-multiplexed lines for addresses and data, plus lines to interpret and validate these § Interface Control Pins - control timing ... interrupt handler routine • Multiple interrupts o Can be handled by disabling some or all interrupts Disabled interrupts generally remain pending and are handled sequentially o Can be handled by ... line: polling - when line goes high, CPU polls devices to determine which caused interrupt § Multiple lines: addressable interrupts - combination of lines indicates both interrupt and which device...

Ngày tải lên: 14/08/2014, 20:21

... Cache Main Memory Cache Registers Universidade Minho – Dep Informática - Campus de Gualtar – 4710-057 Braga - PORTUGAL- http://www.di.uminho.pt William Stallings, “ Computer Organization and Architecture ... Universidade Minho – Dep Informática - Campus de Gualtar – 4710-057 Braga - PORTUGAL- http://www.di.uminho.pt William Stallings, “ Computer Organization and Architecture 5th Ed., 2000 , § Inversely proportional ... updateable in place - writing uses ordinary bus control, address, and data lines Universidade Minho – Dep Informática - Campus de Gualtar – 4710-057 Braga - PORTUGAL- http://www.di.uminho.pt William...

Ngày tải lên: 14/08/2014, 20:21