central processing unit in computer organization and architecture

... central processing unit design, 86 Semantic gap computer architecture and, RISC/CISC evolution cycle, 218 Sequencing instructions, computer architectures, 28– 30 Sequential processing, pipelining ... representation, 63 Integer unit Alpha 2164 pipeline, 230 1026EJ-S processor pipeline design, 203 Integrated circuit (IC), main memory unit, 141 – 142 Intel microprocessors central processing unit design, ... Medium-scale integration (MSI), evolution of, 5– Memory access registers, central processing unit design, 85 – 86 Memory address register (MAR) central processing unit design, 85– 86 interrupt handling,

Ngày tải lên: 19/09/2013, 15:53

... CENTRAL PROCESSING UNIT 10 11 12 Reduced Instruction Set Computers (RISCs) (5-Jan-01) Introduction • RISC is one of the few true innovations in computer organization and architecture in the last ... http://www.di.uminho.pt William Stallings, “ Computer Organization and Architecture? ?? 5th Ed., 2000 , III THE CENTRAL PROCESSING UNIT 10 11 12 … 13 Instruction-Level Parallelism and Superscalar ... rearrange instructions to avoid the idle Superpipelining • A superpipelined architecture is one that makes use of more, and finer-grained, pipeline stages Universidade Minho – Dep Informática

Ngày tải lên: 14/08/2014, 14:20

... courses in Computer Organization and Architecture in the Computer Science and Engineering departments. This text provides a clear, comprehensive presentation of the organization and architecture ... 6. Input/Output. 7. Operating System Support. III. THE CENTRAL PROCESSING UNIT. 8. Computer Arithmetic. 9. Instruction Sets: Characteristics and Functions. 10. Instruction Sets: Addressing ... underlying integrated circuit technology used to construct computer components, to the increasing use of parallel organization concepts in combining those components. In spite of the variety and

Ngày tải lên: 14/08/2014, 20:21

... interrupt handler routine • Multiple interrupts o Can be handled by disabling some or all interrupts. Disabled interrupts generally remain pending and are handled sequentially o Can be handled ... One line: polling - when line goes high, CPU polls devices to determine which caused interrupt § Multiple lines: addressable interrupts - combination of lines indicates both interrupt and which ... System Pins - includes clock and reset § Address and Data Pins - 32 time-multiplexed lines for addresses and data, plus lines to interpret and validate these § Interface Control Pins - control

Ngày tải lên: 14/08/2014, 20:21

... do Minho – Dep. Informática - Campus de Gualtar – 4710-057 Braga - PORTUGAL- http://www.di.uminho.pt William Stallings, ? ?Computer Organization and Architecture? ??, 5th Ed., 2000 bytes). The initiator ... the AD lines and asserts TRDY to indicate that valid data is present on the bus. e. The initiator reads the data at the beginning of clock 4 and changes the byte enable lines as needed in preparation ... http://www.di.uminho.pt William Stallings, ? ?Computer Organization and Architecture? ??, 5th Ed., 2000 II. THE COMPUTER SYSTEM. 3. 4. Internal Memory. (29-Feb-00) Characteristics of Computer Memory

Ngày tải lên: 14/08/2014, 20:21

... image•Single point of entry•Single file hierarchy•Single control point•Single virtual networking•Single memory space•Single job management system•Single user interface•Single I/O space•Single ... scalability—Automatically include new computers in scheduling Trang 56 Parallelizing• Single application executing in parallel on a number of machines in cluster—Complier–Determines at compile time ... Multiple Processor Organization Trang 3 Single Instruction, Single Data Stream - SISD• Single processor• Single instruction stream• Data stored in single memory Trang 4 Single Instruction, Multiple

Ngày tải lên: 30/11/2016, 22:13

... Stallings Computer Organization and Architecture 6th Edition Chapter 15 IA-64 Architecture Background to IA-64 • Pentium 4 appears to be last? ?in? ?x86 line • Intel & Hewlett­Packard (HP) jointly developed ... four execution units are available IA-64 Execution Units • I? ?Unit —Integer arithmetic —Shift? ?and? ?add —Logical —Compare —Integer multimedia ops • M? ?Unit —Load? ?and? ?store – Between register? ?and? ?memory —Some integer ALU ... Predication —Each instruction? ?in? ?loop predicated on rotating  predicate register – Determines whether pipeline is? ?in? ?prolog, kernel or epilog • Special loop termination instructions —Branch instructions that cause registers to rotate? ?and? ?

Ngày tải lên: 30/01/2020, 00:03

... Micro­ops fixed length — Superscalar pipelining? ?and? ?scheduling • Pentium instructions long & complex • Performance improved by separating decoding from  scheduling & pipelining — (More later – ch14) • Data cache is write back ... Number of blocks? ?in? ?main memory = 2d Number of lines? ?in? ?set = k Number of sets = v = 2d Number of lines? ?in? ?cache = kv = k * 2d Size of tag = (s – d) bits Replacement Algorithms (1) Direct mapping • No choice ... L1 cache controlled by 2 bits? ?in? ?register — CD = cache disable — NW = not write through — 2 instructions to invalidate (flush) cache? ?and? ?write back then  invalidate Power PC Cache Organization • • • • • 601 – single 32kb 8 way set associative

Ngày tải lên: 30/01/2020, 00:03

... William Stallings Computer Organization and Architecture 6th Edition Chapter Computer Arithmetic Arithmetic & Logic Unit • Does the calculations • Everything else? ?in? ?the? ?computer? ?is there to  ... service this? ?unit • Handles integers • May handle floating point (real) numbers • May be separate FPU (maths co­processor) • May be on chip separate FPU (486DX +) ALU Inputs and Outputs Integer Representation ... Point is actually fixed between sign bit? ?and? ?body  of mantissa • Exponent indicates place value (point position) Floating Point Examples Signs for Floating Point • Mantissa is stored? ?in? ?2s compliment • Exponent is? ?in? ?excess or biased notation

Ngày tải lên: 30/01/2020, 00:07

... William Stallings Computer Organization and Architecture 6th Edition Chapter Internal Memory Semiconductor Memory Types Semiconductor Memory • RAM  —Misnamed as all semiconductor memory is random  ... —Reduces number of address pins – Multiplex row address? ?and? ?column address – 11 pins to address (211=2048) – Adding one more pin doubles range of values so x4 capacity Refreshing • • • • • • Refresh circuit included on chip ... Packaging Module Organization Module Organization (2) Error Correction • Hard Failure —Permanent defect • Soft Error —Random, non­destructive —No permanent damage to memory • Detected using Hamming error correcting code

Ngày tải lên: 30/01/2020, 01:38

... William Stallings Computer Organization and Architecture 6th Edition Chapter 10 Instruction Sets: Characteristics and Functions What is an instruction set? • The complete collection of instructions that are  ... anyway) a symbolic representation is used —e.g. ADD, SUB, LOAD • Operands can also be represented? ?in? ?this way —ADD A,B Simple Instruction Format Instruction Types • • • • Data? ?processing Data storage (main memory) Data movement (I/O) ... Subroutine call —c.f. interrupt call Branch Instruction Nested Procedure Calls Use of Stack Exercise For Reader • Find out about instruction set for Pentium? ?and? ? PowerPC • Start with Stallings

Ngày tải lên: 30/01/2020, 02:23

... Stallings Computer Organization and Architecture 6th Edition Chapter 18 Parallel Processing Multiple Processor Organization • • • • Single instruction, single data stream ­ SISD Single instruction, multiple data stream ­ SIMD ... JOIN N causes N independent processes to join? ?and? ?merge  following JOIN – O/S Co­ordinates JOINs – Execution is blocked until all N processes have reached JOIN Processor Designs • Pipelined ALU —Within operations ... Data stored? ?in? ?single memory Uni­processor Single Instruction, Multiple Data Stream - SIMD • • • • • Single machine instruction  Controls simultaneous execution Number of? ?processing? ?elements

Ngày tải lên: 30/01/2020, 03:38

... William Stallings Computer Organization and Architecture 6th Edition Chapter 13 Reduced Instruction Set Computers Major Advances in Computers(1) • The family concept —IBM System/360  1964 ... —Limited? ?and? ?simple instruction set —Emphasis on optimising the instruction pipeline Comparison of processors Driving force for CISC • • • • Software costs far exceed hardware costs Increasingly complex high level languages ... —(See memory notes) • Microprocessors —Intel 4004  1971 • Pipelining —Introduces parallelism into fetch execute cycle • Multiple processors The Next Step - RISC • Reduced Instruction Set? ?Computer • Key features

Ngày tải lên: 30/01/2020, 04:03

... module issuing the interrupt? Đ How do you deal with multiple interrupts? ã i.e. an interrupt handler being interrupted Input/Output Problems Đ Wide variety of peripherals ã Delivering different ... free (Re)Selection Command, Data, Status, Message Reset ISA Bus Interrupt System Đ ISA bus chains two 8259As together Đ Link is via interrupt 2 Đ Gives 15 lines ã 16 lines less one for link Đ IRQ 9 is ... keyboard Đ Machine readable ã Monitoring and control Đ Communication ã Modem ã Network Interface Card (NIC) Small Computer Systems Interface (SCSI) Đ Parallel interface Đ 8, 16, 32 bit data lines Đ...

Ngày tải lên: 05/11/2013, 22:15

... programs ã Swapping Advantages of Segmentation Đ Simplifies handling of growing data structures Đ Allows programs to be altered and recompiled independently, without re-linking and re-loading Đ Lends ... process will load into the same place in memory Đ Instructions contain addresses ã Locations of data ã Addresses for instructions (branching) Đ Logical address - relative to beginning of program Đ ... process and bring in another Đ New process may be smaller than swapped out process Đ Another hole Key Elements of O/S Partitioning Đ Splitting memory into sections to allocate to processes (including...

Ngày tải lên: 12/12/2013, 09:15

... branch ã Testing data, status of computation (zero, overflow) ã Branch to some location depending on decision William Stallings Computer Organization and Architecture Chapter 9 Instruction ... fetch next instruction ã On most case, next instruction to be fetched immediately follows current instruction Specific Data Types Đ General - arbitrary binary contents Đ Integer - single binary ... value Đ Ordinal - unsigned integer Đ Unpacked BCD - One digit per byte Đ Packed BCD - 2 BCD digits per byte Đ Near Pointer - 32 bit offset within segment Đ Bit field Đ Byte String Đ Floating Point ...

Ngày tải lên: 12/12/2013, 09:15

... off between powerful instruction repertoire and saving space Indirect Addressing Diagram Address AOpcode Instruction Memory Operand Pointer to operand Indirect Addressing (2) Đ Large address ... programming or compiler writing ã N.B. C programming ỹregister int a; Đ c.f. Direct addressing Register Addressing (1) Đ Operand is held in register named in address filed Đ EA = R Đ Operand = ... versa Indirect Addressing (1) Đ Memory cell pointed to by address field contains the address of (pointer to) the operand Đ EA = (A) ã Look in A, find address (A) and look there for operand Đ...

Ngày tải lên: 12/12/2013, 09:15

... main memory Đ Can fetch next instruction during execution of current instruction Đ Called instruction prefetch Example Register Organizations Data Flow (Data Fetch) Đ IR is examined Đ If indirect ... pipeline Đ Check buffer before fetching from memory Đ Very good for small loops or jumps Đ c.f. cache Đ Used by CRAY-1 Pipelining Đ Fetch instruction Đ Decode instruction Đ Calculate operands ... operands Đ Execute instructions Đ Write result Đ Overlap these operations Data Flow (Execute) Đ May take many forms Đ Depends on instruction being executed Đ May include ã Memory read/write ã Input/Output ã...

Ngày tải lên: 12/12/2013, 09:15

... average; SW average Structure - Top Level Computer Main Memory Input Output Systems Interconnection Peripherals Communication lines Central Processing Unit Computer ... toward a designing a modular system: — Top down — Bottom up William Stallings Computer Organization and Architecture 7 th Edition Chapter 1 Introduction Outline of the Book (1) ã Computer Evolution ... The CPU Computer Arithmetic and Login Unit Control Unit Internal CPU Interconnection Registers CPU I/O Memory System Bus CPU Internet Resources - Web site for book ã http://WilliamStallings.com/COA/COA7e.html links...

Ngày tải lên: 02/07/2014, 04:21