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The Stored Program Computer 1943: ENIAC • Presper Eckert and John Mauchly first general electronic computer (or was it John V Atanasoff in 1939?) • Hard-wired program settings of dials and switches Chapter - ISA 1944: Beginnings of EDVAC • among other improvements, includes program stored in memory 1.The The Von Neumann Model 1945: John von Neumann • wrote a report on the stored program concept, known as the First Draft of a Report on EDVAC The basic structure proposed in the draft became known as the “von Neumann machine” (or model) • a memory, containing instructions and data • a processing unit, for performing arithmetic and logical operations • a control unit, for interpreting instructions For more history, see http://www.maxmon.com/history.htm 4-2 Von Neumann Model Memory 2k x m array of stored bits Address MEMORY MAR MDR INPUT Keyboard Mouse Scanner Disk • unique (k-bit) identifier of location OUTPUT PROCESSING UNIT ALU TEMP Contents Monitor Printer LED Disk • m-bit value stored in location Basic Operations: LOAD • read a value from a memory location CONTROL UNIT PC 0000 0001 0010 0011 0100 0101 0110 1101 1110 1111 00101101 • • • 10100010 STORE IR • write a value to a memory location 4-3 4-4 CuuDuongThanCong.com https://fb.com/tailieudientucntt Interface to Memory Processing Unit How does processing unit get data to/from memory? MAR: Memory Address Register MEMORY MDR: Memory Data Register Functional Units MAR • ALU = Arithmetic and Logic Unit • could have many functional units some of them special-purpose (multiply, square root, …) • LC-3 performs ADD, AND, NOT MDR To LOAD a location (A): PROCESSING UNIT TEMP ALU Registers Write the address (A) into the MAR Send a “read” signal to the memory Read the data from MDR • Small, temporary storage • Operands and results of functional units • LC-3 has eight registers (R0, …, R7), each 16 bits wide To STORE a value (X) to a location (A): Word Size Write the data (X) to the MDR Write the address (A) into the MAR Send a “write” signal to the memory • number of bits normally processed by ALU in one instruction • also width of registers • LC-3 is 16 bits 4-5 4-6 Input and Output Control Unit Devices for getting data into and out of computer memory Orchestrates execution of the program Each device has its own interface, usually a set of registers like the memory’s MAR and MDR INPUT OUTPUT Keyboard Mouse Scanner Disk Monitor Printer LED Disk CONTROL UNIT PC IR Instruction Register (IR) contains the current instruction Program Counter (PC) contains the address of the next instruction to be executed Control unit: • LC-3 supports keyboard (input) and monitor (output) • keyboard: data register (KBDR) and status register (KBSR) • monitor: data register (DDR) and status register (DSR) • reads an instruction from memory Some devices provide both input and output ¾ the instruction’s address is in the PC • disk, network • interprets the instruction, generating signals that tell the other components what to Program that controls access to a device is usually called a driver 4-7 ¾ an instruction may take many machine cycles to complete 4-8 CuuDuongThanCong.com https://fb.com/tailieudientucntt Instruction Processing Instruction The instruction is the fundamental unit of work Specifies two things: Fetch instruction from memory • opcode: operation to be performed • operands: data/locations to be used for operation Decode instruction Execute operation An instruction is encoded as a sequence of bits (Just like data!) • Often, but not always, instructions have a fixed length, such as 16 or 32 bits • Control unit interprets instruction: generates sequence of control signals to carry out operation • Operation is either executed completely, or not at all Store result A computer’s instructions and their formats is known as its Instruction Set Architecture (ISA) E l t address Evaluate dd Fetch operands from memory 4-9 4-10 Example: LC-3 ADD Instruction Example: LC-3 LDR Instruction LC-3 has 16-bit instructions Load instruction reads data from memory Base + offset mode: • Each instruction has a four-bit opcode, bits [15:12] LC-3 has eight registers (R0-R7) for temporary storage • add offset to base register result is memory address • load from memory address into destination register • Sources and destination of ADD are registers “Add the contents of R2 to the contents of R6, and store the result in R6.” “Add the value to the contents of R3 to form a memory address Load the contents of that memory location to R2.” 4-11 4-12 CuuDuongThanCong.com https://fb.com/tailieudientucntt Instruction Processing: FETCH Load next instruction (at address stored in PC) from memory into Instruction Register (IR) • Copy contents of PC into MAR • Send “read” signal to memory • Copy contents of MDR into IR Then increment PC, so that it points to the next instruction in sequence • PC becomes PC+1 Instruction Processing: DECODE First identify the opcode F • In LC-3, this is always the first four bits of instruction • A 4-to-16 decoder asserts a control line corresponding to the desired opcode D F D EA Depending p g on opcode, p , identify y other operands p from the remaining bits EA OP ã Example: ắfor LDR, last six bits is offset ¾for ADD, last three bits is source operand #2 OP EX S EX S 4-13 4-14 Instruction Processing: EVALUATE ADDRESS Instruction Processing: FETCH OPERANDS For instructions that require memory access, compute address used for access F Obtain source operands needed to perform operation F Examples: D Examples: D • add offset to base register (as in LDR) • add offset to PC • add offset to zero EA • load data from memory (LDR) • read data from register file (ADD) EA OP OP EX EX S S 4-15 4-16 CuuDuongThanCong.com https://fb.com/tailieudientucntt Instruction Processing: EXECUTE Instruction Processing: STORE RESULT Perform the operation, using the source operands F Write results to destination (register or memory) F Examples: D Examples: D • send operands to ALU and assert ADD signal • nothing (e.g., (e g for loads and stores) EA OP • result of ADD is placed in destination register • result of memory load is placed in destination register • for store instruction, data is stored to memory ¾write address to MAR, data to MDR ¾assert WRITE signal to memory EA OP EX EX S S 4-17 4-18 Changing the Sequence of Instructions Example: LC-3 JMP Instruction In the FETCH phase, we increment the Program Counter by Set the PC to the value contained in a register This becomes the address of the next instruction to fetch What if we don’t want to always execute the instruction that follows this one? • examples: loop, if-then, function call Need special instructions that change the contents of the PC These are called control instructions • jumps are unconditional they always change the PC • branches are conditional they change the PC only if some condition is true (e.g., the result of an ADD is zero) “Load the contents of R3 into the PC.” 4-19 4-20 CuuDuongThanCong.com https://fb.com/tailieudientucntt Instruction Processing Summary Control Unit State Diagram Instructions look just like data it’s all interpretation The control unit is a state machine Here is part of a simplified state diagram for the LC-3: Three basic kinds of instructions: • computational instructions (ADD, AND, …) • data movement instructions (LD, ST, …) • control instructions (JMP (JMP, BRnz BRnz, …)) Six basic phases of instruction processing: F → D → EA → OP → EX → S • not all phases are needed by every instruction • phases may take variable number of machine cycles 4-21 A more complete state diagram is in Appendix C It will be more understandable after Chapter 4-22 Instruction Set Architecture ISA = All of the programmer-visible components and operations of the computer The LC-3 ã memory organization ắ address space how may locations can be addressed? ¾ addressibility how many bits per location? • register set ¾ how many? what size? how are they used? ã instruction set ắ opcodes ắ data types ắ addressing modes ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language) 4-24 CuuDuongThanCong.com https://fb.com/tailieudientucntt LC-3 Overview: Memory and Registers LC-3 Overview: Instruction Set Memory Opcodes • address space: 216 locations (16-bit addresses) • addressability: 16 bits Registers • temporary storage, accessed in a single machine cycle ¾accessing memory generally takes longer than a single cycle ã eight general-purpose registers: R0 - R7 ắeach 16 bits wide ¾how many bits to uniquely identify a register? ã other registers ắnot directly addressable, but used by (and affected by) instructions ắPC (program counter), condition codes ã • • • • 15 opcodes Operate instructions: ADD, AND, NOT Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STI Control instructions: BR, JSR/JSRR, JMP, RTI, TRAP some opcodes set/clear condition codes, based on result: ¾N = negative, Z = zero, P = positive (> 0) Data Types • 16-bit 2’s complement integer Addressing Modes • How is the location of an operand specified? • non-memory addresses: immediate, register • memory addresses: PC-relative, indirect, base+offset 4-25 Operate Instructions 4-26 NOT (Register) Only three operations: ADD, AND, NOT Source and destination operands are registers • These instructions not reference memory • ADD and AND can use “immediate” mode, where one operand p is hard-wired into the instruction Will show dataflow diagram with each instruction • illustrates when and where data moves to accomplish the desired operation 4-27 Note: Src and Dst could be the same register 4-28 CuuDuongThanCong.com https://fb.com/tailieudientucntt ADD/AND (Register) this zero means “register mode” ADD/AND (Immediate) this one means “immediate mode” Note: Immediate field is sign-extended 4-29 4-30 Using Operate Instructions Data Movement Instructions With only ADD, AND, NOT… Load read data from memory to register • LD: PC-relative mode • LDR: base+offset mode • LDI: indirect mode • How we subtract? Store write data from register to memory • How we OR? • ST ST: PC-relative PC l i mode d • STR: base+offset mode • STI: indirect mode • How we copy from one register to another? Load effective address compute address, save in register • How we initialize a register to zero? • LEA: immediate mode • does not access memory 4-31 4-32 CuuDuongThanCong.com https://fb.com/tailieudientucntt PC-Relative Addressing Mode LD (PC-Relative) Want to specify address directly in the instruction • But an address is 16 bits, and so is an instruction! • After subtracting bits for opcode and bits for register, we have bits available for address Solution: • Use the bits as a signed offset from the current PC bits: − 256 ≤ offset ≤ +255 Can form any address X, such that: PC − 256 ≤ X ≤ PC +255 Remember that PC is incremented as part of the FETCH phase; This is done before the EVALUATE ADDRESS stage 4-33 ST (PC-Relative) 4-34 Indirect Addressing Mode With PC-relative mode, can only address data within 256 words of the instruction • What about the rest of memory? Solution #1: • Read address from memory location, location then load/store to that address First address is generated from PC and IR (just like PC-relative addressing), then content of that address is used as target for load/store 4-35 4-36 CuuDuongThanCong.com https://fb.com/tailieudientucntt LDI (Indirect) STI (Indirect) 4-37 Base + Offset Addressing Mode 4-38 LDR (Base+Offset) With PC-relative mode, can only address data within 256 words of the instruction • What about the rest of memory? Solution #2: • Use a register to generate a full 16-bit 16 bit address address bits for opcode, for src/dest register, bits for base register remaining bits are used as a signed offset • Offset is sign-extended before adding to base register 4-39 4-40 10 CuuDuongThanCong.com https://fb.com/tailieudientucntt STR (Base+Offset) Load Effective Address Computes address like PC-relative (PC plus signed offset) and stores the result into a register Note: The address is stored in the register, not the contents of the memory location 4-41 LEA (Immediate) 4-42 Example 4-43 Address Instruction Comments x30F6 1 0 1 1 1 1 R1 ← PC – = x30F4 x30F7 0 1 0 1 1 R2 ← R1 + 14 = x3102 x30F8 0 1 1 1 1 1 M[PC - 5] ← R2 M[x30F4] ← x3102 x30F9 1 0 1 0 0 R2 ← x30FA 0 1 0 1 0 1 R2 ← R2 + = x30FB 1 1 0 0 1 M[R1+14] ← R2 M[x3102] ← x30FC 1 0 1 1 1 1 1 R3 ← M[M[x30F4]] R3 ← M[x3102] R3 ← opcode 4-44 11 CuuDuongThanCong.com https://fb.com/tailieudientucntt Control Instructions Condition Codes Used to alter the sequence of instructions (by changing the Program Counter) LC-3 has three condition code registers: N negative Z zero P positive (greater than zero) Conditional Branch • branch is taken if a specified condition is true ¾signed offset is added to PC to yield new PC • else, l the th branch b h is i nott ttaken k ¾PC is not changed, points to the next sequential instruction Unconditional Branch (or Jump) Set by any instruction that writes a value to a register (ADD, AND, NOT, LD, LDR, LDI, LEA) Exactly one will be set at all times • always changes the PC • Based on the last instruction that altered a register TRAP • changes PC to the address of an OS “service routine” • routine will return control to the next instruction (after TRAP) 4-45 Branch Instruction 4-46 BR (PC-Relative) Branch specifies one or more condition codes If the set bit is specified, the branch is taken • PC-relative addressing: target address is made by adding signed offset (IR[8:0]) to current PC • Note: PC has already been incremented by FETCH stage • Note: Target must be within 256 words of BR instruction If the branch is not taken, the next sequential instruction is executed 4-47 What happens if bits [11:9] are all zero? All one? 4-48 12 CuuDuongThanCong.com https://fb.com/tailieudientucntt Using Branch Instructions Sample Program Compute sum of 12 integers Numbers start at location x3100 Program starts at location x3000 R1 ← x3100 R3 ← R2 ← 12 R2=0? NO R4 R3 R1 R2 ← ← ← ← M[R1] R3+R4 R1+1 R2-1 YES Address Instruction Comments x3000 1 0 1 1 1 1 R1 ← x3100 (PC+0xFF) x3001 1 1 1 0 0 R3 ← x3002 1 0 1 0 0 R2 ← x3003 0 1 0 1 1 0 R2 ← 12 x3004 0 0 0 0 0 1 If Z, goto x300A (PC+5) x3005 1 0 0 0 0 0 Load next value to R4 x3006 0 1 1 0 0 Add to R3 x3007 0 0 0 1 0 0 Increment R1 (pointer) X3008 0 1 0 1 1 1 Decrement R2 (counter) x3009 0 0 1 1 1 1 1 Goto x3004 (PC-6) 4-49 JMP (Register) 4-50 TRAP Jump is an unconditional branch always taken • Target address is the contents of a register • Allows any target address Calls a service routine, identified by 8-bit “trap vector.” vector routine x23 p a character from the keyboard y input x21 output a character to the monitor x25 halt the program When routine is done, PC is set to the instruction following TRAP (We’ll talk about how this works later.) 4-51 4-52 13 CuuDuongThanCong.com https://fb.com/tailieudientucntt Another Example Flow Chart Count the occurrences of a character in a file • Program begins at location x3000 • Read character from keyboard • Load each character from a “file” Count = (R2 = 0) Done? YES (R1 ?= EOT) ¾ File is a sequence of memory locations ¾ Starting address of file is stored in the memory location immediately after the program Ptr = 1st file character Convert count to ASCII character (R0 = x30, R0 = R2 + R0) NO (R3 = M[x3012]) Print count YES • If file character equals input character, increment counter • End of file is indicated by a special ASCII value: EOT (x04) • At the end, print the number of characters and halt Match? NO ((TRAP x21)) (R1 ?= R0) Input char from keybd (TRAP x23) HALT (assume there will be less than 10 occurrences of the character) Incr Count (TRAP x25) (R2 = R2 + 1) Load char from file (R1 = M[R3]) A special character used to indicate the end of a sequence is often called a sentinel Load next char from file (R3 = R3 + 1, R1 = M[R3]) • Useful when you don’t know ahead of time how many times to execute a loop 4-53 Program (1 of 2) 4-54 Program (2 of 2) Address Instruction Comments Address Instruction Comments x3000 1 0 1 0 0 R2 ← (counter) x300A 0 1 0 1 0 0 R2 ← R2 + x3001 0 0 1 0 0 0 0 R3 ← M[x3102] (ptr) x300B 0 1 1 1 0 0 R3 ← R3 + x3002 1 1 0 0 0 0 1 Input to R0 (TRAP x23) x300C 1 0 1 0 0 0 R1 ← M[R3] x3003 1 0 1 0 0 0 R1 ← M[R3] x300D 0 0 1 1 1 1 1 Goto x3004 x3004 0 1 0 0 1 1 0 R4 ← R1 – (EOT) x300E 0 0 0 0 0 0 0 R0 ← M[x3013] x3005 0 0 0 0 0 0 If Z, goto x300E x300F 0 0 0 0 0 0 R0 ← R0 + R2 x3006 0 0 0 1 1 1 R1 ← NOT R1 x3010 1 1 0 0 0 0 0 Print R0 (TRAP x21) x3007 0 0 0 1 0 0 R1 ← R1 + x3011 1 1 0 0 0 0 1 HALT (TRAP x25) X3008 0 0 0 0 0 0 R1 ← R1 + R0 X3012 Starting Address of File x3009 0 0 1 0 0 0 0 If N or P, goto x300B x3013 0 0 0 0 0 1 0 0 4-55 ASCII x30 (‘0’) 4-56 14 CuuDuongThanCong.com https://fb.com/tailieudientucntt LC-3 Data Path Revisited Data Path Components Global bus • special set of wires that carry a 16-bit signal to many components • inputs to the bus are “tri-state devices,” that only place a signal on the bus when they are enabled • only one (16-bit) signal should be enabled at any time ¾ ¾control t l unit it decides d id which hi h signal i l “drives” “d i ” the th bus b • any number of components can read the bus ¾register only captures bus data if it is write-enabled by the control unit Filled arrow = info to be processed Unfilled arrow = control signal Memory • Control and data registers for memory and I/O devices • memory: MAR, MDR (also control signal for read/write) 4-57 4-58 Data Path Components Data Path Components ALU PC and PCMUX • Accepts inputs from register file and from sign-extended bits from IR (immediate field) • Output goes to bus ¾used by condition code logic, register file, memory • Register File Three inputs to PC, controlled by PCMUX PC+1 – FETCH stage Address adder – BR, JMP bus – TRAP (discussed later) MAR and MARMUX • Two read addresses (SR1, SR2), one write address (DR) • Input from bus ¾result of ALU operation or memory read ã Two 16-bit outputs ắused by ALU, PC, memory address ắdata for store instructions passes through ALU ã Two inputs to MAR, controlled by MARMUX Address adder – LD/ST, LDR/STR Zero-extended IR[7:0] TRAP (discussed later) 4-59 4-60 15 CuuDuongThanCong.com https://fb.com/tailieudientucntt Data Path Components Condition Code Logic • Looks at value on bus and generates N, Z, P signals • Registers set only when control unit enables them (LD.CC) ¾only certain instructions set the codes (ADD, AND, NOT, LD, LDI, LDR, LEA) Control Unit – Finite State Machine • On each machine cycle, changes control signals for next phase of instruction processing ¾who drives the bus? (GatePC, GateALU, …) ¾which registers are write enabled? (LD.IR, LD.REG, ) ắwhich operation should ALU perform? (ALUK) ắ ã Logic includes decoder for opcode, etc 4-61 16 CuuDuongThanCong.com https://fb.com/tailieudientucntt ... controls access to a device is usually called a driver 4- 7 ¾ an instruction may take many machine cycles to complete 4- 8 CuuDuongThanCong.com https://fb.com/tailieudientucntt Instruction Processing... later.) 4- 51 4- 52 13 CuuDuongThanCong.com https://fb.com/tailieudientucntt Another Example Flow Chart Count the occurrences of a character in a file • Program begins at location x3000 • Read character... return control to the next instruction (after TRAP) 4- 45 Branch Instruction 4- 46 BR (PC-Relative) Branch specifies one or more condition codes If the set bit is specified, the branch is taken • PC-relative