Computer architecture Part III The ArithmeticLogic Unit

Part III The Arithmetic/Logic Unit Jan 2007 Computer Architecture, The Arithmetic/Logic Unit Slide About This Presentation This presentation is intended to support the use of the textbook Computer Architecture: From Microprocessors to Supercomputers, Oxford University Press, 2005, ISBN 0-19-515455-X It is updated regularly by the author as part of his teaching of the upper-division course ECE 154, Introduction to Computer Architecture, at the University of California, Santa Barbara Instructors can use these slides freely in classroom teaching and for other educational purposes Any other use is strictly prohibited © Behrooz Parhami Edition Released Revised Revised Revised Revised First July 2003 July 2004 July 2005 Mar 2006 Jan 2007 Jan 2007 Computer Architecture, The Arithmetic/Logic Unit Slide III The Arithmetic/Logic Unit Overview of computer arithmetic and ALU design: • Review representation methods for signed integers • Discuss algorithms & hardware for arithmetic ops • Consider floating-point representation & arithmetic Topics in This Part Chapter Number Representation Chapter 10 Adders and Simple ALUs Chapter 11 Multipliers and Dividers Chapter 12 Floating-Point Arithmetic Jan 2007 Computer Architecture, The Arithmetic/Logic Unit Slide Computer Arithmetic as a Topic of Study Brief overview article – Encyclopedia of Info Systems, Academic Press, 2002, Vol 3, pp 317-333 Our textbook’s treatment of the topic falls between the two extremes (4 chap.) Graduate course ECE 252B – Text: Computer Arithmetic, Oxford U Press, 2000 Jan 2007 Computer Architecture, The Arithmetic/Logic Unit Slide Number Representation Arguably the most important topic in computer arithmetic: • Affects system compatibility and ease of arithmetic • Two’s complement, flp, and unconventional methods Topics in This Chapter 9.1 Positional Number Systems 9.2 Digit Sets and Encodings 9.3 Number-Radix Conversion 9.4 Signed Integers 9.5 Fixed-Point Numbers 9.6 Floating-Point Numbers Jan 2007 Computer Architecture, The Arithmetic/Logic Unit Slide 9.1 Positional Number Systems Representations of natural numbers {0, 1, 2, 3, …} ||||| ||||| ||||| ||||| ||||| || 27 11011 XXVII sticks or unary code radix-10 or decimal code radix-2 or binary code Roman numerals Fixed-radix positional representation with k digits k–1 Value of a number: x = (xk–1xk–2 x1x0)r = Σ xi r i i=0 For example: 27 = (11011)two = (1×24) + (1×23) + (0×22) + (1×21) + (1×20) Number of digits for [0, P]: k = ⎡logr (P + 1)⎤ = ⎣logr P⎦ + Jan 2007 Computer Architecture, The Arithmetic/Logic Unit Slide Unsigned Binary Integers 0000 1111 15 1110 0001 0010 14 1101 0011 13 12 1100 1011 Turn x notches counterclockwise to add x Inside: Natural number Outside: 4-bit encoding 11 10 1010 0100 0101 12 11 10 15 6 1001 14 13 1000 0110 0111 Turn y notches clockwise to subtract y Figure 9.1 Schematic representation of 4-bit code for integers in [0, 15] Jan 2007 Computer Architecture, The Arithmetic/Logic Unit Slide Representation Range and Overflow − Overflow region max max Numbers smaller than max − + Overflow region Numbers larger than max + Finite set of representable numbers Figure 9.2 Overflow regions in finite number representation systems For unsigned representations covered in this section, max – = Example 9.2, Part d Discuss if overflow will occur when computing 317 – 316 in a number system with k = digits in radix r = 10 Solution The result 86 093 442 is representable in the number system which has a range [0, 99 999 999]; however, if 317 is computed en route to the final result, overflow will occur Jan 2007 Computer Architecture, The Arithmetic/Logic Unit Slide 9.2 Digit Sets and Encodings Conventional and unconventional digit sets • Decimal digits in [0, 9]; 4-bit BCD, 8-bit ASCII • Hexadecimal, or hex for short: digits 0-9 & a-f • Conventional ternary digit set in [0, 2] Conventional digit set for radix r is [0, r – 1] Symmetric ternary digit set in [–1, 1] • Conventional binary digit set in [0, 1] Redundant digit set [0, 2], encoded in bits ( 1 )two and ( 1 )two represent 22 Jan 2007 Computer Architecture, The Arithmetic/Logic Unit Slide Carry-Save Numbers Radix-2 numbers using the digits 0, 1, and Example: (1 1)two = (1×23) + (0×22) + (2×21) + (1×20) = 13 Possible encodings (a) Binary (b) Unary 1 MSB LSB Jan 2007 00 01 10 11 (Unused) 0 = 0 = 00 01 (First alternate) 10 (Second alternate) 11 First bit Second bit Computer Architecture, The Arithmetic/Logic Unit 0 1 = 1 = 10 Slide 10 Exceptions Undefined results lead to NaN (not a number) (±0) / (±0) = NaN (+∞) + (–∞) = NaN (±0) × (±∞) = NaN (±∞) / (±∞) = NaN Arithmetic operations and comparisons with NaNs NaN + x = NaN NaN + NaN = NaN NaN × = NaN NaN × NaN = NaN NaN < Ỉ false NaN = Nan Æ false NaN ≠ (+∞) Æ true NaN ≠ NaN Æ true Examples of invalid-operation exceptions Addition: Multiplication: Division: Square-root: Jan 2007 (+∞) + (–∞) 0×∞ / or ∞ / ∞ Operand < Computer Architecture, The Arithmetic/Logic Unit Slide 77 12.3 Floating-Point Addition (±2e1s1) + (±2e1(s2 / 2e1–e2)) = ±2e1(s1 ± s2 / 2e1–e2) (±2e2s2) Numbers to be added: x = 25 × 1.00101101 y = 21 × 1.11101101 Operands after alignment shift: x = 25 × 1.00101101 y = 25 × 0.000111101101 Result of addition: s = 25 × 1.010010111101 s = 25 × 1.01001100 Figure 12.4 Jan 2007 Operand with smaller exponent to be preshifted Extra bits to be rounded off Rounded sum Alignment shift and rounding in floating-point addition Computer Architecture, The Arithmetic/Logic Unit Slide 78 Inp ut Hardware for Floating-Point Addition Inp ut Unpack Signs Exponents Significands Add′Sub Mu x Sub Possible swap & compleme nt Align significands Control & sign logic Add Norma lize & round Figure 12.5 Simplified schematic of a floating-point adder ± Sign Exponent Significand Pack Outp ut Jan 2007 Computer Architecture, The Arithmetic/Logic Unit Slide 79 12.4 Other Floating-Point Operations Overflow (underflow) possible Floating-point multiplication (±2e1s1) × (±2e2s2) = ±2e1+ e2(s1 × s2) Product of significands in [1, 4) If product is in [2, 4), halve to normalize (increment exponent) Overflow (underflow) possible Floating-point division (±2e1s1) / (±2e2s2) = ±2e1– e2(s1 / s2) Ratio of significands in (1/2, 2) If ratio is in (1/2, 1), double to normalize (decrement exponent) Floating-point square-rooting (2es)1/2 = 2e/2(s)1/2 = 2(e–1)2(2s)1/2 Normalization not needed Jan 2007 when e is even when e is odd Computer Architecture, The Arithmetic/Logic Unit Slide 80 Hardware for Floating-Point Multiplication and Division Input Input Unpack Signs Exponents Significands Mul′Div ± Multiply or divide Control & sign logic Normalize & round ± Figure 12.6 Simplified schematic of a floatingpoint multiply/divide unit Sign Exponent Significand Pack Output Jan 2007 Computer Architecture, The Arithmetic/Logic Unit Slide 81 12.5 Floating-Point Instructions Floating-point arithmetic instructions for MiniMIPS: add.s sub.d mul.d div.s neg.s 31 F op $f0,$f8,$f10 $f0,$f8,$f10 $f0,$f8,$f10 $f0,$f8,$f10 $f0,$f8 25 ex 20 # # # # # ft set set set set set 15 $f0 $f0 $f0 $f0 $f0 fs to to to to to 10 ($f8) +fp ($f8) –fp ($f8) ×fp ($f8) /fp –($f8) ($f10) ($f10) ($f10) ($f10) fd fn 0 0 0 0 x 1 0 0 0 0 0 0 x x x Floating-point instruction s=0 d=1 Source register Source register Destination register add.* = sub.* = mul.* = div.* = neg.* = Figure 12.7 The common floating-point instruction format for MiniMIPS and components for arithmetic instructions The extension (ex) field distinguishes single (* = s) from double (* = d) operands Jan 2007 Computer Architecture, The Arithmetic/Logic Unit Slide 82 The Floating-Point Unit in MiniMIPS m ≤ 32 Loc Loc Loc B / location Memory Loc Loc m−8 m−4 up to 30 words Coprocessor EIU $0 $1 $2 (Main proc.) $31 ALU Execution & integer unit (Coproc 1) Integer mul/div FP arith Hi FPU $0 $1 $2 Floatingpoint unit $31 Pairs of registers, beginning with an even-numbered one, are used for double operands Lo TMU Chapter 10 Chapter 11 Figure 5.1 Jan 2007 Chapter 12 BadVaddr Trap & (Coproc 0) Status memory Cause unit EPC Memory and processing subsystems for MiniMIPS Computer Architecture, The Arithmetic/Logic Unit Slide 83 Floating-Point Format Conversions MiniMIPS instructions for number format conversion: cvt.s.w cvt.d.w cvt.d.s cvt.s.d cvt.w.s cvt.w.d 31 F op $f0,$f8 $f0,$f8 $f0,$f8 $f0,$f8 $f0,$f8 $f0,$f8 25 ex # # # # # # 20 set set set set set set ft $f0 $f0 $f0 $f0 $f0 $f0 15 to to to to to to fs single(integer $f8) double(integer $f8) double($f8) single($f8,$f9) integer($f8) integer($f8,$f9) 10 fd fn 0 0 0 0 x 0 0 0 0 0 0 0 0 x x x Floating-point instruction Figure 12.8 Jan 2007 *.w = w.s = w.d = *.* = Unused Source register Destination register To format: s = 32 d = 33 w = 36 Floating-point instructions for format conversion in MiniMIPS Computer Architecture, The Arithmetic/Logic Unit Slide 84 Floating-Point Data Transfers MiniMIPS instructions for floating-point load, store, and move: lwc1 swc1 mov.s mov.d mfc1 mtc1 31 F $f8,40($s3) $f8,A($s3) $f0,$f8 $f0,$f8 $t0,$f12 $f8,$t4 op 25 20 ft load mem[40+($s3)] into $f8 store ($f8) into mem[A+($s3)] load $f0 with ($f8) load $f0,$f1 with ($f8,$f9) load $t0 with ($f12) load $f8 with ($t4) 15 fs 10 fd fn 0 0 0 0 x 0 0 0 0 0 0 0 0 1 Floating-point instruction 31 R ex # # # # # # op s=0 d=1 25 rs Unused 20 rt Source register 15 rd Destination register 10 sh mov.* = fn 0 0 0 x 0 1 0 0 0 0 0 0 0 0 Floating-point instruction Figure 12.9 Jan 2007 mfc1 = mtc1 = Source register Destination register Unused Unused Instructions for floating-point data movement in MiniMIPS Computer Architecture, The Arithmetic/Logic Unit Slide 85 Floating-Point Branches and Comparisons MiniMIPS instructions for floating-point load, store, and move: bc1t bc1f c.eq.* c.lt.* c.le.* 31 I L L $f0,$f8 $f0,$f8 $f0,$f8 op 25 20 branch on fp flag true branch on fp flag false if ($f0)=($f8), set flag to “true” if ($f0)