Solution manual micheal d ciletti1

1 Advanced Digital Design with the Verilog HDL Michael D Ciletti ciletti@eas.uccs.edu Copyright 2003, 2004, 2005 M.D Ciletti Selected Solutions Updated: 10/31/2005 Solutions to the following problems are available to faculty at academic institutions using Advanced Digital Design with the Verilog HDL This list will be updated as additional solutions are developed Request the solutions by contacting the author directly (ciletti@eas.uccs.edu) Chapter 2: #1, 2, 3, 4, 5, 8, 9, 10, 12 Chapter 3: #1, 2, 4, 5, 6, 7, 9, 10, 11 Chapter 4: #1, 2, 4, 7, 10, 11, 12, 14, 15, 16 Chapter 5: #1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 13, 16, 17, 18, 19, 20, 23, 24, 26, 27, 28, 29, 30, 32, 33 Chapter 6: #4, #7, 8, 21 Chapter 7: #12 Chapter 9: #12, #18, #19 Copyright 2004, 2005 Note to the instructor: These solutions are provided solely for classroom use in academic institutions by the instructor using the text, Advance Digital Design with the Verilog HDL by Michael Ciletti, published by Prentice Hall This material may not be used in off-campus instruction, resold, reproduced or generally distributed in the original or modified format for any purpose without the permission of the Author This material may not be placed on any server or network, and is protected under all copyright laws, as they currently exist I am providing these solutions to you subject to your agreeing that you will not provide them to your students in hardcopy or electronic format or use them for off-campus instruction of any kind Please email to me your agreement to these conditions I will greatly appreciate your assisting me by calling to my attention any errors or any other revisions that would enhance the utility of these slides for classroom use rev 10/10/2005 www.elsolucionario.net Advanced Digital Design with the Verilog Hardware Description Language Michael D Ciletti Prentice-Hall, Pearson Education, 2003 Problem 2-1 F(a, b, c) = Σ m(1, 3, 5, 7) Canonical SOP form: F(a,b,c) = a'b'c + a'bc + ab'c + abc Also: K-map for F: bc 00 01 11 10 a 0 m0 m4 m1 m5 m3 m7 m2 m6 F' = m0 + m2 + m4 + m6 F' = a'b'c' + a'bc' + a'bc + abc F = (a'b'c' + a'bc' + a'bc + abc)' F = (a'b'c')' (a'bc')' (a'bc)' (abc)' Canonical POS form: F = (a + b + c)(a + b' +c) (a + b' + c') (a' + b' +c') www.elsolucionario.net Advanced Digital Design with the Verilog Hardware Description Language Michael D Ciletti Prentice-Hall, Pearson Education, 2003 Problem 2-2 F(a, b, c, d) = Π M(0, 1, 2, 3, 4, 5, 12) F(a, b, c, d) = (a’+ b’ + c’ + d’)(a’ + b’ + c’ + d)(a’ + b’ + c + d’)(a’ + b’ + c + d)(a’ + b + c’ + d’)(a’ + b + c’ + d)(a + b + c’ + d’) www.elsolucionario.net Advanced Digital Design with the Verilog Hardware Description Language Michael D Ciletti Prentice-Hall, Pearson Education, 2003 Problem 2-3 F(a, b, c) = a'b + c bc 00 01 11 10 a 0 m0 m4 m1 m5 m3 m7 m2 m6 F(a, b, c) = m1 + m2 + m3 + m5 + m7 F(a, b, c) = a'b'c + a'bc' + a'bc + ab'c + abc www.elsolucionario.net Advanced Digital Design with the Verilog Hardware Description Language Michael D Ciletti Prentice-Hall, Pearson Education, 2003 Problem 2-4 F(a, b, c, d) = a'bcd' + a'bcd + a'b'c'd' + a'b'c'd = m6 + m7 + m0 + m1 F(a, b, c, d) = Σ m(0, 1, 6, 7) www.elsolucionario.net Advanced Digital Design with the Verilog Hardware Description Language Michael D Ciletti Prentice-Hall, Pearson Education, 2003 Problem 2-5 G(a, b, c, d) = (a'bcd' + a'bcd + a'b'c'd' + a'b'c'd)' G'(a, b, c, d) = a'bcd' + a'bcd + a'b'c'd' + a'b'c'd K-map for G': cd 00 01 11 10 ab 00 m0 01 m4 11 10 m1 m5 m3 m7 m2 m6 0 0 m12 m13 m15 m14 0 0 m9 m11 m10 m8 G(a, b, c) = Σ m(2, 3, 4, 5, 8, 9, 10 , 11, 12, 13, 14, 15) www.elsolucionario.net Advanced Digital Design with the Verilog Hardware Description Language Michael D Ciletti Prentice-Hall, Pearson Education, 2003 Problem 2-8 (a) (ab’ + a’b)’ = a’b’ + ab (b) (b + (cd’ + e)a’)’ = b’(c’ + d) e’ + a (c) ((a’ + b + c)(b’ + c’)(a + c))’ = ab’c’ + bc + a’c’ www.elsolucionario.net Advanced Digital Design with the Verilog Hardware Description Language Michael D Ciletti Prentice-Hall, Pearson Education, 2003 Problem 2-9 (a) F = a + a’b = a + b (b) F = a(a’ + b) = ab (c) F = ac + bc’ + ab = ac + bc’ www.elsolucionario.net Advanced Digital Design with the Verilog Hardware Description Language Michael D Ciletti Prentice-Hall, Pearson Education, 2003 Problem 2-10a F(a, b, c) = Σ m(0, 2, 4, 5, 6) bc 00 01 11 10 a m0 1 m4 m1 m5 m3 m7 m2 m6 F(a, b, c) = Σ m(0, 2, 4, 5, 6) = ab' + c' www.elsolucionario.net 10 Advanced Digital Design with the Verilog Hardware Description Language Michael D Ciletti Prentice-Hall, Pearson Education, 2003 Problem 2-10b F(a, b, c) = Σ m(2, 3, 4, 5) bc 00 01 11 10 a 0 m0 1 m4 m1 m5 m3 m7 m2 m6 F(a, b, c) = Σ m(2, 3, 4, 5) = ab' + a'b = a ⊕ b www.elsolucionario.net 133 assign Serial_out = Data_Register[0]; always @ (negedge clock, posedge reset) if (reset) Data_Register