5 D C B 01_BLOCK DIAGRAM 02_SCH GPIO Setting 03_EC Pin Define 04_Power Sequrnse DC 05_Power Sequence AC 06_Power Sequence Description 07_Clock Gen_ICS9LPR427 08_CPU-SILVERTHORNE (1) 09_CPU-SILVERTHORNE (2) 10_CPU-SILVERTHORNE (3) 11_SCH_Poulsbo_HOST (1) 12_SCH_Poulsbo_DDR2 (2) 13_SCH_Poulsbo_LVDS/SDVO (3) 14_SCH_Poulsbo_PM/USB/IDE/AZ (4) 15_SCH_Poulsbo_STRAP(5) 16_SCH_Poulsbo_POWER (6) 17_SCH_Poulsbo_GND (7) 18_DDR2_SODIMM 19_DDR2_Termination 20_CH7317_SDVO_CRT 21_Onboard VGA 22_LCD Conn_LID 23_3.5G 24_Mini WIFI 25_Bluetooth_BT253 26_FAN_THERMAL SENSOR 27_LAN_Atheros AR8113/AR8132 28_RJ45 29_Small brd Conn 30_PATA TO SATA 31_USB Port 32_EC_ENE KB3310 33_SPI ROM_Debug Conn 34_Reset Map 35_KB_Touch Pad 36_ 37_Discharge 38_PWR Jack 39_Screw Hole 40_EMI 41_Power Flow 42_Vcore 43_Power System 44_Power_+1.8V & VTTDDR 45_Power_VCCP 46_Power_+1.5VS & +2.5VS 47_Charger 48_Power_Load Switch 49_Power Latch 50_HISTORY http://hobi-elektronika.net 1101HA Block Diagram (Silverthorne / Poulsbo) D CPU Clock Generator Silverthorne ICS ICS9LPRS427 Page 29 Page 4~5 FSB 533MHz LVDS Page 45 DDR2 SDVO CH7317A CRT DDR-II So-DIMM Page 7~9 SCH C POULSBO Small-Board 100M LAN Realterk ALC269 WLAN MiniCard PCIE X1 PATA INT DMIC Speaker MIC Jack HP Jack RJ-45 AR8132 Azalia Azalia Codec Page 10~15 JMH330 Debug Conn USB Port *2 CMOS SATA HDD ࣩ࣭࣠ EC ENE KBC3310 SPI ROM B Internal KB Touch Pad USB 2.0 3G MiniCard Cardreader AU6336 USB Port *1 Bluetooth A A Title : Block Diagram ASUSTeK COMPUTER INC Size Project Name Custom Engineer: Rev 1101HA 1.2 Date: Tuesday, July 21, 2009 N/A Sheet 1 of 50 D http://hobi-elektronika.net SCH GPIO SETTING Pin C Pin Name D Connect to Type Power Well S3 S4/ S5 Input/Output Set U41 GPIOSUS0 PM_LEVELDOWN# I/O CMOS3.3 Sus VIX-unknown OFF Output N43 GPIOSUS1 CPU_LEVELDOWN I/O CMOS3.3 Sus VIX-unknown OFF Output N45 GPIOSUS2 PM_PWRBTN# I/O CMOS3.3 Sus VIX-unknown OFF Input R41 GPIOSUS3/ USBCC +VCCP_OV0 I/O CMOS3.3 Sus VIX-unknown OFF output G29 GPIO0 Strap CMC/ BT_Disable I/O CMOS3.3 Core OFF OFF Input K30 GPIO1 CARD_READER_EN# I/O CMOS3.3 Core OFF OFF Output F34 GPIO2 SIMCARD_IN# I/O CMOS3.3 Core OFF OFF iutput G33 GPIO3 Strap CMC I/O CMOS3.3 Core OFF OFF Input K36 GPIO4 3GLAN_OFF I/O CMOS3.3 Core OFF OFF Output H36 GPIO5 MINICARD_EN# I/O CMOS3.3 Core OFF OFF Output F36 GPIO6 DDR_MEM_CONFIG I/O CMOS3.3 Core OFF OFF Input J31 GPIO7/ SLPIOVR# SLPIOVR# I/O CMOS3.3 Core OFF OFF Output H34 GPIO8/ PROCHOT# CAMERA_EN I/O CMOS3.3/ OD Core OFF OFF Output K28 GPIO9/ EXTTS1# WLAN_LED I/O CMOS3.3 Core OFF OFF Output C B B A A Title : SCH GPIO Setting ASUSTek Computer INC Size A3 Engineer: Rev 1101HA 1.2 Date: Tuesday, July 21, 2009 N/A Project Name Sheet of 50 http://hobi-elektronika.net EC KB3310 GPIO SETTING Pin Pin Name Signal Name GPIO00/GA20 A20GATE GPIO01/KBRST# 13 14 Type Note EC KB3310 Other Pin SETTING Pin Pin Name Signal Name Pin Pin Name Signal Name O 70 GPO3D/DA1 LCD_BACKOFF# O SERIRQ INT_SERIRQ I/OD RC_IN# O 71 GPO3E/DA2 THRO_CPU_VOLT# O LFRAME# LPC_FRAME# I GPIO04 HOTKEY_SW0# I GPIO05/PCIRST# BUF_RST# I GPIO07 HOTKEY_SW1#(no use) I Internal pull high Type Note Type 72 GPO3F/DA3 BAT_LL# O Battery Low Low LAD3 LPC_AD3 I/O 73 GPIO40 AC_OK I AC Adaptor Plug in LAD2 LPC_AD2 I/O 74 GPIO41 PM_RSMRST# O 10K pull down to GND LAD1 LPC_AD1 I/O Note 10K pull high to +3V D C B A D Batt1 (Small/Internal): 1-present, 0-absent Batt2 (Small/Internal): 1-present, 0-absent VCC +3VA P 10 LAD0 LPC_AD0 I/O 4.7K pull high to +3VA_EC 11 GND GND P I/OD 4.7K pull high to +3VA_EC 12 PCICLK CLK_PCI_EC I SMB1_CLK I/OD 10K pull high to +3V 22 VCC +3VA P GPIO47/SDA2 SMB1_DAT I/OD 10K pull high to +3V 24 GND GND P 81 GPIO48/KSO16 KB_ID0 I for KB type detection 33 VCC +3VA P Battery critical capacity 82 GPIO49/KSO17 KB_ID1 I for KB type detection 35 GND GND P OD Internal pull high in ICH 83 GPIO4A/PSCLK1 N.C O 37 ECRST# EC_RST# I FAN0_PWM O CPU Fan 84 GPIO4B/PSDAT1 CRT_IN I 67 AVCC +3VA_AEC P 15 GPIO08 EXT_SMI# OD 10K pull high to +3VSB 75 GPI42 BAT_IN I 16 GPIO0A LID_EC_R# I Internal pull high 76 GPI43 BAT2_IN I 17 GPIO0B/ESB_CLK PCB_ID0 I 77 GPIO44/SCL1 SMB0_CLK I/OD 18 GPIO0C/ESB_DAT PCB_ID1 I 78 GPIO45/SDA1 SMB0_DAT 19 GPIO0D LID_EC_L#(no use) I Internal pull high 79 GPIO46/SCL2 20 GPIO0E/SCI# KBC_SCI# O 10K pull high to +3VSB 80 21 GPIO0F/PWM0 BL_PWM_DA O 23 GPIO10/PWM1 BATSEL# I 25 GPIO11/PWM2 PM_PWRBTN# 26 GPIO12/FANPWM1 27 GPIO13/FANPWM2 FAN1_PWM O VGA Fan 85 GPIO4C/PSCLK2 CRT_DACPWR_EN# O 69 AGND AGND P 28 GPIO14/FANFB1 FAN0_TACH I CPU FanTach 86 GPIO4D/PSDAT2 CRTDAC_RST# O 94 GND GND P 29 GPIO15/FANFB2 FAN1_TACH I VGA FanTach 87 GPIO4E/PSCLK3 TP_CLK I/OD 10K pull high to +3V 96 VCC +3VA P 30 GPIO16/E51_TX E51_TX O RS232 debug port 88 GPIO4F/PSDAT3 TP_DAT I/OD 10K pull high to +3V 111 VCC +3VA P 31 GPIO17/E51_RX E51_RX I RS232 debug port 89 GPIO50/SELIO# CHG_LED_GREEN# O Green charger LED 113 GND GND P Orange charger LED 32 GPIO18 PWR_SW# I Internal pull high 90 GPIO52/E51_CS# CHG_LED_UP# O 119 RD#/SPIDI SPI_SO I 34 GPIO19/PWM3 PS-ON O latch power 91 GPIO53/CAPLED CAP_LED# O 120 WR#/SPIDO SPI_SI O 36 GPIO1A/NUMLED NUM_LED# O 92 GPIO54 PWR_LED_UP O 122 XCLKI K_XCLKI I 38 GPIO1D/CLKRUN# LPC_CLKRUN# O 93 GPIO55/SCRLED SCRL_LED# O 123 XCLKO K_XCLKO O 39 GPIO20/KSO0/TP_TEST KSO0 O 95 GPIO56 GS1_INT1(no use) I Internal pull high 124 V18R V18R P 40 GPIO21/KSO1/TP_PLL KSO1 O 97 GPXOA00/SDICS# SPI_MODE# O 4.7K pull down to GND 125 VCC +3VA P 41 GPIO22/KSO2 KSO2 O 98 GPXOA01/SDICLK SUSC_ON O 128 SPICS#/SELMEM# SPI_CS# O 42 GPIO23/KSO3 KSO3 O 99 GPXOA02/SDIDO VSUS_ON O 43 GPIO24/KSO4 KSO4 O 100 GPXOA03 CPU_VRON O 44 GPIO25/KSO5 KSO5 O 101 GPXOA04 SUSB_ON O 45 GPIO26/KSO6 KSO6 O 102 GPXOA05 CNT1_CHG# O batt1 (Big/External) charging enabled Batt1 is discharging priority in AC mode 46 GPIO27/KSO7 KSO7 O 103 GPXOA06 CNT1_DIS# O batt1 discharging enabled 47 GPIO28/KSO8 KSO8 O 104 GPXOA07 CNT2_CHG# O 48 GPIO29/KSO9 KSO9 O 105 GPXOA08 CNT2_CHG# O 49 GPIO2A/KSO10 KSO10 O 106 GPXOA09 SPI_WP# O 50 GPIO2B/KSO11 KSO11 O 107 GPX0A10 OP_SD# O 51 GPIO2C/KSO12 KSO12 O 108 GPXOA11 BAT_LEARN O 52 GPIO2D/KSO13 KSO13 O 109 GPXID0/SDIDI PM_PWROK O 53 GPIO2E/KSO14 KSO14 O 110 GPXID1 RST# O Battery parallel, H:1P, L:2P~3P GPIO2F/KSO15 KSO15 O 112 GPXID2 THRO_CPU O Active if CPU temperature over spec KSI0 I Internal pull high 114 GPXID3 PM_SLPRDY# I SLPRDY#,100K pull down to GND 56 GPIO31/KSI1 KSI1 I Internal pull high 115 GPXID4 SLPMODE I SUSC#,100K pull down to GND 57 GPIO32/KSI2 KSI2 I Internal pull high 116 GPXID5 VRM_PWRGD I Pull high to +3V 58 GPIO33/KSI3 KSI3 I Internal pull high 117 GPXID6 PM_RSTRDY# I KSI4 I Internal pull high 118 GPXID7 RSTWARN O GPIO35/KSI5 KSI5 I Internal pull high 121 GPIO57 GS1_INT2(no use) I 61 GPIO36/KSI6 KSI6 I Internal pull high 126 GPIO58/SPICLK SPI_CLK O 62 GPIO37/KSI7 KSI7 I Internal pull high 127 GPIO59/TEST_CLK GS2_INT1(no use) O 63 GPI38/AD0 BAT_A I 64 GPI39/AD1 BAT_B I 65 GPIO3A/AD2 BAT_C I 66 GPIO3B/AD3 BAT_D I 68 GPO3C/DA0 CHG_EN# O B Audio OP GPIO30/KSI0 GPIO34/KSI4 Reserved 1uF to GND batt2 (Big/External) charging enabled Batt2 is discharging priority in AC mode 54 59 C batt2 discharging enabled 55 60 100K pull high to +3VA_EC Internal pull high A Title : EC Pin Define ASUSTek Computer INC Size battery charger enabled A3 Engineer: Rev 1101HA 1.2 Date: Tuesday, July 21, 2009 N/A Project Name Sheet of 50 http://hobi-elektronika.net LDO AC_BAT_SYS +5VA +5VA AC_BAT_SYS BAT MB39A Battery +3VSUS VSUS_ON D SUSC_ON +5VSUS VSUS_PWRGD BAT1_IN VSUS_ON H H S4/S5 12 Power Adapter H Battery L H L L Main SUSC_ON H H L DUAL SUSB_ON AC_BAT_SYS UP6111 SUSB_ON > 5ms 12 15 CPU_VRON VSUS_ON 16 ENE KB3310 D SI7326 +5VS EN 13 SI7326 +3V EN 10 14 UP7711 13 UP7704 EN +3VS VTT_DDR 13 EN 13 +1.5VS SUSC_ON 12 SUSB_ON +3VS +3V Vccp_PWRGD EN 12 SI7326 EN +2.5VS SUSB_ON 12 12 C 13 UP7704 EN VRM_PWRGD 19 > 5ms SUSC_ON BUF_RST# > 100us 24 S0/S1 > 5ms S3 21 23 +5VA +3VA +3VSUS +5VSUS +1.8V +3V +5V V V V V V V V V V V V V V V V V AC_BAT_SYS Vccp +1.5V H_PWRGD 22 +VCC_RTC 25 CLK_REF_SCH 15 H_CPURST# SLIVERTHORNE VCORE 18 15 RST# CLK_PCIE_SCH Intel SCH CLK_96M_UMA 15 15 +3VSUS 14 VRM_PWRGD 19 H_PWRGD +5VSUS 24 +3VSUS CLK_LCD_LVDS +5VS BUF_RST# BUFFER 23 15 +3VS 19 CLK_BCLK_CPU 15 +1.8V VRM_PWRGD 26 CLK_BCLK_SCH +1.5VS 16 B 15 Vccp CPU_VRON MAX8796 VID[6:0] 17 CLK_PCI_SCH BATT VTT_DDR Vccp +1.5VS +3VS +5VS +2.5VS V V V V V V - RST# RST# 20 PM_RSTRDY# PM_RSMRST# PM_PWRBTN# 11 PM_RSTWARN EC_PWROK S4/S5 13 +1.8V CLK_PCI_EC PWR_SW# + 12 Vccp +3VA 10 +3VSUS B SUSC_ON 9 SUSB_ON C 1.8V_PWRGD EN +5V +3VSUS 10 UP6111 SUSC_ON SUSB_ON +1.8V AC_BAT_SYS VSB SI7326 EN +5VSUS SUSB_ON Signal S0/S1 S3 +5VSUS RT8205 +3VA G923 15 Vccp_PWRGD 26 A 15 15 PCIE CLK 100M SCH MINICARD LAN 15 REF CLK 14M ICH 25 H_CPURST# FSB CLK 100M CPU MCH ITP PCI CLK 33M SCH EC DEBUG ICS9LPR426 A 15 UMA CLK 96M SCH LVDS CLK 100M MCH Title : Power Sequence DC 15 ASUSTek Computer INC Size A3 Engineer: Rev 1101HA 1.2 Date: Tuesday, July 21, 2009 N/A Project Name Sheet of 50 http://hobi-elektronika.net A/D_DOCK_IN Adapter LDO AC_BAT_SYS AC_BAT_SYS MB39A +5VA RT8205 VSUS_ON H H S4/S5 SUSC_ON Adapter H Battery L UP6111 SUSC_ON H L L Main SUSC_ON H H L DUAL SUSB_ON 16 10 EN UP7111 13 EN 13 UP7704 EN +3VS VTT_DDR 13 EN +3VS SI7326 +1.5VS SUSC_ON SUSB_ON 12 12 C UP7704 VTT_DDR 13 EN > 5ms 19 BUF_RST# > 100us 24 S0/S1 S3 21 23 +5VA +3VA +3VSUS +5VSUS +1.8V +3V +5V V V V V V V V V V V V V V V V V V V AC_BAT_SYS Vccp +1.5V H_PWRGD 22 +VCC_RTC 25 CLK_REF_SCH 15 H_CPURST# SLIVERTHORNE VCORE 18 15 RST# CLK_PCIE_SCH Intel SCH CLK_96M_UMA 15 15 +3VSUS 14 VRM_PWRGD 19 H_PWRGD +5VSUS BUF_RST# 24 +3VSUS CLK_LCD_LVDS +5VS BUFFER 23 15 +3VS 19 CLK_BCLK_CPU 15 +1.8V VRM_PWRGD 26 CLK_BCLK_SCH +1.5VS 16 B 15 Vccp CPU_VRON MAX8796 VID[6:0] 17 CLK_PCI_SCH BATT VTT_DDR Vccp +1.5VS +3VS +5VS +2.5VS V V V V V V - RST# RST# 20 PM_RSTRDY# PM_RSMRST# PM_PWRBTN# 11 PM_RSTWARN EC_PWROK S4/S5 + +3V SI7326 VRM_PWRGD SUSC_ON B 14 12 SUSB_ON ENE KB3310 13 EN +3V Vccp_PWRGD EN +1.8V CPU_VRON PWR_SW# 13 12 15 12 Vccp CLK_PCI_EC VSUS_ON SUSB_ON UP6111 12 SUSC_ON 1.8V_PWRGD D +5VS SI7326 +3VSUS C 10 EN +3VSUS AC_BAT_SYS SUSB_ON > 5ms +3VA +1.8V 10 EN AC_OK BAT_IN SUSB_ON 12 AC_BAT_SYS VSB +5V SI7326 +5VSUS SUSB_ON Power +5VSUS +5VSUS VSUS_PWRGD Signal S0/S1 S3 +3VA G923 +3VSUS Battery +5VA VSUS_ON BAT D 15 Vccp_PWRGD 26 A 15 15 PCIE CLK 100M SCH MINICARD LAN 15 REF CLK 14M ICH 25 H_CPURST# FSB CLK 100M CPU MCH ITP PCI CLK 33M SCH EC DEBUG ICS9LPR426 A 15 UMA CLK 96M SCH LVDS CLK 100M MCH Title : Power Sequence AC 15 ASUSTek Computer INC Size A3 Engineer: Rev 1101HA 1.2 Date: Tuesday, July 21, 2009 N/A Project Name Sheet of 50 S4/S5 to S0(Adapter Mode) D http://hobi-elektronika.net This sequence will occur whenever the system is in S4/S5 and the EC initiates a sleep exit sequence from S4/S5 to S0 Initial EC state: VSUS_ON=0, SUSB_ON=0, SUSC_ON=0, A20GA=X, KBRST=X, CPU_VRON=0, ICH_PWROK=0, RSTWARN=0, and PM_RSMRST#=0, RESET#=0 Initial EC state: VSUS_ON=0, SUSB_ON=0, SUSC_ON=0, A20GA=X, KBRST=X, CPU_VRON=0, ICH_PWROK=0, RSTWARN=0, and PM_RSMRST#=0, RESET#=0 2.At least 5mS after AC_OK is asserted, EC asserts VSUS_ON to enable VSUS power 3.At least 20mS after VSUS power is stable, waiting for PWR_SW# until user is pressed (Or waiting for SCH deasserted SLPRDY#, too?) 4.EC asserts RSTWARN 5.SUSC_ON is asserted at least 20mS (de-bounce) after receiving PWR_SW# 6.PM_RSMRST# is deasserted at least 5mS after SUSC power is stable 7.At least 5mS after PM_RSMRST# is deasserted, SUSB_ON is enabled 8.CPU_VRON is deasserted at least 100mS after SUSB power is stable 9.Waiting for CPUPWR_GD (VRM_PWRGD) until CPU_VRON power is stable 10.At least 10mS after receiving CPUPWR_GD, PM_PWROK is asserted, and then deasserts RSTWARN 1.Waiting for BAT_IN until battery power is good, then S0 to S3/S4/S5 This sequence will occur when system entry to sleep states, or all power planes are shut down Initial EC state: VSUS_ON=1, SUSB_ON=1, SUSC_ON=1, CPU_VRON=1, ICH_PWROK=1, and PM_RSMRST#=1, RESET#=1, RSTWARN=0, PM_PWRBTN#=1 D 1.Waiting for PWR_SW# until user is pressed (go to 2), or waiting for SLPRDY# is asserted (go to 3) 2.Waiting for PWR_SW# until user is pressed 2.At least 20mS after PWR_SW# is asserted, EC asserts PM_PWRBTN# (50mS width) to SCH 3.EC asserts VSUS_ON to enable VSUS power 3.Waiting for SLPRDY# until has been asserted 4.At least 20mS after VSUS power is stable 4.EC asserts RSTWARN to SCH to begin internal sequence 5.EC asserts RSTWARN 5.SCH asserts RSTRDY# to EC to indicate all outstanding transactions are completed 6.SUSC_ON is asserted at least 20mS (de-bounce) after receiving PWR_SW# 6.EC asserts RESET# after detecting RSTRDY# asserted 7.PM_RSMRST# is deasserted at least 5mS after SUSC power is stable 8.At least 5mS after PM_RSMRST# is deasserted, SUSB_ON is enabled 9.CPU_VRON is deasserted at least 10mS after SUSB power is stable 10.Waiting for CPUPWR_GD (VRM_PWRGD) until CPU_VRON power is stable 11.At least 10mS after receiving CPUPWR_GD, PM_PWROK is asserted, and then deasserts RSTWARN 12.Waiting for RSTRDY# until deasserted by SCH 11.Waiting for RSTRDY# until deasserted by SCH 7.EC deasserts ICH_PWROK 8.EC deasserts SUSB_ON and CPU_VRON to turn off power planes C This completes the entry to S3 (SLPMODE=1) If SLPMODE=0, this indicates S4/S5 was the desired state, EC takes additional actions: 9.EC asserts PM_RSMRST# 10.EC deasserts SUSC_ON to turn off the other power planes 11.EC deasserts VSUS_ON if in battery mode 12.EC deasserts RSTWARN to save more power 12.RESET# can be deasserted at lease 100uS after PM_PWROK is asserted Power Sequence Description: S3 to S0 13.RESET# can be deasserted at lease 100uS after ICH_PWROK is asserted This sequence will occur in S3, and wake event is detected by EC or SCH The warm reset sequence results in reset without remove any power supplies Initial EC state: SUSB_ON=0, CPU_VRON=0, ICH_PWROK=0, PM_RSMRST#=1, PM_PWRBTN#=1, and VSUS_ON=1, RSTWARN=1, SUSC_ON=1, RESET#=0 Initial EC state: SUSB_ON=1, CPU_VRON=1, ICH_PWROK=1, PM_RSMRST#=1, PM_PWRBTN#=1, and VSUS_ON=1, RSTWARN=1, SUSC_ON=1, RESET#=1 1.For internal wake event, SCH deasserts SLPRDY# to EC, than 1.SCH asserts RSTRDY# at the same time as driving SLPMODE=1 to EC 2.For external wake event (PWR_SW#, keyboard wake up), then 2.EC asserts RSTWARN to SCH 3.EC asserts PM_PWRBTN# at least 50mS to wake SCH, and waiting for SLPRDY# until SCH deasserted 3.EC asserts RESET# for 1200mS to SCH after asserts RSTWARN 4.EC deasserts RSTWARN 4.EC asserts SUSB_ON to enable SUSB power 5.CPU_VRON is deasserted at least 100mS after SUSB power is stable Cold Reset (SLPMODE=0) Warm Reset (SLPMODE=1) B The cold reset sequence results in a power cycling of all but the RTC power well B Initial EC state: SUSB_ON=1, CPU_VRON=1, ICH_PWROK=1, PM_RSMRST#=1, PM_PWRBTN#=1, and VSUS_ON=1, RSTWARN=1, SUSC_ON=1, RESET#=1 1.SCH asserts RSTRDY# at the same time as driving SLPMODE=0 to EC 2.EC asserts RSTWARN to SCH 5.EC deasserts RESET# after at least 100uS delay from RSTWARN 3.EC asserts RESET# to SCH after asserts RSTWARN 4.EC deasserts PM_PWROK and disables SUSB_ON and CPU_VRON power 5.EC asserts PM_RSMRST# after CPU_VRON power is off 6.EC disables SUSC_ON power for 3~5 seconds 7.S4/S5 to S0 sequence is automatically followed to bring the system back to S0 when SUSC_ON power is enable 6.Waiting for CPUPWR_GD (VRM_PWRGD) until CPU_VRON power is stable A S4/S5 to S0(Battery Mode) This sequence will occur whenever the system is in S4/S5 and the EC initiates a sleep exit sequence from S4/S5 to S0 1.Waiting for AC_OK until adaptor power is good, then C 7.At least 5mS after receiving CPUPWR_GD, ICH_PWROK is asserted A 8.Deasserts RSTWARN after ICH_PWROK is asserted 9.RESET# can be deasserted 100uS after RSTWARN is deasserted Power Sequence Description Title : Engineer: ASUSTeK COMPUTER INC Size Custom Rev 1101HA Date: Tuesday, July 21, 2009 N/A Project Name 1.2 Sheet of 50 http://hobi-elektronika.net +3VS +3V_CLK CL3 CR1 1MOhm /X 1 T34 120Ohm/100Mhz l0603 +3V_CLK_VDDA CX1 3/31 item14 GND D CC12 0.1UF/16V +3VS CC10 120Ohm/100Mhz 0.1UF/16V l0603 1 CC9 0.1UF/16V CC8 0.1UF/16V CC6 0.1UF/16V CC5 0.1UF/16V CC4 0.1UF/16V CC3 0.1UF/16V CC2 0.1UF/16V 1 CC1 10uF/10V /X c0805 120Ohm/100Mhz l0603 /X 1 CC14 27PF/50V 2 CC13 27PF/50V CL2 CL1 14.318Mhz +3V CLK_XOUT D 2 CLK_XIN GND PCI_STOP# GND 1:Disable 0:Enable STP_CPU# +3V_CLK_VDDA 22PF/50V +3V_CLK +3V_CLK 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 GND CLK_PEREQ#1 CLK_PEREQ#2 CLK_FS4 [14] CLK_PEREQ#1 [24] CLKREQ#_MINICARD 4/29 item1 CR4 CLK_ITP_EN CLK_SEL_48# 33Ohm [42,45] VCCP_PWRGD CLK_FSLA CRN12A CRN12B CLK_FSLB CR5 CR6 CRN13A CRN13B [14] CLK_96M_UMA [14] CLK_96M_UMA# [14] [14] [13] [13] CLK_LCD_LVDS CLK_LCD_LVDS# CLK_PCIE_SCH CLK_PCIE_SCH# CRN14A CRN14B [24] CLK_PCIE_MINICARD [24] CLK_PCIE_MINICARD# /X/RF EC47 CLK_96M CLK_96M# 0Ohm 0Ohm 0OHM 0OHM 0OHM 0OHM CLK_LCD CLK_LCD# CLK_PCIE1 CLK_PCIE#1 CLK_PCIE2 CLK_PCIE#2 EC46 22PF/50V /X/RF CR11 VDD1 25MHz GND1 PCI&PCIEX_STOP# PEREQ1# CPU_STOP# PEREQ2# REF0/FSLC FS4/PCICLK0 DOC_PEREQ3#/SELDOC# GND2 GND4 VDDPCI X1 ITP_EN/PCICLK_F0 X2 SEL12_48#/12_48MHz VDDREF Vtt_PwrGd/PD# SDATA VDD2 SCLK FSLA/USB_48MHz GND5 GND3 CPUT_LR0 DOTT_96MHzLR CPUC_LR0 DOTC_96MHzLR VDDCPU FSLB CPUT_LR1 PCIeT_LR0 CPUC_LR1 PCIeC_LR0 RESET# PCIeT_LR1 GNDA PCIeC_LR1 VDDA VDDPCIEX1 CPUITPT_LR2/PCIeT_LR6 PCIeT_LR2 CPUITPC_LR2/PCIeC_LR6 PCIeC_LR2 VDDPCIEX3 PCIeT_LR3 PCIeT_LR5 PCIeC_LR3 PCIeC_LR5 SATACLKT_LR PCIeT_LR4 SATACLKC_LR PCIeC_LR4 VDDPCIEX2 GND6 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CLK_FSLC CLK_PEREQ#3 221Ohm CR12 PCI_STOP# STP_CPU# CLK_25M_LAN [27] 22Ohm [14] CR3 CLK_25M_SATA [30] 33Ohm CLK_SCH14 CLK_PEREQ#1 CRN1D 10KOhm CLK_PEREQ#2 10KOhm CRN1C CLK_PEREQ#3 CRN1A 10KOhm [14] CLK_PEREQ#3 [27] C CLK_XIN CLK_XOUT VDDREF +3V_CLK S_SMB_DATA [14] S_SMB_CLK [14] CLK_BCLK0 CRN16A CLK_BCLK#0 CRN16B 0OHM 0OHM CLK_BCLK_CPU [8] CLK_BCLK_CPU# [8] CLK_BCLK1 CRN15A CLK_BCLK#1 CRN15B 0OHM 0OHM CLK_BCLK_MCH [11] CLK_BCLK_MCH# [11] CLK_BCLK2 CRN17A CLK_BCLK#2 CRN17B 0OHM 0OHM /ITP /ITP CLK_BCLK_ITP [8] CLK_BCLK_ITP# [8] CLK_ITP_EN 8.2KOhm CRN2A CLK_SEL_48# 8.2KOhm CRN2B GND +3V_CLK CLK_PCIE4 CLK_PCIE#4 ICS9LPRS427AGLF 06G011552010 CRN18A CRN18B 0OHM 0OHM CLK_PCIE_LAN [27] CLK_PCIE_LAN# [27] CLK_FS4 CR7 8.2KOhm CR8 8.2KOhm /X 3/26 item7 FOR RF 22PF/50V EC45 22PF/50V 0OHM 0OHM CLK_96M_UMA CLK_96M_UMA# 22PF/50V /X/RF /X/RF CLK_LCD_LVDS CLK_LCD_LVDS# EC41 +3V_CLK EC35 CU1 [29] CLK_48M_READER 10KOhm PEREQ1:PCIEx0 & PCIEx1 PEREQ2:PCIEx2 & PCIEx3 & SATA PEREQ3:PCIEx4 & PCIEx5 & PCIEx6 CLK_SEL_48# C CR2 CRN1B 10KOhm GND GND GND B +3V_CLK FSB FSA CPU PCIE 0 133 100 1 100 100 CC15 10PF/50V S_SMB_CLK CC16 10PF/50V CLK_SCH14 CC17 10PF/50V CLK_25M_LAN CC23 CLK_25M_SATA CC24 10PF/50V /X 10PF/50V /X B CL4 VDDREF 2 8.2KOhm FSC +3V_CLK CRN2C CR9 8.2KOhm /X CLK_FSLB CC7 120Ohm/100Mhz /RF l0603 0.1UF/16V GND CLK_FSLA S_SMB_DATA +3V_CLK GND GND 3/26 item7 FOR RF CC25 0.1UF/16V /RF GND CLK_FSLC RF solution GND CRN2D 8.2KOhm CR10 A A 8.2KOhm GND GND Title : Clock Gen_ICS9LPRS427 ASUSTek Computer INC Size A3 Date: Engineer: N/A Project Name Rev 1101HA 1.2 Sheet Tuesday, July 21, 2009 of 50 http://hobi-elektronika.net [11] [11] [11] [11] [11] GND H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 +VCCP_C6 +3VA +VCCP_C6 +3VS [11] H_ADSTB#1 R8 1KOhm H_INIT# H_A20M# [11] R199 10KOhm 1 H_IGNNE# [11] H_STPCLK# [11] H_INTR [11] H_NMI [11] H_SMI# Q2A UM6K1N A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# ADSTB[1]# G30 J28 H27 A20M# FERR# IGNNE# K1 H31 L28 J26 STPCLK# LINT0 LINT1 SMI# AE16 AF17 AD15 AD17 D9 D7 E8 E10 L30 J30 +VCCP_C6 Q2B UM6K1N RC_IN# H_PBE# B5 A12 D5 E12 B9 A6 B13 E14 A10 B7 D13 A8 C4 A14 B11 D11 3/26_Item5 R200 10KOhm /X [32] R7 1KOhm C REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# GND KBRST# Level Shift K29 RSVD7 RSVD8 RSVD9 RSVD10 RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 H_DEFER# [11] H_DRDY# [11] H_DBSY# [11] H1 F31 LOCK# D25 RESET# RS[0]# RS[1]# RS[2]# TRDY# M5 D27 E28 E26 F25 HIT# HITM# E30 F29 BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# RSVD14 F1 E2 F5 D3 E4 F7 L2 N2 M1 P1 J4 G26 H_BPM#0 H_BPM#1 H_BPM#2 H_BPM#3 H_BPM#4 H_BPM#5 H_TCK H_TDI H_TDO H_TMS H_TRST# PROCHOT# THRMDA THRMDC H5 T5 U4 H_PROCHOT_R# THERMTRIP# T1 PM_THRMTRIP# H_BR0# H_IERR# H_INIT# +VCCP H_INIT# H_RS#0 H_RS#1 H_RS#2 H_TRDY# [11] [11] [11] [11] [11] +VCCP T29 R3 56OHM H_CPURST# H_PBE# /X +VCCP_C6 CMOS Rreference Voltage Level R9 1KOhm 1% CPU_CMREF T213 [26] [26] C C2 0.1UF/16V GND P29 R28 VSS0 K31 R11 1KOhm 1% GND CLK_BCLK_CPU [7] CLK_BCLK_CPU# [7] R10 0Ohm /X +VCCP_C6 RSVD11 RSVD6 A26 E6 RSVD15 TEST4 G28 U30 TEST3 CMREF[1] RSVD13 V27 AE26 T3 T209 T4 H_BPM#5 CPU_CMREF HR1 56OHM +VCCP H_TDO H_STPCLK# S [11] [11] H_THERMDA H_THERMDC BCLK[0] BCLK[1] D GND H_CPURST# Z530 : 01G011980000 Z520 C0 stage : 01G012610200 2 3/27_Item14 Q19 2N7002 [11] GND R14 56OHM G H_LOCK# [11] H_HIT# H_HITM# D 11 [11] +VCCP_C6 R13 1KOhm 1% /X 3 INT441 01G011980000 B +VCCP R2 1KOhm 1% H_CPURST_R# H_RS#0 H_RS#1 H_RS#2 H_PROCHOT_R# [11] [32] THRO_CPU C28 ADDR GROUP H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 A20M# Level Shift B25 D23 E20 A24 B21 B27 W28 D29 A20GATE DEFER# DRDY# DBSY# BR0# R15 56OHM [11] [11] Q1B UM6K1N [32] [11] H_ADSTB#0 H_ADS# H_BNR# H_BPRI# C26 H25 G24 IERR# INIT# 3/27_Item14 Q1A UM6K1N +VCCP T1 ADS# BNR# BPRI# CONTROL R198 10KOhm /X H_A20M# XDP/ITP SIGNALS R197 10KOhm THERM D HCLK H_A#[31 3] [11] A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# NC +3VS E22 A22 D21 E24 B17 A18 B23 A16 E18 D15 B19 A20 D17 B15 D19 ADDR GROUP H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 Processor Hot THRO_CPU : H : throttle ON THRO_CPU : L : throttle OFF U1A R1 1KOhm 1 +VCCP_C6 +3VA 2 HR2 56OHM H_TMS HRN1A 56OHM H_TDI HRN1B 56OHM H_TCK HRN1C 56OHM H_TRST# HRN1D 56OHM +VCCP ITP1 31 11 13 15 17 19 21 23 25 27 29 32 [7] CLK_BCLK_ITP# [14,18] SMB_CLK H_TCK +VCCP 3/27_Item14 H_TDO H_BPM#0 H_BPM#2 H_BPM#4 R16 56OHM HR4 [9,11] A PM_THRMTRIP# H_PWRGD ITP_PWRGD 1KOhm /ITP PM_THRMTRIP#_R [10,11] GND GND SIDE1 SIDE4 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SIDE2 SIDE3 FPC_CON_30P /ITP 12-183303002 34 10 12 14 16 18 20 22 24 26 28 30 33 JTAG Interface When ITP/XDP is not Implemented CLK_BCLK_ITP [7] SMB_DATA [14,18] ITP_CPURST# H_TMS H_TDI HR3 1KOhm /ITP H_CPURST# CLK_BCLK_CPU C459 10PF/50V /X CLK_BCLK_CPU# C460 10PF/50V /X H_BPM#1 H_BPM#3 H_BPM#5 H_TRST# A GND GND Title : CPU-SLIVERTHORNE(1) ASUSTeK COMPUTER INC ITP Connector For Debug Size Custom Engineer: N/A Project Name Rev 1101HA 1.2 Date: Tuesday, July 21, 2009 B /ITP Sheet of 50 D D GTL_REF T214 T215 T5 T6 T7 1 1 AJ26 P31 T31 R30 M31 U28 GTLREF COMP[0] COMP[1] MISC COMP[2] COMP[3] TEST1 TEST2 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# RSVD12 BSEL[0] BSEL[1] BSEL[2] H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 AH5 AB5 AJ6 Y1 AF5 AG4 AF3 AC6 AE6 AE4 W4 AC2 AE2 AD1 AA2 AC4 AB1 AA4 Y5 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 AE14 AD13 E16 F15 H_COMP0 H_COMP1 H_COMP2 H_COMP3 G2 G6 V31 G4 J2 K27 H_D#[63:0] H_D#[63:0] [11] +VCCP_C6 Near CPU H_DSTBN#2 [11] H_DSTBP#2 [11] H_DINV#2 [11] R18 1KOhm 1% 9A T ss = ms C total = 20 uF I inrush =3.6 mA Power Dissipation: OVP: +1.8V@3A EN Voltage: V en = 1.4V V sd = 0.8 V Supply Voltage: Phase selection: POR: /X Vccrth =3.7~4.1V Vcchys=0.2V 10.Inrush Current: C total = 100 uF I inrush= 0.15 A UVP: A A Vout*70% Title : +1.8V & VTTDDR Engineer: ASUSTek Computer INC Size A2 Rev 1101HA Date: Tuesday, July 21, 2009 Joy_Zhou Project Name 1.2 Sheet 44 of 50 PR144 SUSB_ON http://hobi-elektronika.net P_VCCP_BST_15 GND PC126 10UF/25V c1206_h75 1Ohm P_VCCP_LG_20 1000PF/50V GND 2.87KOhm 1% 1 PR101 GND GND GND 22UF/6.3V Power stage I/P Current: PC98 C 0.1UF/16V I in = Vo*Io/( 0.8 * Vin) =0.84A PU8B PR103 GND 18 19 20 21 PT37 GND 25.5KOhm 1% PQ26A 1 GND 100KOhm PC99 0.1UF/16V /X I rip =1.79A I spec=2.5A *1 pcs Dynamic: PM_LEVELDOWN# [14,43,44,46] Hi : Vout = 1.0497V GND Low : Vout = 0.965V I peak=5.5A ESR / pcs =18 mohm ϦV =99mV Inductor Spec: R1.1G GND PR105 2 Ripple Current: GND2 GND3 GND4 GND5 UP6111AQDD PR104 UM6K1N Controller 39KOhm Voltage & Current: PQ26B PR106 UM6K1N GND +VCCP_OV0 PC160 P_VCCP_FBJP_10 PR102 10KOhm 1% C 100UF/2.5V /X PC159 22UF/6.3V GND GND 1 22UF/6.3V SHORT_PIN /X 402KOhm PC158 PR100 GND +VCCP + PCE5 PJP19 PR99 G GND PT21 2.2UH 1 Ilimit = Rilim / Rsense * 20u PC93 1000PF/50V c0603 P_VCCP_PHASE_S PJP18 SHORT_PIN /X PC95 1UF/10V R1.1G PT20 PL13 P_VCCP_PHASE_20 P_VCCP_OCR_10 PQ25 SI7326DN_T1_E3 2 PR98 10KOhm 1% PQ24 SI7326DN_T1_E3 12 11 10 UGATE PHASE IMAX PVCC UP6111AQDD PC97 +VCCP / 5.5A GND GND1 TON EN_PSM NC2 BOOT 3P_VCCP_BST_15 PC92 0.1UF/25V P_VCCP_FB_10 1UF/10V BAT54CW S GND PC94 PD14 D PC96 0.1UF/16V /X 1 [7,42] VCCP_PWRGD VOUT VCC FB POK NC1 AGND PGND LGATE +VCCP P_VCCP_VDD_10 P_VCCP_FB_10 P_VCCP_PWRGD_104 AC_BAT_SYS G 100KOhm D S PU8A 17 16 15 14 13 P_VCCP_UG_20 GND PR96 PC90 10UF/25V c1206_h75 2 GND P_VCCP_FB_10 +5VS 70Ohm/100Mhz +3VS P_VCCP_IN_S PL12 P_VCCP_IN_S R1.1G D PR95 820KOhm GND +5VS PC89 1000PF/50V /X S3/S5 S5 0Ohm /X PR94 1MOHM 0Ohm P_VCCP_SNU_S 1 S0 0428 PR93 [32,42] CPU_VRON B PR145 D PD13 BAT54CW 0Ohm /X P_VCCP_TON_10 P_VCCP_EN_10 [32,37,46,48] PM_LEVELDOWN# L L 100KOhm PC100 0.1UF/16V /X +VCCP_OV0 [14] +VCCP@5.5A Frequency: PR95=820k ohm Fosc=300KHz OCP: GND Voltage Status 0.965V Power Saving L H 1.0497V Normal H L 1.02V /X H H 1.102V Performance PR98=10K ohm -> 9A POR: Vccrth =3.7~4.1V Vcchys=0.2V UVP: Vout*70% OVP: I sat=14 A I dc =8 A DCR=18 mohm MOSFET Spec: H-side MOSFET: SI7326DN_T1_E3 Vout*115% Enable Voltage: V = 2.9V Soft start time: Rds(ON)= 22 mohm I cont = 6.5 A I peak = 40 A Tss=1.2 ms Phase selection: /X (Vgs=4.5 V) (T =25 к ) (Pause І10 us) B L-side MOSFET: SI7326DN_T1_E3 10.Inrush Current: Rds(ON)= 22 mohm I cont = 6.5 A I peak = 40 A C total = 100 uF I inrush= 0.15 A (Vgs=4.5 V) (T =25 к ) (Pause І10 us) A A Title : VCCP Engineer: ASUSTek Computer INC Size A2 Rev 1101HA Date: Tuesday, July 21, 2009 Joy_Zhou Project Name 1.2 Sheet 45 of 50 http://hobi-elektronika.net D D Dropout Voltage: +3VS_VDAC_CH +2.5VS / 150mA +3VS_VDAC_CH PR107 0Ohm I limit= 480mA PU9 UP7714BMA5-00 SHORT_PIN /X PC103 PR109 10KOhm 1% 10UF/6.3V PT32 Pd: PT31 GND Tss = 400us C total = 10 uF I inrush= 62.5 mA R thjc =5 C/W Pd =0.4W GND GND5 GND4 GND6 13 10 GND3 11 C PU12B UP7706U8 mb_soic_8p_197x236_4via 12 GND Inrush current: I cont= 150mA GND C Continue Current: +2.5VS Vcc=3.3V 1 2 1UF/16V PC102 1UF/16V /X EN NC/SS/FB GND VIN VOUT 1 P_2.5VS_SHDN#_10 PC101 Current Limit: PR108 PJP20 22KOhm 1% P_2.5VS_FB_101 2P_2.5VS_FBJP_10 2 70Ohm/100Mhz 2 PL15 EN Voltage: V rising = V V falling = 0.8 V Supply Voltage: ϦV= 210mV (Io=300m A) PL16 +1.8V +1.5VS / 1A 70Ohm/100Mhz B GND PJP21 SHORT_PIN /X 8.66KOhm PR114 51KOhm 1% PC106 10UF/6.3V GND GND 1 PR113 2 GND PC108 0.1UF/16V /X PR111 6.34KOhm 1P_1.5VS_FBJP_10 EN Voltage: V rising = 1.4 V Ϧ V= 300 mV (Io=2 A) V falling = 0.4 V Current Limit: Supply Voltage: I limit= 2.8 A Vcc=5V Continue Current: +1.5VS P_1.5VS_CNTL_10 UP7706U8 mb_soic_8p_197x236_4via 2 10UF/6.3V PC105 1MOHM PC104 0.1UF/16V /X PR112 P_1.5VS_FB_10 P_1.5VS_VIN_S GND2 GND1 FB VOUT NC POK EN VIN CNTL 1 P_1.5VS_EN_10 1 Dropout Voltage: PC107 10UF/6.3V PT30 PT29 2 SUSB_ON GND PU12A PR110 10KOhm [32,37,45,48] B +5VS GND GND PT40 PQ27 2N7002 GND I cont= 1A Inrush current: P_1.5VS_OV#_10 Pd: D Tss = ms C total = 20 uF I inrush= 7.5mA PR115 PM_LEVELDOWN# 1P_+1.5VS_OV_10 11 G 100KOhm A R thjc =5 C/W Pd =1.9W S [14,43,44,45] PC127 0.1UF/16V /X GND PM_LEVELDOWN# Voltage A Status GND L 1.38V Power Saving H 1.48V Normal Title : +1.5VS & +2.5VS ASUSTek Computer INC Size A3 Date: Engineer: Joy_Zhou Project Name Rev 1101HA 1.2 Sheet Tuesday, July 21, 2009 46 of 50 D2 D2 P PR37 100KOhm PJP9 /X SHORT_PIN PJP8 /X SHORT_PIN PR39 S PD6 BAT54CW G2 PR38 PC31 0.1UF/25V S2 Power stage D1 G1 MB39A132 D1 P S1 GND3 GND4 GND5 GND6 GND D G I/P Current: BAT I in = Vo*Io/( 0.8 * Vin) =1.64A PQ9 AP4835GM 2 Ripple Current: 10KOhm 2MOhm 2 2 1 P_CHG_PHASE_20 PL5 70Ohm/100Mhz PC33 10UF/25V AC_BAT_SYS Inductor Spec: PL6 70Ohm/100Mhz PQ12 SI7326DN_T1_E3 D CHG_ACOK# = 0, Adaptor Mode GND PC36 0.1UF/25V PC34 10UF/25V 2 S 1 P_CHG_VIN_S /X PC35 P_CHG_ACOK#_10 [43,49] CHG_ACOK# = 1, Battetry Mode 2N7002 G PT25 PQ11 11 P_CHG_ACOK#_10 P_AC_APR_UC_10 D P_CHG_AIRS-_5 32 P_CHG_AIRS+_5 PR41 100KOhm PQ10A UM6K1N GND I sat=10 A I dc =5.5A DCR=37mohm 1000PF/50V S GND A/D_DOCK_IN 2 1 1 10UF/25V 2 Rds(ON)= 22 mohm I cont = 6.5 A I peak = 40 A PC42 GND GND Rds(ON)= 22 mohm I cont = 6.5 A I peak = 40 A GND PC48 0.1UF/16V (Vgs=4.5 V) (T =25 к ) (Pause І10 us) 2 PC47 0.1UF/16V C L-side MOSFET: SI7326DN_T1_E3 P_CHG_VBTT_10 1 PC46 0.1UF/25V PR48 33KOhm (Vgs=4.5 V) (T =25 к ) (Pause І10 us) P_CHG_CIRS+_5 P_CHG_CIRS-_5 GND 10UF/25V +5VSUS PC51 /X 120PF/50V P_CHG_INE3-_10 +3VA PQ14A UM6K1N PC53 1000PF/50V PR53 10KOhm 1% /X P_CHG_CTL1_CTL2_10 PR56 10KOhm PR52 56KOhm PR54 100KOhm TPC26T PT15 /X 1 GND PC49 820PF/50V 1 GND Controller GND CHG_EN# [32] CHG_EN# = 0, Charger Enable CHG_EN# = 1, Charger Disable PRN62A 100KOhm 1 33 32 31 30 29 28 27 26 25 GND2 CTL2 CB OUT1 LX VB OUT2 PGND CELLS 2 GND PC41 +3VA PR51 22KOhm Vmid PJP12 /X SHORT_PIN 1Ohm GNDGND PC50 3300PF/50V PC54 0.1UF/16V PJP11 /X SHORT_PIN P_CHG_VBTT_10 H-side MOSFET: SI7326DN_T1_E3 PJP10 /X SHORT_PIN PC52 PR55 120PF/50V 1KOhm 2 PC45 0.1UF/16V P_CHG_CIRS+_5 P_CHG_CIRS-_5 PR50 10KOhm GND MOSFET Spec: GND GND PR45 PR49 100KOhm BAT_LEARN = 1, Battery discharges BAT 25mOHM PC40 1000PF/50V P_CHG_LG_20 P_CHG_RT_10 P_CHG_CS_10 P_CHG_ADJCV_10 P_CHG_VBTT_10 GND PU3A MB39A132 MB39A132_VREF P_CHG_VIN_10 P_CHG_CTL1_CTL2_10 24 23 22 21 20 19 18 17 VIN CTL1 GND1 VREF RT CS ADJ3 BATT 1UF/25V 1CHG_COMPAI_10 1 PC44 2 PR47 34.8KOhm 1% -INE1 OUTC1 OUTC2 +INC2 -INC2 ADJ2 COMP2 COMP3 1 PC43 0.1UF/16V /X BAT_LEARN 10 11 12 13 P_CHG_ADJCI_10 14 P_CHG_COMPCI_10 15 P_CHG_COMPCV_10 16 1 PR46 22KOhm VCC -INC1 +INC1 ACIN ACOK -INE3 ADJ1 COMP1 6.8UH P_CHG_SNU_S PQ10B UM6K1N PQ13 SI7326DN_T1_E3 G P_CHG_ACIN_10 P_CHG_ACOK#_10 P_CHG_INE3-_10 CHG_VCC GND S PR44 200KOhm D GND PR42 PC39 1UF/16V CHG_VCC PD8 /X BAT54CW ACIN C PL7 MB39A132_VREF PR43 220KOhm [32] GND A/D_DOCK_IN PT14 TPC26T P_CHG_HG_20 GND PC38 /X 0.01UF/25V 2 PC37 /X 0.01UF/25V P_CHG_BST_20 P_CHG_HG_20 P_CHG_PHASE_20 P_CHG_VL_20 P_CHG_LG_20 GND GND G PD7 BAT54CW D I rip =1.18A I spec=2A ×1 pcs 2 PR40 1Ohm D PU3B 34 35 36 37 PC32 0.1UF/25V PT13 TPC26T AC_BAT_SYS 10KOhm P_ADIN_SNU_S Vmid http://hobi-elektronika.net PR36 1 PQ8 AP4957GM PC30 4700PF/50V PT12 TPC26T PR35 15mOHM A/D_DOCK_IN P_AC_APR_UC_10 PT26 PRN62B GND Voltage & Current: 100KOhm G PR57 S BAT_IN 100KOhm 100KOhm PQ14B UM6K1N [38,43] BAT_IN# +5VSUS PC57 Frequency: Soft start time: PR122=33KOHM, Fosc=515KHz OCP: Phase selection: POR: 8.Inrush Current: N/A 100KOhm 0.1UF/16V /X PU4 GND GND [32,38] SMB1_CLK [32,38] SMB1_DATA GND VCC SCL OUT1 SDA OUT2 P_6268_VCC P_CHG_ADJCV_10 P_CHG_ADJCI_10 UP6268AMA6 GND GND PC58 GND 0.1UF/16V B Tss=23ms PC56 /X 0.01UF/25V PRN62D [32] G S 2 PRN62C V = 2.9 V +3VA PQ16 2N7002 PC55 0.1UF/25V D 11 Enable Voltage: +12.6V@2.5A 11 B [32] GND 3 D AC_OK PQ15 2N7002 C total =20uF I inrush= 0.01A POR Hysteresis =0.1V V on =7.5V GND GND PR60 /X 0Ohm PQ17 PMBS3906 E C PR61 10KOhm 1 B A 0.1UF/25V PC59 A/D_DOCK_IN PR62 10KOhm CHG_VCC Battery Charging Current : 4.4V > Vadj2 >= 0V ==> Ichg = (Vadj2-0.075)/(25*Rs) BATSEL_2P# = 1, Ich=1.49A BATSEL_2P# = 0, Ich=2.62A Input Adaptor Max Current Limit : Ilimit_current = (Vadj1-0.075) / (25*Rs)=1.90A GND Pre-Charging Mode : Battery Charging Voltage : Vadj3 :VREF ==> Vbat = 4.2V /cell 3.9V>Vadj3>2.4V ==> Vbat = 4.35V/cell Vadj3 :GND ==> Vbat = 4.0V /cell 2.2V>Vadj3>1.1V ==> Vbat = 2*Vadj3 /cell Battery Cell Selection : CELLS: VREF ==> Cells; CELLS: OPEN ==> Cells; CELLS: GND ==> Cells; Precharging current = 149.2mA Vadj2 = 168mV ACIN Threshold = 1.25V Adaptor > 13.75V, System Powered by Adaptor Adaptor SIMCARD_IN#;GPIO1 >HDD_ON 3/25_Item8 Page14 add Test point for USB port4&SB_SPKR 3/25_Item9 Page7 del EC34,CLK_48M_READER2 3/25_Item10 Page37 add TP for LID_EC_L#, CNT2_CHG#, CNT2_DIS#, GS1_INT1, GS1_INT2 3/25_Item11 Page32 add +5V_USB source(+5VS&JP3201) 3/26_Item0 DEL unused page& rename page No 4/6 item2 P40 add EC32~EC34 for EMI needed 3/29_Item3 P21+5V_CRT >+5V_CRT_F ,VR2 > /X 4/6 item3 swap RN6/RN18 3/29_Item4 P23 del power control circuit, add pull up for SIMCARD_IN#; 3G reset circuit >/X 4/6 item4 P39 change H149 from s03549 to s04146 3/29_Item5 P13 add Test point T207 (strap pin) 4/6 item5 P14 change EC39 PIN1 definition from A_CLK to A_Z_BITCLK for EMI 3/29_Item6 P22 +3VS > +3V_LCD 4/6 item6 P29 exchange DUA_CON PIN 12&21 definition for EMI which was found problem in 1005 4/7 item2 P40 add CAPs for EMI request 4/28 item1 P22 GC99 change to 0.22UF 3/30_Item3 P27 LAN pin5 connect to pin15 (not +3V_LAN) 4/28 item2 P24 add WC19,unstuff cut off power circuit 3/30_Item4 P18 go back to STD DIMM Conn 4/28 item3 P14 SCH GPIO8 use as +1.8V OV, and add pull up R228 3/30_Item5 P21 correct Vsync & Hsync 4/28 item4 P41~P49add power circuit 3/30_Item6 P29 Re-define +5VSUS for I/O Brd pin 21 for PWR Led 4/28 item5 P37 /X Q13,Q17,R170,R174,R180 (costdown ) 3/30_Item7 P14 add pull down for WLAN_LED; P33 add cost down solution for Auto-boot circuit 4/28 item6 P22 reserve EC back light control ,reserve C487 for +3V_LCD,reserve D22 for BL_EN control 4/29 item1 P7,P32 reserve PCI CLK for EC for OC consideration 3/30_Item9 P32 CRT_IN change to EC pin14 (hot key 1) 4/29 item2 P7 CR14 change from 10 to 30 ohm,add CC7 for VDDREF power noise 3/31_Item1 P39 Add screw hole H149 3/26_Item3 P31 Add JP3101 for +5VS /+5V_USB 4/29 item3 P27 C457 change to ohm 3/31_Item2 P41-P49 add power new circuit 3/26_Item4 P32 Define EC pin102 >CPU_OV0; pin103 >CPU_OV1 5/4 item2 delete SL & JP for factory request 3/31_Item4 P19 change array cap to single type Define EC pin85 >DDR_OV0; pin86 >DDR_OV1 3/26_Item5 P08 Add net name H_IGNNE# 3/26_Item6 P13 Modify RTC circuit C 5/4 item1 add R145 & C475 for RF request 3/31_Item3 P24 WR9,WR11,WR13,WR14 Change to 0603 type Define EC pin104 >+VCCP_OV0; pin105 >+VCCP_OV1 3/31_Item5 P28 change 4R8p 0ohm to 2R4p type 5/6 VGA connector P/N change to 12G10110915M 3/31_Item6 P22 L84,L85,L86,L87 change to low cost part 5/7 Touchpad connector P/N change to 12G183401225 3/31_Item7 P29 del camera USB common chock and ohm (I/O brd already has) 3/26_Item7 P07,P14,P22,P32,P33,P35 Add RF optional circuit 3/31_Item8 All Colay OHM Change to array type 3/26_Item8 P39 correct screw hole 3/26_Item9 P24 add short point for intel Echo peak pin define; ADD optinal ohm for Echo peak and NE672 Aux power pin define 3/26_Item10 P27 Decrease component for LAN circuit 3/26_Item11 P29 Del D36 & FLASH_LED_P# & R123; Add CSL2; 3/31_Item9 P29 del IR3 (I/O brd already has a bead) 3/31_Item10 P30 del SRN1~SRN7 for costdown&layout 3/31_Item11 P34 Reserve OR29 for cost down 3/31_Item12 P23 Q20 change to 2N7002 +VCC_FLASH change to +3VS 3/31_Item13 P22 chage the RF Cap position for LVDS signals P30 Del FLASH_LED_P# & SR16 3/31_Item14 P7,P13,P32 chage the crystal to low cost part 3/26_Item12 P41 P49 add power new schematic 3/31 item15 Reserve CR29 for future cost down power latch circuit B 3/26_Item13 P31 del JP3201 (power page has this JP) 4/1 item1 P14 add Pull up for PM_LEVELDOWN#/CPU_LEVELDOWN#,Pull down for +VCCP_OV0 3/27_Item1 P29 YQ2B >YQ1B; P35 TPQ2B >TPQ1B 4/1 item2 P20,21 add back up CRT DAC Reset&Power control solution 3/27_Item2 P21 VR8,VR9 Change to short JP 4/1 item3 P24 WU1 change to 06G030057013 3/27_Item3 P21 Costdown RGB ESD Diode 4/1 item4 P16 Reserve HDA I/O power to +1.5VS ,P29 Camera_EN to +1.5VS P14 del CAMERA_EN 3/27_Item4 P10 ADD optional Thermtrip# circuit 3/27_Item5 P41-P49 ADD power new circuit 4/1 item5 P22 del GU13(+3V_LCD circuit) , P38 Del L3816 for Layout placement space 3/27_Item6 P32 +VCCP_OV0 changed from EC pin104 to SCH GPIOSUS3 4/1 item6 P32 add OSL5,OSL6 for PM_RSTRDY#&PM_RSTWARN (debug) P32 TP_LED# changed from EC pin14 to EC pin85 3/27_Item7 P35 HOTKEY_SW0# Pull up change to +3VA 4/2 item1 P27 swap LAN pin29/30 net name(add LR86,LR87 for 8132), add R64 for clock Voltage swing,add LC11,12,13,15 decoupling 4/2 item2 P32 modify BAT_IN2 pull down,BAT_IN pull High 3/27_Item8 P29 Del HDD_ON CIRCUIT 4/2 item3 P27 del LR80 ,P28 add LC18 (/X) 3/27_Item9 P35 add CIRCUIT for EXPRESS GATE 4/2 item4 P21 reserve D13 for ESD 3/27_Item10 P41-P49 add power new circuit 4/3 item1 P18/19/22/35 swap memory data/address/command, common choke, Keyboard I/O chip capacitors 4/3 item2 P38 change DCIN_GND to GND P14 CARD_READER_EN# changed from SCH GPIOSUS3 to SCH GPIO1 3/27_Item11 P18 change DIMM to STD Type 3/27_Item12 P21 cost down U6, Del F1 Fuse 3/27_Item13 P27 LAN chip change to 02G911002601,modify LAN circuit (need check pin define) 3/27_Item14 P08 R14,R16 120 >56 OHM; R15 68 >56OHM A 4/3 item3 P39 change H140 pin 3&5 from GND to NC 4/3 item4 P32 OR10 change to 0603 size 4/3 item5 P20 R209 >/X,R218,L6 >N/A (for Pre-ER) P18 MC5, MC9, MC10 >/X Title : HISTORY 4/5 item1 P24 del WLAN SMB for layout routing P19 Cap Change to Array Cap for Costdown Engineer: 4/5 item2 P40 add EMI cap 3/27_Item15 P39 del H143,H144 for ME change Size 4/5 item3 swap for DIMM & chip resistors of clock Gen A3 Project Name Rev 1101HA 1.2 Date: Tuesday, July 21, 2009 D 4/7 item1 P39 change H142 pin from GND to NC 3/30_Item8 P37 Array Resitor change to single type for future cost down 3/26_Item1 P38 BAT2_IN# >BAT_IN#; Reserve ESD Diode for SMB&BAT_IN# P32 BAT1_IN# >BAT_IN ;Del BAT2_IN off-page 3/26_Item2 P10 Add VID & VSSSENCE for OC/UC Go back T91 solution A 4/6 item1 P40 add EC29~EC31 as stitched CAPs 3/29_Item2 model name change to N12L P21 add CRT conn in circuit Page23 add GR2 3/29_Item1 P22 add pull down 100K for LBKLT_EN 3/30_Item1 P32 EC pin32 >CRT_IN (pull up); pin85 >CRT_DACPWR_EN#; pin86 >CRTDAC_RST# ; TP_LED# > Pin18 3/30_Item2 P20 add CRT DAC power control circuit & CRT reset circuit 3/25_Item5 Page37 EC pin14 use as TP_LED# B http://hobi-elektronika.net 3/29_Item7 P27 add R179 >/X (no WOL function) 3/25_Item4 Page34 circuit move to Page30 C Sheet 50 of 50 ... EXTTS1# WLAN_LED I/O CMOS3.3 Core OFF OFF Output C B B A A Title : SCH GPIO Setting ASUSTek Computer INC Size A3 Engineer: Rev 1101HA 1.2 Date: Tuesday, July 21, 2009 N/A Project Name... enabled 55 60 100K pull high to +3VA_EC Internal pull high A Title : EC Pin Define ASUSTek Computer INC Size battery charger enabled A3 Engineer: Rev 1101HA 1.2 Date: Tuesday, July... DEBUG ICS9LPR426 A 15 UMA CLK 96M SCH LVDS CLK 100M MCH Title : Power Sequence DC 15 ASUSTek Computer INC Size A3 Engineer: Rev 1101HA 1.2 Date: Tuesday, July 21, 2009 N/A Project Name