54762 wistron husk petra rev 4m sch

5 Husk/Petra UMA/Muxless Schematics Document Ivy Bridge Intel PCH D D C B C DY :None Installed DIS:DIS installed DIS_Muxless :BOTH DIS or Muxless installed DIS_PX:BOTH DIS or PX installed DIS_PX_Muxless:DIS or PX or Muxless installed Muxless: Muxless installed.(PX4.0) PX:MUX installed.(PX3.0) PX_Muxless:BOTH PX or Muxless installed UMA:UMA installed UMA_Muxless:BOTH UMA or Muxless installed UMA_PX_Muxless:UMA or PX or Muxless installed ANNIE: ONLY FOR ANNIE solution PSL: KBC795 PSL circuit for 10mW solution installed 10mW: External circuit for 10mW solution installed 65W: for 65W adaptor installed 90W: for 90W adaptor installed B A A DIS IVB Touch Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Cover Page Size A3 Date: Document Number Rev -4M Husk/Petra Thursday, September 06, 2012 Sheet 1 of 103 CHARGER Husk and Petra Block Diagram (Optimus/UMA/co-lay) VRAM 1GByte DDR3 900MHz Intel CPU 17W/GT2 Nvidia N13P-GL 16 lane/128bit/29x29mm BT+ SYSTEM DC/DC 41 RT8223MGQW INPUTS OUTPUTS DCBATOUT D 5V_AUX_S5 3D3V_AUX_S5 5V_S5 3D3V_S5 CPU DC/DC DDRIII 1333/1600 Channel A Ivy Bridge Sandy Bridge PCIe x 16(Gen2_5Gb/s) (Muxless) OUTPUTS DCBATOUT Project code : 91.4TU01.001 PCB P/N : Revision : -4M 88,89,90,91 D 40 BQ24727 INPUTS ISL95836HRTZ DDRIII Slot 14 1600/1333 42~43 INPUTS OUTPUTS DCBATOUT VCC_CORE SYSTEM DC/DC DDRIII 1333/1600 Channel A 44 ISL95836HRTZ DDRIII Slot 15 1600/1333 INPUTS OUTPUTS DCBATOUT VCC_GFXCORE 4,5,6,7,8,9,10,11,12,13 83.84,85,86,87 SYSTEM DC/DC 45 TPS51218DSCR FDIx4x2 (UMA only) C PCIE x 1+ USB x DMIx4 Mini-Card and BT INPUTS OUTPUTS DCBATOUT 1D05V_VTT LCD SYSTEM DC/DC LVDS Intel HDMI HDMI 51 PCIE x INPUTS SD/MMC LAN 61 RTL8411 26 Left Side: 62 USB x MDI Feature Port (CRT+LAN) High Definition Audio 49 1D05_VTT USB2.0 x 0D85V_S0 B 92 ISL62882CHRTZ 17,18,19,20,21,22,23,24,25,26 OUTPUTS DCBATOUT VGA_CORE 93 Switches Touch Sensor49 INPUTS Flash ROM 8MB 60 ALC271X LPC debug port ODD 56 71 1D05V_VGA_S0 1D5V_S3 1D5V_VGA_S0 L1:Top L4:Signal L2:VCC L5:GND L3:Signal L6:Bottom SMBus 29 3D3V_VGA_S0 1D05V_VTT PCB LAYER KBC NPCE885 A OUTPUTS 26 HDD 56 (SATA3_6Gb/s) SATA LPC Bus Azalia CODEC 3D3V_S0 SPI AZALIA COMBO OUTPUTS VGA INPUTS Internal Analog MIC 48 G978 ACPI 1.1 CAMERA 1D8V_S0 LDO INPUTS LPC I/F B OUTPUTS 3D3V_S0 50 RGB PCIE ports (8) (USB2.0 + USB3.0) 47 RT9025-25ZSP INPUTS SATA ports (6) 1D5V_S3 0D75V_S0 DDR_VREF_S3 LDO 31 ETHERNET (10/100/1000Mb) USB2.0 x OUTPUTS DCBATOUT 74 PCH:HM70/77 Panther Point USB 3.0 / 14 USB 2.0/1.1 ports Left Side: USB x 46 RT8207LGQW co-lay 49 C 65 802.11a/b/g eDP A DIS IVB Touch 27 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C SPEAKER Title Touch PAD 69 Int KB69 Thermal NCT 7718W 28 Block Diagram Fan 28 Size A3 25 Date: Document Number Rev -4M Husk/Petra Thursday, September 06, 2012 Sheet of 103 A PCH Strapping Name SPKR B C Processor Strapping Huron River Schematic Checklist Rev.0_7 Schematics Notes Reboot option at power-up Default Mode: Internal weak Pull-down No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kΩ - 10-kΩ weak pull-up resistor INIT3_3V# Weak internal pull-up Leave as "No Connect" GNT3#/GPIO55 GNT2#/GPIO53 GNT1#/GPIO51 GNT[3:0]# functionality is not available on Mobile Mobile: Used as GPIO only Pull-up resistors are not required on these signals If pull-ups are used, they should be tied to the Vcc3_3power rail Strap Description Configuration (Default value for each bit is unless specified otherwise) CFG[2] PCI-Express Static Lane Reversal 1: 0: CFG[6:5] CFG[7] PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training POWER PLANE VOLTAGE 5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE 1D8V_VGA_S0 3D3V_VGA_S0 1V_VGA_S0 5V 3.3V 1.8V 1.5V 1.05V 0.95 - 0.85V 0.75V 0.35V to 1.5V 0.4 to 1.25V 1.8V 3.3V 1V 5V_USBX_S3 1D5V_S3 DDR_VREF_S3 5V 1.5V 0.75V BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5 6V-14.1V 6V-14.1V 5V 5V 3.3V 3.3V 3D3V_LAN_S5 3.3V WOL_EN Legacy WOL 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states 3D3V_AUX_S5 3.3V G3, Sx Powered by Li Coin Cell in G3 and +V3ALW in Sx Disable Danbury:Leave floating (internal pull-down) Low (0) - Flash Descriptor Security will be overridden Also, when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features High (1) - Security measure defined in the Flash Descriptor will be enabled Platform design should provide appropriate pull-up or pull-down depending on the desired settings If a jumper option is used to tie this signal to GND as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently Note: CRB recommends 1-kohm pull-down for FD Override There is an internal pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for strapping functions HDA_SDO Weak internal pull-down Do not pull high Sampled at rising edge of RSMRST# HDA_SYNC Weak internal pull-down Do not pull high Sampled at rising edge of RSMRST# GPIO8 GPIO27 11 DMI termination voltage Weak internal pull-up Do not pull low HAD_DOCK_EN# /GPIO[33] GPIO15 11 : x16 - Device functions and disabled 10 : x8, x8 - Device function enabled ; function disabled 01 : Reserved - (Device function disabled ; function enabled) 00 : x8, x4, x4 - Device functions and enabled Disable Danbury:Left floating, no pull-down required 15 -> 0, 14 -> 1, PCI-Express Port Bifurcation Straps Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor NC_CLE Normal Operation Lane Numbers Reversed Default Value Disabled - No Physical Display Port attached to 1: Embedded DisplayPort Enabled - An external Display Port device is 0: connectd to the EMBEDDED display Port SPI_MOSI NV_ALE E Pin Name CFG[4] Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor] D Huron River Schematic Checklist Rev.0_7 Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality Note : This is an un-muxed signal This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low Sampled at rising edge of RSMRST# CRB has a 1-kohm pull-up on this signal to +3.3VA rail GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down using a 1k +/- 5% resistor When this signal is sampled high at the rising edge of RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is enabled Default = Do not connect (floating) High(1) = Enables the internal VccVRM to have a clean supply for analog rails No need to use on-board filter circuit Low (0) = Disables the VccVRM Need to use on-board filter circuits for analog rails Voltage Rails DESCRIPTION ACTIVE IN S0 CPU Core Rail Graphics Core Rail S3 AC Brick Mode only All S states USB Table PCIE Routing LANE1 Mini Card2(WWAN) LANE2 Mini Card1(WLAN) SATA LANE3 Card Reader LANE4 Onboard LAN LANE5 USB3.0 LANE6 Intel GBE LAN LANE7 Dock LANE8 New Card Table SATA Pair Device Pair Device Touch Panel / 3G SIM USB Ext port (HS) I C / SMBus Addresses Fingerprint Device BLUETOOTH Mini Card2 (WWAN) CARD READER X X HDD1 USB Ext port / E-SATA /USB CHARGER HDD2 USB Ext port 2 N/A 10 EDP CAMERA N/A 11 Mini Card1 (WLAN) ODD 12 CAMERA ESATA 13 New Card SMBus ADDRESSES Ref Des HURON RIVER ORB Address Hex Bus EC SMBus Battery CHARGER BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA EC SMBus PCH eDP SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA PCH SMBus SO-DIMMA (SPD) SO-DIMMB (SPD) Digital Pot G-Sensor MINI DIS IVB Touch PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK Title PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK Size A3 Date: Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Table of Content Document Number Rev -4M Husk/Petra Thursday, September 06, 2012 Sheet of 103 SSID = CPU 1D05V_VTT_CPU OF CPU1A 19 DMI_TXP[3:0] 19 DMI_RXP[3:0] 19 FDI_TXN[7:0] 19 FDI_TXP[7:0] DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 N3 P7 P3 P11 DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 K1 M8 N4 R2 DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 K3 M7 P4 T3 DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3 FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 U7 W11 W1 AA6 W6 V4 Y2 AC9 FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3 FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 U6 W10 W3 AA7 W7 T4 AA3 AC8 FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3 AA11 AC12 19 FDI_FSYNC0 19 FDI_FSYNC1 U11 19 FDI_INT 19 FDI_LSYNC0 19 FDI_LSYNC1 DP_HPD# 1D05V_VTT_CPU R402 24D9R2F-L-GP DP_COMP FDI_INT AA10 AG8 FDI0_LSYNC FDI1_LSYNC AF3 AD2 AG11 EDP_COMPIO EDP_ICOMPO EDP_HPD# 49 DP_HPD# FDI0_FSYNC FDI1_FSYNC Intel(R) FDI C M2 P6 P1 P10 DMI 19 DMI_RXN[3:0] DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 R403 Do Not Stuff B AG4 AF4 EDP_AUX# EDP_AUX 49 DP_TXN0_CPU 49 DP_TXN1_CPU AC3 AC4 AE11 AE7 EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3 49 DP_TXP0_CPU 49 DP_TXP1_CPU AC1 AA4 AE10 AE6 EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3 49 DP_AUXN_CPU 49 DP_AUXP_CPU eDP DY PCI EXPRESS GRAPHICS 19 DMI_TXN[3:0] D G3 G1 G4 PEG_IRCOMP_R PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15 H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7 PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0 PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15 K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6 PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0 PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15 G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4 PEG_C_TXN15 PEG_C_TXN14 PEG_C_TXN13 PEG_C_TXN12 PEG_C_TXN11 PEG_C_TXN10 PEG_C_TXN9 PEG_C_TXN8 PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0 C401 C402 C403 C404 C405 C406 C407 C408 C409 C410 C411 C412 C413 C414 C415 C416 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP PEG_TXN15 PEG_TXN14 PEG_TXN13 PEG_TXN12 PEG_TXN11 PEG_TXN10 PEG_TXN9 PEG_TXN8 PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0 PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15 F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4 PEG_C_TXP15 PEG_C_TXP14 PEG_C_TXP13 PEG_C_TXP12 PEG_C_TXP11 PEG_C_TXP10 PEG_C_TXP9 PEG_C_TXP8 PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0 C417 C418 C419 C420 C421 C422 C423 C424 C425 C426 C427 C428 C429 C430 C431 C432 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless Muxless SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP PEG_TXP15 PEG_TXP14 PEG_TXP13 PEG_TXP12 PEG_TXP11 PEG_TXP10 PEG_TXP9 PEG_TXP8 PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0 PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO R401 24D9R2F-L-GP D PEG_RXN[0 15] 83 PEG_RXP[0 15] 83 C PEG_TXN[0 15] 83 PEG_TXP[0 15] 83 B IVY-BRIDGE-GP-NF 71.00IVY.A0U DIS IVB Touch A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (PCIE/DMI/FDI) Size A3 Date: Document Number Rev -4M Husk/Petra Thursday, September 06, 2012 Sheet of 103 SSID = CPU PROC_DETECT# C49 CATERR# A48 PECI C45 PROCHOT# D45 THERMTRIP# 22,27 27,42 H_PROCHOT# H_PECI R513 H_PROCHOT#_R 56R2J-L1-GP 22,36 H_THERMTRIP# THERMAL C502 SC47P50V2JN-3GP CLOCKS C57 H_PROCHOT# R501 62R2J-GP PROC_SELECT# DDR3 MISC 1D05V_VTT_CPU F49 2 OF MISC 22 H_SNB_IVB# D CPU1B J3 H2 CLK_EXP_P CLK_EXP_N 20 20 DPLL_REF_CLK DPLL_REF_CLK# AG3 AG1 CLK_DP_P CLK_DP_N 20 20 SM_DRAMRST# AT30 R502 4K99R2F-L-GP SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 BF44 BE43 BG43 SM_RCOMP_0 R506 SM_RCOMP_1 R507 SM_RCOMP_2 R508 BCLK BCLK# R503 10KR2J-L-GP B46 22,36,97 H_CPUPW RGD BE45 37 VDDPW RGOOD UNCOREPWRGOOD SM_DRAMPWROK B BUF_CPU_RST# XDP_DBRESET# 18,27,31,36,65,71,83,97 PLT_RST# 3D3V_S0 RN503 SRN1K5J-1-GP BUF_CPU_RST# D44 RESET# JTAG & BPM PM_SYNC PWR MANAGEMENT C48 H_PM_SYNC D SM_DRAMRST# 37 140R2F-GP 25D5R2F-GP 200R2F-L-GP Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils C 19 PRDY# PREQ# N53 N55 TCK TMS TRST# L56 L55 J58 TDI TDO M60 L59 DBR# K58 BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7 G58 E55 E59 G55 G59 H60 J59 J61 C 1D05V_VTT_CPU XDP_TRST# XDP_TDO XDP_TDO XDP_TRST# RN501 SRN51J-GP XDP_DBRESET# B IVY-BRIDGE-GP-NF 71.00IVY.A0U DIS IVB Touch Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C A Title Size Custom Date: A CPU (THERMAL/CLOCK/PM ) Document Number Rev -4M Husk/Petra Thursday, September 06, 2012 Sheet of 103 SSID = CPU OF CPU1C OF M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 D C B AG6 AJ6 AP11 AL6 AJ10 AJ8 AL8 AL7 AR11 AP6 AU6 AV9 AR6 AP8 AT13 AU13 BC7 BB7 BA13 BB11 BA7 BA9 BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56 SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 14 14 14 M_A_BS0 M_A_BS1 M_A_BS2 BD37 BF36 BA28 SA_BS0 SA_BS1 SA_BS2 14 14 14 M_A_CAS# M_A_RAS# M_A_W E# BE39 BD39 AT41 SA_CAS# SA_RAS# SA_WE# 15 SA_CK0 SA_CK#0 SA_CKE0 AU36 AV36 AY26 M_A_DIM0_CLK_DDR0 14 M_A_DIM0_CLK_DDR#0 14 M_A_DIM0_CKE0 14 SA_CK1 SA_CK#1 SA_CKE1 AT40 AU40 BB26 M_A_DIM0_CLK_DDR1 14 M_A_DIM0_CLK_DDR#1 14 M_A_DIM0_CKE1 14 SA_CS#0 SA_CS#1 BB40 BC41 M_A_DIM0_CS#0 14 M_A_DIM0_CS#1 14 SA_ODT0 SA_ODT1 AY40 BA41 M_A_DIM0_ODT0 14 M_A_DIM0_ODT1 14 SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7 AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15 BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 M_B_DQ[63:0] M_A_DQS#[7:0] 14 M_A_DQS[7:0] 14 M_A_A[15:0] 14 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 AL4 AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9 BD13 BF12 BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59 AM60 AL59 AF61 AH60 SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 15 15 15 M_B_BS0 M_B_BS1 M_B_BS2 BG39 BD42 AT22 SB_BS0 SB_BS1 SB_BS2 15 15 15 M_B_CAS# M_B_RAS# M_B_W E# AV43 BF40 BD45 SB_CAS# SB_RAS# SB_WE# D SB_CK0 SB_CK#0 SB_CKE0 BA34 AY34 AR22 M_B_DIM0_CLK_DDR0 15 M_B_DIM0_CLK_DDR#0 15 M_B_DIM0_CKE0 15 SB_CK1 SB_CK#1 SB_CKE1 BA36 BB36 BF27 M_B_DIM0_CLK_DDR1 15 M_B_DIM0_CLK_DDR#1 15 M_B_DIM0_CKE1 15 SB_CS#0 SB_CS#1 BE41 BE47 M_B_DIM0_CS#0 15 M_B_DIM0_CS#1 15 SB_ODT0 SB_ODT1 AT43 BG47 M_B_DIM0_ODT0 15 M_B_DIM0_ODT1 15 SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7 AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 C DDR SYSTEM MEMORY B M_A_DQ[63:0] DDR SYSTEM MEMORY A CPU1D 14 M_B_DQS#[7:0] 15 M_B_DQS[7:0] 15 B SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15 BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22 M_B_A[15:0] M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 15 IVY-BRIDGE-GP-NF IVY-BRIDGE-GP-NF 71.00IVY.A0U 71.00IVY.A0U DIS IVB Touch A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (DDR) Size A3 Date: Document Number Rev -4M Husk/Petra Thursday, September 06, 2012 Sheet of 103 SSID = CPU Do Not Stuff Do Not Stuff TP701 TP702 1 Do Not Stuff TP703 0:Lane Reversed D CFG2 R702 1KR2J-L2-GP Muxless CFG0_TP CFG1_TP CFG2 CFG3_TP CFG4 CFG5 CFG6 CFG7 B50 C51 B54 D53 A51 C53 C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 H43 K43 VCC_VAL_SENSE VSS_VAL_SENSE H45 K45 VAXG_VAL_SENSE VSSAXG_VAL_SENSE F48 G48 VCC_DIE_SENSE RSVD47 H48 K48 RSVD6 RSVD7 Enabl EDP function 1:Disable CFG4 0:Enable CFG4 C BA19 AV19 AT21 BB21 BB19 AY21 BA22 AY22 AU19 AU21 BD21 BD22 BD25 BD26 BG22 BE22 BG26 BE26 BF23 BE24 R703 1KR2J-L2-GP EDP PCIE Port Bifurcation Straps CFG[6:5] 11: x16 - Device functions and disabled RESERVED 1: Normal Operation; Lane # definition matches socket pin map definition OF CPU1E PEG Static Lane Reversal CFG2 BCLK_ITP BCLK_ITP# N59 N58 RSVD30 RSVD31 RSVD32 RSVD33 N42 L42 L45 L47 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 M13 M14 U14 W14 P13 RSVD39 RSVD40 AT49 K24 RSVD41 RSVD42 RSVD43 RSVD44 AH2 AG13 AM14 AM15 RSVD45 N50 DC_TEST_A4 DC_TEST_C4 DC_TEST_D3 DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58 DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 D A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1 C 10: x8, x8 - Device function enabled ; function disabled 01: Reserved - (Device function disabled ; function enabled) 00: x8,x4,x4 - Device functions and enabled IVY-BRIDGE-GP-NF 71.00IVY.A0U B B CFG6 1 CFG5 DY R705 Do Not Stuff DY R704 Do Not Stuff PEG DEFER TRAINING CFG7 1: PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training CFG7 R706 Do Not Stuff DY DIS IVB Touch A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (RESERVED) Size A3 Date: Document Number Rev -4M Husk/Petra Thursday, September 06, 2012 Sheet of 103 SSID = CPU PEG IO AND DDR IO 2 2 2 2 2 2 2 2 2 2 GAP-CLOSE-PWR PG805 GAP-CLOSE-PWR PG806 GAP-CLOSE-PWR R810 100KR2J-4-GP VCCIO_SEL BC22 H_VCCP_SEL_L B 1D05V_VTT_CPU 1D05V_VTT_CPU +V1.05S_VCCPQE R808 0R0402-PAD C853 SC1U6D3V2KX-L-1-GP A44 B43 C44 H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT R805 75R3J-L-GP R804 130R2F-1-GP R803 43R2J-GP2 VR_SVID_ALERT# 42 H_CPU_SVIDCLK 42 H_CPU_SVIDDAT 42 Place near processor VCC_CORE SVID VIDALERT# VIDSCLK VIDSOUT 1D05V_VTT_CPU AM25 AN22 VCCPQE1 VCCPQE2 CORE SUPPLY 2 2 C 3D3V_S5 QUIET RAILS 1 2 2 2 1 1 2 2 DY GAP-CLOSE-PWR PG804 SC1U6D3V2KX-L-1-GP C824 DY SC1U6D3V2KX-L-1-GP C823 DY SC1U6D3V2KX-L-1-GP C822 DY SC1U6D3V2KX-L-1-GP C821 GAP-CLOSE-PWR PG803 1D05V_VTT_CPU SC1U6D3V2KX-L-1-GP C814 1 SC1U6D3V2KX-L-1-GP C813 1D05V_VTT_CPU PG801 GAP-CLOSE-PWR PG802 SC1U6D3V2KX-L-1-GP C812 D DY 1D05V_VTT SC1U6D3V2KX-L-1-GP C809 DY SC10U6D3V5KX-1GP C845 SC10U6D3V5KX-1GP C844 SC10U6D3V5KX-1GP C843 DY 1D05V_VTT_CPU SC10U6D3V5KX-1GP C830 W16 W17 DY SC10U6D3V5KX-1GP C829 VCCIO50 VCCIO51 DY SC10U6D3V5KX-1GP C840 AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15 DY SC10U6D3V5KX-1GP C839 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 VCCIO40 VCCIO41 VCCIO42 VCCIO43 VCCIO44 VCCIO45 VCCIO46 VCCIO47 VCCIO48 VCCIO49 DY SC1U6D3V2KX-L-1-GP C807 SC10U6D3V5KX-1GP C836 SC10U6D3V5KX-1GP C834 SC10U6D3V5KX-1GP C833 SC10U6D3V5KX-1GP C832 SC10U6D3V5KX-1GP C835 B AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48 SC1U6D3V2KX-L-1-GP C806 DY VCCIO1 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 SC10U6D3V5KX-1GP C838 SC2D2U6D3V2KX-GP C820 DY VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 Iccmax:8.5A ICC_TDC:8.5A SC10U6D3V5KX-1GP C810 SC2D2U6D3V2KX-GP C811 DY A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38 SC10U6D3V5KX-1GP C831 SC10U6D3V5KX-1GP C828 SC10U6D3V5KX-1GP C827 SC10U6D3V5KX-1GP C826 SC10U6D3V5KX-1GP C825 DY SC2D2U6D3V2KX-GP C819 SC2D2U6D3V2KX-GP C818 DY VCC_CORE SC2D2U6D3V2KX-GP C808 SC2D2U6D3V2KX-GP C804 DY DY DY DY SC2D2U6D3V2KX-GP C817 SC2D2U6D3V2KX-GP C816 DY SC2D2U6D3V2KX-GP C803 SC2D2U6D3V2KX-GP C802 SC2D2U6D3V2KX-GP C815 SC2D2U6D3V2KX-GP C801 C DY VCC_CORE D OF SC10U6D3V5KX-1GP C805 ULV:17W Iccmax:33A ICC_TDC:25A POWER CPU1F F43 G43 1D05V_VTT_CPU AN16 AN17 Place near processor R802 100R2F-L1-GP-U DY VCCIO_SENSE VSS_SENSE_VCCIO 42 42 VCCSENSE VSSSENSE R806 10R1F-GP VCCIO_SENSE 45 VSSIO_SENSE 45 A A VCC_SENSE VSS_SENSE SENSE LINES R801 100R2F-L1-GP-U DIS IVB Touch R807 10R1F-GP IVY-BRIDGE-GP-NF Wistron Corporation DY 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 71.00IVY.A0U Title CPU (VCC_CORE) Size Custom Date: Document Number Rev -4M Husk/Petra Monday, September 17, 2012 Sheet of 103 SSID = CPU 1 2 1 2 DY DY C QUIET RAILS +1.5S_VCCD_Q R909 0R0402-PAD C923 SC1U6D3V2KX-L-1-GP B 0D85V_S0 BC43 TP_VDDQ_SENSE BA43 TP_VDDQ_VSS 1 TP901 TPAD14-OP-GP TP902 TPAD14-OP-GP VDDQ_SENSE VSS_SENSE_VDDQ R902 100R2F-L1-GP-U R902 need be close to pin U10 VCCSA_SENSE VCCSA_VID0 VCCSA_VID1 D48 D49 VCCSA_VID0 VCCSA_VID1 1D05V_VTT_CPU 1D05V_VTT_CPU U10 VCCSA_SENSE R908 10KR2J-L-GP R912 10KR2J-L-GP VCCSA_VID0 VCCSA_VID1 DY DY VCCSA_VID0 VCCSA_VID1 48 48 2 C915 SC10U6D3V5KX-1GP AM28 AN26 ICC_MAX:6A VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 VCCSA9 VCCSA10 VCCSA11 VCCSA12 VCCSA13 VCCSA14 VCCSA15 VCCSA16 VCCDQ1 VCCDQ2 L17 L21 N16 N20 N22 P17 P20 R16 R18 R21 U15 V16 V17 V18 V21 W20 0D85V_S0 1.8V RAIL VCCPLL1 VCCPLL2 VCCPLL3 SA RAIL BB3 BC1 BC4 C922 SC1U10V2KX-1GP SENSE LINES VAXG_SENSE VSSAXG_SENSE VCCSA VID lines F45 G45 ICC_MAX:1.2A DY +V1.5S_VCCD_Q should be short to +V1.5S_VCCDDQ on board SENSE LINES DY PROCESSOR DDR 1.5V QUIET RAIL (BGA only) 1D8V_S0 2 2 1 2 VREF - 1.5V RAILS DDR3 GRAPHICS 2 2 2 1 1D5V_S0 Iccmax:5A SC1U6D3V2KX-L-1-GP C926 AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33 SC1U6D3V2KX-L-1-GP C917 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26 1D5V_S0 42 VCC_AXG_SENSE 42 VSS_AXG_SENSE B D SC1U6D3V2KX-L-1-GP C918 R907 100R2F-L1-GP-U BE7 and BG7 is NC ball in HR DY R906,R907 close to CPU VCC_AXG_SENSE VSS_AXG_SENSE 37 37 RN902 SRN1KJ-7-GP SC1U6D3V2KX-L-1-GP C925 2 M_VREF_DQ_DIMM0_C M_VREF_DQ_DIMM1_C SC1U6D3V2KX-L-1-GP C924 R906 100R2F-L1-GP-U 37 SC10U6D3V5KX-1GP C913 VCC_GFXCORE +V_SM_VREF_CNT M_VREF_DQ_DIMM0_C M_VREF_DQ_DIMM1_C BE7 BG7 SC10U6D3V5KX-1GP C912 C SA_DIMM_VREFDQ SB_DIMM_VREFDQ AY43 SC10U6D3V5KX-1GP C911 DY SM_VREF VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54 VAXG55 VAXG56 Routing Guideline: Power from DDR_VREF_S3 and +V_SM_VREF_CNT should have 10 mils trace width OF SC10U6D3V5KX-1GP C910 SC10U6D3V5KX-1GP C921 SC10U6D3V5KX-1GP C920 SC10U6D3V5KX-1GP C919 DY SC10U6D3V5KX-1GP C908 DY SC1U6D3V2KX-L-1-GP C916 SC1U6D3V2KX-L-1-GP C914 SC1U6D3V2KX-L-1-GP C909 SC1U6D3V2KX-L-1-GP C907 DY DY SC10U6D3V5KX-1GP C905 DY SC10U6D3V5KX-1GP C904 SC10U6D3V5KX-1GP C903 SC10U6D3V5KX-1GP C902 D AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46 N45 P47 P48 P50 P51 P52 P53 P55 P56 P61 T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61 POWER CPU1G Iccmax:18A(GT1) ICC_TDC:12A(GT1) VCC_GFXCORE R913 10KR2J-L-GP R914 10KR2J-L-GP 1 IVY-BRIDGE-GP-NF 71.00IVY.A0U A A DIS IVB Touch Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (VCC_GFXCORE) Size Custom Date: Document Number Rev -4M Husk/Petra Monday, September 17, 2012 Sheet of 103 SSID = CPU OF CPU1H OF CPU1I C B VSS VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53 BG9 C29 C35 C40 D10 D14 D18 D22 D26 D29 D35 D4 D40 D43 D46 D50 D54 D58 D6 E25 E29 E3 E35 E40 F13 F15 F19 F29 F35 F40 F55 G51 G6 G61 H10 H14 H17 H21 H4 H53 H58 J1 J49 J55 K11 K21 K51 K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61 M11 M15 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS NCTF TEST PIN： A5,A57,BC61,BG5 BG57,C3,E1,E61 D VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13 NCTF A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53 A9 AA1 AA13 AA50 AA51 AA52 AA53 AA55 AA56 AA8 AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46 AC6 AD17 AD20 AD4 AD61 AE13 AE8 AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59 AG10 AG14 AG18 AG47 AG52 AG61 AG7 AH4 AH58 AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48 AJ7 AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61 AM13 AM20 AM22 AM26 AM30 AM34 M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59 VSS_NCTF_1#A5 VSS_NCTF_2#A57 VSS_NCTF_3#BC61 VSS_NCTF_8#BG5 VSS_NCTF_9#BG57 VSS_NCTF_10#C3 VSS_NCTF_13#E1 VSS_NCTF_14#E61 A5 A57 BC61 BG5 BG57 C3 E1 E61 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_11 VSS_NCTF_12 BD3 BD59 BE4 BE58 C58 D59 D C B IVY-BRIDGE-GP-NF 71.00IVY.A0U DIS IVB Touch A A IVY-BRIDGE-GP-NF Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 71.00IVY.A0U Title CPU (VSS) Size A3 Date: Document Number Rev -4M Husk/Petra Thursday, September 06, 2012 Sheet 10 of 103 ... Date: Document Number Rev -4M Husk/ Petra Thursday, September 06, 2012 Sheet of 103 A PCH Strapping Name SPKR B C Processor Strapping Huron River Schematic Checklist Rev. 0_7 Schematics Notes Reboot... PCH_SMBDATA/PCH_SMBCLK Size A3 Date: Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Table of Content Document Number Rev -4M Husk/ Petra Thursday, September... IVB Touch A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (PCIE/DMI/FDI) Size A3 Date: Document Number Rev -4M Husk/ Petra Thursday,