Nghiên cứu thiết kế và chế tạo kênh dẫn sóng Plasmon bề mặt Study and fabrication of surface plasmon polariton waveguides

Nghiên cứu thiết kế và chế tạo kênh dẫn sóng Plasmon bề mặt Study and fabrication of surface plasmon polariton waveguides Nghiên cứu thiết kế và chế tạo kênh dẫn sóng Plasmon bề mặt Study and fabrication of surface plasmon polariton waveguides luận văn tốt nghiệp thạc sĩ

MINISTRY OF EDUCATION AND TRAINING HANOI UNIVERSITY OF SCIENCE AND TECHNOLOGY INTERNATIONAL TRAINING INSTITUTE FOR MATERIALS SCIENCE - NGUYEN VAN CHINH STUDY AND FABRICATION OF SURFACE PLASMON POLARITON WAVEGUIDES MASTER THESIS OF MATERIALS SCIENCE ITIMS BATCHS 2014 Hanoi - 2016 MINISTRY OF EDUCATION AND TRAINING HANOI UNIVERSITY OF SCIENCE AND TECHNOLOGY INTERNATIONAL TRAINING INSTITUTE FOR MATERIALS SCIENCE - NGUYEN VAN CHINH STUDY AND FABRICATION OF SURFACE PLASMON POLARITON WAVEGUIDES Specialized: Science and Engineering of Electronic Materials MASTER THESIS OF MATERIALS SCIENCE ITIMS BATCHS 2014 SUPERVISOR: Dr CHU MANH HOANG Hanoi - 2016 ACKNOWLEDGEMENT Firstly, I would like to thank my supervisor, Dr Chu Manh Hoang who has supervised and encouraged me during my stay at ITIMS Acknowledgement would be also sent to all the members of Micro-nano systems and sensors technology Laboratory – International Training Institute for Materials Science (ITIMS) Finally, thanks should also be given to my family and friends, who always supported me in my study LIST OF PUBLICATIONS Nguyen Van Chinh, Nguyen Thanh Huong, and Chu Manh Hoang (2015), ―Design and simulation of triangular wedge surface plasmon polariton waveguide‖, 9th Vietnam National Conference of Solid Physics and Materials Science , pp 314317, 2015, ISBN: 978-604-938-722-7 Nguyen Van Chinh, Nguyen Thanh Huong, Vu Ngoc Hung, Chu Manh Hoang (2015), ―Fabrication of triangular-shaped plasmonic waveguide based on wet bulk micromachining‖, International Conference on Applied & Engineering Physics, pp 124-127, 2015, ISBN: 978-604-913-232-2 Nguyen Van Chinh, Nguyen Thanh Huong, Vu Ngoc Hung, Chu Manh Hoang (2016), ―Characteristics of Trapezoidal-Shaped Plasmonic Waveguide‖, The 3rd International Conference on Advanced Materials and Nanotechnology, pp 111114, 2016, ISBN: 978-604-95-0010-7 STATEMENT OF ORIGINAL AUTHORSHIP I hereby declare that the results presented in the thesis are performed by the author The research contained in this thesis has not been previously submitted to meet requirements for an award at this or any higher education institution Date: Signature: 30/09/2016 CONTENTS CHAPTER FUNDAMENTALS OF PLASMONICS 1.1 History of development 1.2 Fundamentals of Surface Plasmon Polaritons 1.3 Wedge surface plasmon polariton waveguides 1.3.1 Conventional wedge waveguides 1.3.2 Hybrid wedge waveguides 1.3.3 Fabrication of wedge waveguides 11 1.3.4 Exciting surface plasmon polariton mode in the wedge waveguide 13 1.3.5 Applications of wedge waveguides 15 Purpose of this thesis 19 CHAPTER DESIGN AND SIMULATION OF WAVEGUIDE 20 2.1 Basic theory for the simulation of waveguides 20 2.2 Triangular Waveguide 21 2.2.1 Structure of triangular waveguide 21 2.2.2 Meshing 22 2.2.3 The thickness of metal layer 23 2.2.4 The tip angle of triangular waveguide 28 2.2.5 Height of triangular waveguide 30 2.2.6 The refractive index of cladding medium 32 2.3 Trapezoidal waveguide 34 2.3.1 Model of the waveguides 34 2.3.2 Results and discussion 35 CHAPTER FABRICATION OF WAVEGUIDE 40 3.1 Process of fabrication 40 3.1.1 Oxidation of SOI wafer 42 3.1.2 Photolithography 43 3.1.3 Isotropic wet–etching in buffered Hydrofluoric acid solution 45 3.1.4 Anisotropic etching in Potassium Hydroxide 46 3.1.5 Sputtering metal layer 47 3.2 Results of the fabrication of waveguide 48 CONCLUSIONS 51 SUGGESTED FURTURE WORKS 51 REFERENCES 52 LIST OF FIGURES Figure 1.1: Lycurgus cup Figure 1.2: Number of papers Figure 1.3: SPPs at single interface Figure 1.4: SPP on Three-layer system Figure 1.5: Schematic of conventional wedge waveguide Figure 1.6: Typical hybrid wedge waveguides 10 Figure 1.7: Fabrication steps of wedge waveguide 11 Figure 1.8: Schematic of 2PP technique 12 Figure 1.9: Prism coupling 13 Figure 1.10: Waveguide coupling 14 Figure 1.11: Grating coupling 15 Figure 1.12 Wedge ring - type hybrid microresonator 16 Figure 1.13 Plasmon nanolaser 18 Figure 2.1: Schematic of triangular waveguide 21 Figure 2.2: Distribution of mesh 22 Figure 2.3: Electric field depending on meshing 23 Figure 2.4: Electric field depending on the thickness of metal 25 Figure 2.5: The influence of metal on transmission characteristics 27 Figure 2.6: Electric field at the thickness of 20nm 28 Figure 2.7: Electric field at various wedge angles 29 Figure 2.8: Transmission properties at various wedge angles 30 Figure 2.9: Electric field at different heights 31 Figure 2.10: Propagation characteristic at different heights 32 Figure 2.11: WPP mode depending on surrounding medium 33 Figure 2.12: Sketch of trapezoidal waveguide 34 Figure 2.13: Distribution of hybrid WPP mode 35 Figure 2.14: Electric field at the top surface 36 Figure 2.15: y and z components of electric field 37 Figure 2.16: The confinement and attenuation of WPP mode 38 Figure 2.17: Characteristic of waveguide 39 Figure 3.1: Schematic of fabrication process 41 Figure 3.2: Array of mask 43 Figure 3.3: Coating photoresist 44 Figure 3.4: Double-Side Align System PEM-800 45 Figure 3.5: The sputtering system 47 Figure 3.6: Silicon dioxide mask line 48 Figure 3.7: Silicon dioxide mask line after under - etching 49 Figure 3.8: Silicon waveguide 50 GLOSSARY OF TERMS AND ABBREVIATIONS SPP Surface Plasmon Polariton WPP Wedge Plasmon Polariton CPP Chanel Plasmon Polariton 2PP Two – Photon Polymerization TM Transverse Magnetic 2D Two Dimensional FIB Focus Ion Beam ATR Attenuated Total Reflectance SOI Silicon – on - Insulator MEMS BHF Microelectromechanical Systems Buffered Hydrofluoric Acid RF Radio frequency DC Direction Current SEM Scanning Electron Microscope CHAPTER FABRICATION OF WAVEGUIDE 3.1 Process of fabrication Wet–bulk micromachining is a very popular technology, which has been used commonly to fabricate Microelectromechanical systems (MEMS) devices In this process, micro-structures are produced inside a substrate by selectively etching material Apart from the advantages such as simple, low–budget, high productivity, so on, this technique also has an important property that structures are fabricated by etching based on crystallographic orientations So, the surface of structures can be atomically smooth if etching is carried out precisely This is an extremely important property in surface plasmonic devices because the propagation of surface wave would be strongly degraded on roughness surfaces In this chapter, we will fabricate the WPP waveguides which are designed in chapter on (100) SOI wafer by using wet–bulk micromachining Based on (100) silicon wafer, the anisotropic wet – etching is usually uses the alkali solutions such as Tetra Methyl Ammonium Hydroxide (TMAH), Ethylene Diamine Pyrocatechol (EDP), or Potassium Hydroxide (KOH) solution Using lowly anisotropic etchants such as TMAH or EDP, we can fabricate V–shape structures with sidewall being (110) or (100) lattice planes The sidewall angle α is 45o or 90o In the case of highly anisotropic etchant KOH, the sidewall is (100) or (111) plane, depending on the orientation of mask line So, the sidewall angle is 90 o or 54.7o [26] From the results of simulation in chapter 2, we can realize that the value 54.7o of α is the most trade – off between attenuation and confinement of WPP mode Not only that, the etching rate in direction is smallest (only a few dozen nanometers per minute), which will make it easier to control the size of structures Therefore, we will use KOH solution as an etchant to fabricate the waveguides with the sidewall angle of 54.7o 40 Figure 3.1 Schematic of fabrication process of waveguide 41 Figure 3.1 illustrates schematic of fabrication process of waveguides The fabrication is performed under four main stages: traditional photolithography for creating photoresist mask line, isotropic etching in Buffered Hydrofluoric Acid (BHF) solution to form silicon dioxide mask line and to reduce the size of mask lines as well, anisotropic etching in KOH solution to define triangular shape or trapezoidal shape silicon waveguide, sputtering to deposit a Silver metal film onto structure The fabrication steps will be discussed in detail in the following sections 3.1.1 Oxidation of SOI wafer We begin our fabrication by (100) SOI wafer This wafer diameter is inch It has a thickness of device layer to be 1µm and thickness of buffered oxide layer to be µm The purpose of this process is to grow up a silicon dioxide layer on the surface of wafer, which is used for forming oxide mask line in subsequent steps Firstly, we clean the wafer in Piranha solution to remove impurity particles on surface Piranha solution is prepared by mixing specification of sulfuric acid (98% by weight) with hydro peroxide (35%) and DI water in 1:2:2 volume ratio Heat of hydration would boil the solution and generate oxygen atom Powerful oxidizing capacity of the mixture helps removed almost dust from the surface The wafer is immersed in this solution until reaching room temperature, then it is washed with DI water This process would be used to clean up the sample, interspersed with later steps Following, the wafer is oxidized in furnace at temperature 1100oC The dry thermal oxidation occurred in reaction Si + O2  SiO2 [3.1] After carrying out the oxidation during hours, we obtain a silicon dioxide layer with the thickness of 200nm Following the expression 3.1, to generate mole SiO2, we must sacrifice mole of Si From that, we have a relative expression of thickness of growing up oxide layer tox and thickness of the lost silicon layer tsi: [3.2] 42 Here, ρ and M is density and molecular weight of materials, respectively Ordinary, density of silicon is 2.3209 g/cm3 and of silicon dioxide is 2.196 g/cm3 Replacing to [3.2], we obtain tSi = 0.44tox, that mean to built up a SiO2 layer with 200nm of thickness, the thickness of consumed silicon is 88nm Therefore, the thickness of remaining device layer after oxidation as the height of waveguide is about 912nm In order to keep the thickness of device layer to be constant, we have to use other methods such as CVD, Epitaxy or Sputtering, so on 3.1.2 Photolithography Fig 3.2 Array of designed Cr mask line patterns is used for investigating the fabrication process of WPP waveguides (a) and the arrangement of it on wafer (b) The next process is to form a photoresist mask line onto surface of oxidized wafer The shapes of resist mask are the same as the Chromium mask lines, which are fabricated by lift - off process on a glass substrate The mask lines are the metal strips which have a width varied in the range from 0.8µm to 2µm The interspace between the Cr mask lines is 5.0 µm The length of the Cr mask lines is 2cm, which depends on the available working dimension of photolithography machine Figure 3.2 show the shape of mask lines (a) and their arrangement on silicon wafer (b) In order to obtain the sidewall of waveguide as (111) plane, the mask line is oriented in the directions (parallel or perpendicular to the flat of wafer) Difference in 43 mask size enables the optimization of etching-time in the later stages to become easier Figure 3.3 Spinner unit (a) and schematically illustrating the spin coating of photoresist onto the SOI wafer (b) The next step in photolithography is to spin coat a photoresist layer onto the surface of wafer Figure 3.3 (a) display the spinner unit that is used for spin coating primer and photoresist Before spin coating photoresist, a thin primer layer is spin coated on the surface of wafer to enhance the adhesion of resist layer and substrate The programming of the rotation speed and time are shown in figure 3.3 (b) After the coated photoresist layer, the wafer is baked on a hotplate at 90oC in 90 seconds to evaporate the solvent After the spin coating process, the shape of Chromium mask line is transported to wafer by Double side Align system PEM – 800 (Fig 3.4) This system uses a mercury vapor lamp to emit Ultraviolet radiation at wavelength about 400nm The power of lamp is 250W and the radiated power of UV source is 12 mW/cm2 The wafer is exposed during 45 second in the hard contact mode and then is soft baked on the hotplate at 90oC in 120 secs After the mask alignment, the photoresist is developed in 45 secs Then, the photoresist mask is hard baked at 120oC in 15 The quality of mask line is preliminary evaluated by optical microscope 44 Figure 3.4 Double Side Align System PEM-800 used for photolithography 3.1.3 Isotropic wet–etching in buffered Hydrofluoric acid solution The photoresist mask in the previous step is used to shape the oxide mask lines, which will protect silicon in potassium hydroxide solution By that photolithography technique, we can only achieve the width of mask line at micro scale In this section, we will define the oxide mask lines and reduce their size to sub–micro scale The isotropic etching of silicon dioxide takes place in Buffered Hydrofluoric (BHF) acid solution 1:5 This solution is the mixture of (40% by weight) NH4F solution and (49% by weight) HF solution in 5:1 volume ratio This etchant can dissolve silicon dioxide by chemical reaction SiO2 + 6HF  H2 + SiF6 +2H2O [3.3] NH4F ↔ NH3 + HF [3.4] 45 In the first step of isotropic etching, the etchant will attack on the surface of silicon dioxide in area that is not covered by photoresist to form oxide mask lines have the same width of resist mask At room temperature, the etching rate of BHF 1:5 is about 100nm per minute, so it takes about two minutes to completely etching the unprotected area of SiO2 layer In the second step of isotropic etching, the etchant will attack on both side walls of silicon dioxide strip This undercut etching reduces the width of mask line to sub–micro scale It is due to in undercut – etching, the reaction products are difficult to move out, it prevents the attack of etchant, thereby reducing the etching rate Using this process, it is difficult for us to decrease excessively the size of structures because of prevention of reaction product and the wet sticking of photoresist on the surface of buffer layer To continue downing the size, we have to use the other undercut-etching in KOH solution at next process 3.1.4 Anisotropic etching in Potassium Hydroxide The oxide mask line in the previous process would protect silicon against the attach of etchant in this process The anisotropic etching is carried out in Potassium Hydroxide 25% by weight at the temperature of 80oC The silicon layer will be dissolved to from V–shape structure by chemical reaction Si + 2OH- + 2H2O  SiO2(OH)2- + 2H2↑ [3.5] The rate of this reaction is strongly depend the density of dangling bond at surface of wafer In silicon single crystal, the density of dangling bonds is different on various crystal planes It leads to the etching rate is very different, the rate on (111) plane is very small compared with two remaining planes In KOH 25% solution at 80oC, the etching rate in (100) orientation is 1.4μm per minute while in (111) orientation it is only several dozen nanometers per minute In the first step of this stage, KOH is attached on the surface of wafer The area that is not protected by oxide mask will be etched in (100) direction with high speed After a short time (about 40 sec.), the trapezoidal shaped waveguides which have the top surface size equal to the width of oxide mask line are performed The 46 sidewall of these waveguides are (111) planes thus the sidewall angle is 54.7o Then, the second step in Figure 3.1 is carried out The etchant attaches both the sidewalls of waveguide, the etching intervenes in (111) directions with slow rate and make two sidewalls approaching each other 3.1.5 Sputtering metal layer Figure 3.5 The sputtering system used to deposit metal film onto the silicon waveguide This is the final stage of fabrication of WPP waveguide A thin silver layer would be deposited onto the surface of silicon waveguide to create metal–air interface for guiding surface plasmon wave The sputtering system used to create thin metal film is displayed in Figure 3.8 This system has a RF generator with power 500W and a DC generator with a power of 750W, a quartz lamp heater to expel water particle from the surface of substrate It can be fitted simultaneously with two targets and can be rotate the substrate while sputtering The highest vacuum can reach 10-7 Torr by using turbo pump 47 Cause of the insulation of buffer layer, we have to sputter at the RF mode The plasma power is 150 W and the sputtering rate is 40 nm per minute Therefore, to deposit silver films with thicknesses of 60nm and 200nm, we have to set the sputtering time are 90 and 300 seconds, respectively 3.2 Results of the fabrication of waveguide Figure 3.6 Scanning electron microscope image of silicon dioxide mask lines after isotropic etching in The scanning electron microscope (SEM) image of oxide mask lines after this step is shown in figure 3.6 As we see, the width of second mask line is 1.02 µm, slightly smaller than Chromium mask (1.1 µm) This may be due to diffraction in photolithography or by the fluctuation of room temperature changing etching rate of BHF At micro scale, this error is acceptable Figure 3.7 displays the SEM image of second mask line after etching time is minutes The size of line is reduced from more than 1μm to about 300nm and we can estimate the average rate of undercut – etching is about 60nm per minute This value is smaller than the etching rate in first step In fact, it is hard for me to reduce the size of oxide mask line to less than 100nm The cause is when increasing the under distance, the reaction products is more difficult to move out It prevents the etchant to attack the sidewall of oxide mask lines due to decreasing etch rate over time Moreover, if the sample is embedded in 48 Figure 3.7 Scanning electron microscope image of dioxide mask lines after isotropic etching in minutes BHF solution so long, the photoresist layer can be destroyed Of course, the oxide mask will be destroyed rapidly then For reaction products move out more easily, we can increase the thickness of oxide layer However, the deposited rate of dry oxidation technique is small and it can‘t be used for forming the thick oxide layer We can use wet oxidation for depositing the thick oxide mask, but the oxide which forms by this technique is porous and low quality After the time etching of minutes, the size of top surface is 244nm (Fig 3.8 a) and after minutes, the size is down to 91nm (Fig 3.8 b) Based on these values, we estimate the etching rate in (111) plane is about 16nm per minute and anisotropy ratio is about 90 By calculating the time etching, we can reduce the size of top surface to zero and form a triangular waveguide In summary, we have presented a top-down fabrication method for producing single-crystal silicon waveguides with high throughput based on the standard photolithography technique and KOH wet-bulk micromachining The fabricated single-crystal silicon waveguides are molds for forming the surface plasmonic waveguides after depositing metal layer 49 Figure 3.8 The SEM images of silicon waveguide after anisotropic in (a) and minute (b) 50 CONCLUSIONS  In this thesis, we have proposed wedge plasmon polariton waveguide structures that are based on the etching properties of single crystal silicon in Potassium Hydroxide solution  The thesis also has carried out simulation analysis on the influence of structural parameters on the transmission characteristic of waveguide Electromagnetic wave is confined strongly in a size at nano–scale on the wedge and top surface of structures When decreasing the wedge corner, the distance of two tip or increasing the refractive index of surrounding medium, the confinement is stronger but the attenuation is also increased In the case of very thin metal layer, WPP can couple with the high order mode in silicon dielectric waveguide leading to the variation of propagation characteristics  We also describe a simple and lowcost method to fabricate waveguide structures based on wet–bulk micromachining The size of structure is controlled at nano scale By using this method, we have successfully fabricated a number of structures that are selected from the simulation results SUGGESTED FURTURE WORKS - Establish a measurement setup to verified the obtained results from simulation - Explore a possible solution for integrating the waveguides into optic circuits - Develop coupling mechanism for the waveguide and optical sensors based on the waveguide 51 REFERENCES [1] Ashall, B., ―http://www.ucd.ie/biophysics/surfaceplasmons.html,‖ Plasmonics and Ultrafast NanoOptics [Online] [2] Bian, Y and Q Gong, ―Deep-subwavelength light confinement and transport in hybrid dielectric-loaded metal wedges,‖ Laser Photonics Rev., vol 8, no 4, pp 549–561, 2014 [3] Bian, Y and Q Gong, ―Low-loss hybrid plasmonic modes guided by metal-coated dielectric wedges for subwavelength light confinement.,‖ Appl Opt., vol 52, no 23, pp 5733–41, 2013 [4] Bian, Y., Z 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Hop Nguyen The study of these scientists mainly is on theoretical calculations of bulk plasmon and localized plasmon 1.2 Fundamentals of Surface Plasmon Polaritons Surface plasmon polaritons (SPPs)... FUNDAMENTALS OF PLASMONICS 1.1 History of development 1.2 Fundamentals of Surface Plasmon Polaritons 1.3 Wedge surface plasmon polariton waveguides 1.3.1 Conventional wedge waveguides. .. Hybrid wedge waveguides 1.3.3 Fabrication of wedge waveguides 11 1.3.4 Exciting surface plasmon polariton mode in the wedge waveguide 13 1.3.5 Applications of wedge waveguides