Ultrasonic array research platform (uarp) the receiver side

Project Number: 61 Ultrasonic Array Research Platform (UARP) The Receiver Side THINH HUNG PHAM Submitted in accordance with the requirements for the degree of Master of Science (Eng.) In Embedded Systems Engineering The University of Leeds School of Electronic and Electrical Engineering August 2010 Supervisor Dr S Freear The candidate confirms that the work submitted is his/her own and that appropriate credit has been given where reference has been made to the work of others THINH HUNG PHAM ELEC 5881 Main Project The University of Leeds School of Electronic & Electrical Engineering Declaration of Academic Integrity Student Name: THINH HUNG PHAM [Block Capitals if handwritten] University ID Number: 200508597 Modules: ELEC 5880 & 5881 Module Leader: Dr Chris Trayner Plagiarism in University Assessments and the Presentation of Fraudulent or Fabricated Coursework Plagiarism is defined as presenting someone else’s work as your own Work means any intellectual output, and typically includes text, data, images, sound or performance [1] Fraudulent or fabricated coursework is defined as work, particularly reports of laboratory or practical work that is untrue and/or made up, submitted to satisfy the requirements of a University Assessment in whole or in part [1] Declaration: • I have read the University Regulations on Cheating and Plagiarism [2] and state that the work in this report is my own and does not contain any unacknowledged work from other sources • I confirm that any mitigating circumstances or other matters which might have affected my performance and which I wish to bring to the attention of the examiners/markers have been submitted to the Secretary of the Director of Learning & Teaching [Jennifer Finnigan, School of Electronic & Electrical Engineering] Signed Date THINH HUNG PHAM ELEC 5881 Main Project Acknowledgements I would like to acknowledge and extend my gratitude to Dr Steven Freear, who not only served as my project supervisor but also encouraged and challenged me throughout the course of this project I would also like to thank Dr David Cowell, Mr Peter Smith and Mr Ben Raiton for their continued help, guidance and support throughout this project I also pay my thanks to Mr Bao Bui and Mr Chau Vo with whom I enjoyed working alongside this year to develop the overall UARP system Finally I would also like to thank all other members of the University of Leeds Ultrasound group, especially THINH HUNG PHAM ELEC 5881 Main Project TABLE OF CONTENTS I ABSTRACT II INTRODUCTION 10 II.1 Ultrasonic Imaging 10 II.2 Ultrasonic Array Research Platform (UARP) Project overview 12 II.2.1 ALTERA DE3 Main Board & FPGA Device 14 II.2.2 Receiver Board 14 II.2.3 Transmitter Board 15 II.2.4 Backplane 15 II.2.5 Receiver side 15 II.2.6 Transmitter side 15 II.2.7 Computer side 15 II.2.8 Division of Labour 16 II.3 Altera design tool for system design on FPGA 17 II.3.1 The Altera Quartus II Design Software 17 II.3.2 Chip Planner and Floorplan 17 II.3.3 TimeQuest Timing Analyzer 17 II.3.4 SOPC (System on Programmable Chip) Builder and Nios-II Embedded Design (EDS) 18 III RECEIVER SIDE ON FPGA 19 III.1 Choosing the DE3 board for the receiver side 20 III.2 Configuring the AFE5805 21 III.3 ADC Receiver Channel 23 III.3.1 Double Data Rate Input (DDRI) 25 III.3.2 De-serialised Module 26 III.3.3 Receiver Channel buffer 27 III.3.4 Simulation and result of the receiver channel 29 III.3.5 Packaging the ADC receiver channel 31 THINH HUNG PHAM ELEC 5881 Main Project III.4 SOPC System 32 III.5 Design of the receiver channel system 34 III.5.1 Clock Control for receiver channel system 37 III.5.2 Design Floorplan for receiver channel system 38 III.5.3 Timing Constrain & Analysis for receiver channel system 40 III.5.4 Result of the receiver channel system 47 III.6 Final Design of the 96 receiver channel system 48 III.6.1 Control & Synchronize 96 receiver channels 49 III.6.2 Clock Control for 96 receiver channel system 51 III.6.3 Design Floorplan for 96 receiver channel system 51 III.6.4 Timing Constrain & Analysis for 96 receiver channel system 53 III.6.5 Firmware and testing programme 54 III.6.6 Result of the 96 receiver channel system 55 III.6.7 Result of UARP platform with 96 channel transducer array 57 IV FUTURE WORK 63 V CONCLUSION 64 REFERENCES 65 APPENDIX A - Verilog code for De-Serialized module 67 APPENDIX B - Verilog code for ADC Channel IP module 69 APPENDIX C - Verilog code for ADC_control module 73 APPENDIX D - Verilog code for 96 Receiver Channel System 77 APPENDIX E - Timing Design Constraint for receiver side system111 APPENDIX F - C Code for firmware and testing Matlab script for receiver side system 139 THINH HUNG PHAM ELEC 5881 Main Project LIST OF FIGURES Figure 1: Ultrasound imaging [8] 10 Figure 2: Ultrasonic Arrays [9] 11 Figure 3: Beam forming for an array [9] 12 Figure 4: The block diagram of system [12] 13 Figure 5: Division of Labour 16 Figure 6: Block diagram of receiver system 19 Figure 7: The block diagram of AFE 5805 [21] 22 Figure 8: DDR and SDR interfaces mode 22 Figure 9: The specification of serial data stream from the AFE5805 23 Figure 10: The block diagram of ADC Receiver channel 24 Figure 11: The block diagram of DDIO_IN Megafunction [22] 25 Figure 12: The simulated waveform of DDIO_IN module on the Quartus II 25 Figure 13: The block diagram of the de-serialised module 26 Figure 14: The diagram of combining data 27 Figure 15: The I O ports of DC FIFO [12] 28 Figure 16: The receiver channel buffer 29 Figure 17: Verify the function of receiver channel 30 Figure 18: Packaging the ADC receiver channel 31 Figure 19: Create and instantiate ADC channel IP inside PSOC system 32 Figure 20: Structure of SOPC system 33 Figure 21: The schematic of receiver channel system 36 Figure 22: The configuration of clock control for receiver channel system 38 Figure 23: The result of floorplan design for receiver channel system 39 Figure 24: Clock control for bit clock and frame clock in floorplan of receiver channel system 40 Figure 25: Data arrival path and Clock arrival path [19] 41 Figure 26: Create Virtual Bit Clock 42 Figure 27: Constrain for data transferring between bit clock and frame clock 43 Figure 28: Timing analysis for worst path from input pin to the input of internal register44 Figure 29: Timing analysis for worst path from output to the input of internal registers 45 Figure 30: Timing analysis for worst path between bit clock and frame clock 46 Figure 31: The result of acquiring simultaneously sample of channels 47 THINH HUNG PHAM ELEC 5881 Main Project Figure 32: The ADC_control module in 96 receiver channel system 49 Figure 33: The state machine of ADC_control module 50 Figure 34: The simulation of ADC_control module 50 Figure 35: The floorplan design of 96 receiver channel system 52 Figure 36: The report of timing analysis for 96 receiver channel system 53 Figure 37: The flowchart of testing Matlab script 54 Figure 38: The result of acquiring simultaneously sample of 96 channels 56 Figure 39: The Hardware setup of UARP platform 58 Figure 40: Plotting the received data of one receiver element 59 Figure 41: The test block diagram 60 Figure 42: The result image using one element in sequential 61 Figure 43: The result image with elements in subarray 61 Figure 44: The result image with elements in subarray 62 Figure 45: The result image with 16 elements in subarray 62 THINH HUNG PHAM ELEC 5881 Main Project LIST OF TABLES Table 1: Comparison of Stratix III devices [12] 21 Table 2: The clock control resource of the Stratix III 3SL340 37 Table 3: Resource usage for receiver channel system on Stratix III 3SL340 FPGA 48 Table 4: Resource usage for 96 receiver channel system on Stratix III 3SL340 FPGA 57 Table 5: Input Delay for serial data channels 113 THINH HUNG PHAM ELEC 5881 Main Project I ABSTRACT The aim of project is to develop the receiver side of the Ultrasonic Array Research Platform This Platform is responsible for exciting and receiving up to 96 transducers to perform beam forming and steering The processing of this system is implemented on the Altera DE3 development board manufactured by Terasic The main focus of this project is on the receiver side of the Hardware Platform based on Stratix III FPGA (Field Programmable Gate Arrays), a second MSc project is concentrating on the excitation and drive circuitry in the transmitter side and a third MSc project is concentrating on signal processing on MatLab In the Receiver side, Altera DE3 Board is connected to 12 receiver boards through High Speed Terasic Connectors (HSTC) using a backplane Interconnect Board Each of these receiver cards has Analog to Digital Conversion (ADC) channels So, the receiver side can support a maximum connection of 96 ultrasonic transducers Each ADC channel can sample at speed of up-to 50 mega samples per second where each sample has 12 bits of resolution This results in approximately 53 Giga Bits per second of receiving data The samples of ADC channel are de-serialized and transmitted through Low Voltage Differential Signaling (LVDS) signal Interfacing simultaneously with the serialized data stream of 96 channels at the data rate of 600 Mbps per channel is the most crucial aspect of this project as it requires the highly timing critical design constraint A limited number of phase locked loops (PLL) on the Stratix III FPGA and very few dedicated clock lines available at the HSTC connectors on DE3 board restrict the conventional approaches Therefore, totally customized system has been implemented to accommodate 96 channels without using PLLs and dedicated clock pins This requires the implementation be constrained strictly in the timing and the ploorplan to optimize the multiple high speed receiver channels THINH HUNG PHAM ELEC 5881 Main Project II INTRODUCTION II.1 Ultrasonic Imaging Ultrasonic is now more useful and popular within the industrial [3], [4] and medical fields [5], especially with regards to non-invasive imaging techniques, often for real time imaging reconstruction [6], [7] Ultrasonic imaging is processed similarly to Sonar or Radar and based on the active probing of a subject in order to obtain information derived from differences in time and/or amplitude of echo paths In A mode imaging, the received amplitude of echo paths at a certain time, i.e from a certain depth, can be displayed as energy amplitude The amplitude of echo paths can also be displayed as the brightness of the point in image representing the scatterer, in a B mode imaging In M mode imaging, the moving of some scatterers can be traced by letting the B-mode image sweep across a screen [8] Analysis of a number of pulses directed along different paths enables reconstruction of 2-D, 3-D and even 4-D images The quality of these images depends upon a number of factors including penetration depth, frame rate and resolution [9] 2D imaging Figure 1: Ultrasound imaging [8] Ultrasonic Arrays, which consist of many small elements, provide flexibility not possible with solid apertures The transducer elements are excited by signals phased to steer and focus beams electronically Ultrasonic arrays scan a beam electronically in the XZ 10 THINH HUNG PHAM ELEC 5881 Main Project pu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_ module_sysclk|*jdo*}] set_false_path -from [get_keepers {sld_hub:sld_hub_inst|irf_reg*}] -to [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_c pu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_ module_sysclk|ir*}] set_false_path -from {sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]}] [get_keepers -to [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_o ci_debug|monitor_go}] # # Set fault path for crossing clock domain between frame clock and system clock set_false_path -from [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] - through [get_nets *] -to [get_clocks {frmclk0}] set_false_path -from [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] - through [get_nets *] -to [get_clocks {frmclk1}] set_false_path -from [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] - through [get_nets *] -to [get_clocks {frmclk2}] set_false_path -from [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] - through [get_nets *] -to [get_clocks {frmclk3}] set_false_path -from [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] - through [get_nets *] -to [get_clocks {frmclk4}] set_false_path -from [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] - through [get_nets *] -to [get_clocks {frmclk5}] 135 THINH HUNG PHAM ELEC 5881 Main Project set_false_path -from [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] - through [get_nets *] -to [get_clocks {frmclk6}] set_false_path -from [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] - through [get_nets *] -to [get_clocks {frmclk7}] set_false_path -from [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] - through [get_nets *] -to [get_clocks {frmclk8}] set_false_path -from [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] - through [get_nets *] -to [get_clocks {frmclk9}] set_false_path -from [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] - through [get_nets *] -to [get_clocks {frmclk10}] set_false_path -from [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] - through [get_nets *] -to [get_clocks {frmclk11}] set_false_path -from [get_clocks {frmclk0}] -through [get_nets *] -to [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {frmclk1}] -through [get_nets *] -to [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {frmclk2}] -through [get_nets *] -to [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {frmclk3}] -through [get_nets *] -to [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {frmclk4}] -through [get_nets *] -to [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] 136 THINH HUNG PHAM ELEC 5881 Main Project set_false_path -from [get_clocks {frmclk5}] -through [get_nets *] -to [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {frmclk6}] -through [get_nets *] -to [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {frmclk7}] -through [get_nets *] -to [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {frmclk8}] -through [get_nets *] -to [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {frmclk9}] -through [get_nets *] -to [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {frmclk10}] -through [get_nets *] -to [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {frmclk11}] -through [get_nets *] -to [get_clocks {DE3_SOPC_Instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]}] #************************************************************** # Set Multicycle Path for crossing clock domain between frame clock and bit clock #************************************************************** set_multicycle_path -setup -start -from [get_clocks {bitclk0}] -to [get_clocks {frmclk0}] set_multicycle_path -hold -start -from [get_clocks {bitclk0}] -to [get_clocks {frmclk0}] set_multicycle_path -setup -start -from [get_clocks {bitclk1}] -to [get_clocks {frmclk1}] set_multicycle_path -hold -start -from [get_clocks {bitclk1}] -to [get_clocks {frmclk1}] set_multicycle_path -setup -start -from [get_clocks {bitclk2}] -to [get_clocks {frmclk2}] set_multicycle_path -hold -start -from [get_clocks {bitclk2}] -to [get_clocks {frmclk2}] set_multicycle_path -setup -start -from [get_clocks {bitclk3}] -to [get_clocks {frmclk3}] set_multicycle_path -hold -start -from [get_clocks {bitclk3}] -to [get_clocks {frmclk3}] # -set_multicycle_path -setup -start -from [get_clocks {bitclk4}] -to [get_clocks {frmclk4}] 137 THINH HUNG PHAM ELEC 5881 Main Project set_multicycle_path -hold -start -from [get_clocks {bitclk4}] -to [get_clocks {frmclk4}] set_multicycle_path -setup -start -from [get_clocks {bitclk5}] -to [get_clocks {frmclk5}] set_multicycle_path -hold -start -from [get_clocks {bitclk5}] -to [get_clocks {frmclk5}] set_multicycle_path -setup -start -from [get_clocks {bitclk6}] -to [get_clocks {frmclk6}] set_multicycle_path -hold -start -from [get_clocks {bitclk6}] -to [get_clocks {frmclk6}] set_multicycle_path -setup -start -from [get_clocks {bitclk7}] -to [get_clocks {frmclk7}] set_multicycle_path -hold -start -from [get_clocks {bitclk7}] -to [get_clocks {frmclk7}] # -set_multicycle_path -setup -start -from [get_clocks {bitclk8}] -to [get_clocks {frmclk8}] set_multicycle_path -hold -start -from [get_clocks {bitclk8}] -to [get_clocks {frmclk8}] set_multicycle_path -setup -start -from [get_clocks {bitclk9}] -to [get_clocks {frmclk9}] set_multicycle_path -hold -start -from [get_clocks {bitclk9}] -to [get_clocks {frmclk9}] set_multicycle_path -setup -start -from [get_clocks {bitclk10}] -to [get_clocks {frmclk10}]5 set_multicycle_path -hold -start -from [get_clocks {bitclk10}] -to [get_clocks {frmclk10}] set_multicycle_path -setup -start -from [get_clocks {bitclk11}] -to [get_clocks {frmclk11}]5 set_multicycle_path -hold -start -from [get_clocks {bitclk11}] -to [get_clocks {frmclk11}] 138 THINH HUNG PHAM ELEC 5881 Main Project APPENDIX F - C Code for firmware and testing Matlab script for receiver side system • Test Script of Matlab for receiver system Read and plot 48 channels of 96 channels script close all DEPTH = 8*1024; % set depth of channel % Load Dll for USB driver loadlibrary USB_dll USB_dll.h dptr = libpointer('uint8Ptr',zeros(48*DEPTH,1)); %16KB a = calllib('USB_dll', 'open_dev') if (a < 0) error('USB error') end % -% Configure receiver board calllib('USB_dll', 'set_channel_capacity',DEPTH); // configure depth of channel depth = calllib('USB_dll', 'read_channel_capacity') US_set_rxDelay(100) % set delay counter in ADC _control US_Set_ADC_Defaults(1) % configure board US_Set_ADC_Defaults(2) US_Set_ADC_Defaults(3) US_Set_ADC_Defaults(4) US_Set_ADC_Defaults(5) US_Set_ADC_Defaults(6) % US_Set_ADC_Defaults(7) % US_Set_ADC_Defaults(8) % US_Set_ADC_Defaults(9) % US_Set_ADC_Defaults(10) % US_Set_ADC_Defaults(11) % US_Set_ADC_Defaults(12) % -% Set enable receiver channel % US_Set_rxChannel_Enable('00000000','00000000','00FFFFFF','00FFFFFF') US_Set_rxChannel_Enable('00FFFFFF','00FFFFFF','00000000','00000000') 139 THINH HUNG PHAM ELEC 5881 Main Project % % Start receiving data -US_RX_start calllib('USB_dll','read_asyn_init',hex2dec('AA000A00'),1,48); % - for i=1:10 % read receiving data -a = calllib('USB_dll','read_asyn_finish',dptr) % % read receiving new data -US_RX_start calllib('USB_dll','read_asyn_init',hex2dec('AA000A00'),1,48); % - % processing data -data = reshape( typecast(dptr.value(1:48*DEPTH),'int16'), DEPTH/2, 48 ); data = double(data); % -% ploting data -figure (1) scrsz = get(0,'ScreenSize'); set(1,'Name','Simulation Plot channels to 48 ','Position',[10 10 scrsz(3) scrsz(4)]); subplot(8,6,1); plot(data(:,1)); subplot(8,6,7); plot(data(:,2)); subplot(8,6,13); plot(data(:,3)); subplot(8,6,19); plot(data(:,4)); subplot(8,6,25); plot(data(:,5)); subplot(8,6,31); plot(data(:,6)); subplot(8,6,37); plot(data(:,7)); subplot(8,6,43); plot(data(:,8)); subplot(8,6,2); plot(data(:,9)); subplot(8,6,8); plot(data(:,10)); 140 THINH HUNG PHAM ELEC 5881 Main Project subplot(8,6,14); plot(data(:,11)); subplot(8,6,20); plot(data(:,12)); subplot(8,6,26); plot(data(:,13)); subplot(8,6,32); plot(data(:,14)); subplot(8,6,38); plot(data(:,15)); subplot(8,6,44); plot(data(:,16)); subplot(8,6,3); plot(data(:,17)); subplot(8,6,9); plot(data(:,18)); subplot(8,6,15); plot(data(:,19)); subplot(8,6,21); plot(data(:,20)); subplot(8,6,27); plot(data(:,21)); subplot(8,6,33); plot(data(:,22)); subplot(8,6,39); plot(data(:,23)); subplot(8,6,45); plot(data(:,24)); subplot(8,6,4); plot(data(:,25)); subplot(8,6,10); plot(data(:,26)); subplot(8,6,16); plot(data(:,27)); subplot(8,6,22); plot(data(:,28)); subplot(8,6,28); plot(data(:,29)); subplot(8,6,34); plot(data(:,30)); subplot(8,6,40); plot(data(:,31)); subplot(8,6,46); plot(data(:,32)); subplot(8,6,5); plot(data(:,33)); subplot(8,6,11); plot(data(:,34)); subplot(8,6,17); plot(data(:,35)); subplot(8,6,23); plot(data(:,36)); subplot(8,6,29); plot(data(:,37)); subplot(8,6,35); plot(data(:,38)); subplot(8,6,41); plot(data(:,39)); subplot(8,6,47); plot(data(:,40)); subplot(8,6,6); plot(data(:,41)); subplot(8,6,12); plot(data(:,42)); subplot(8,6,18); plot(data(:,43)); subplot(8,6,24); plot(data(:,44)); 141 THINH HUNG PHAM ELEC 5881 Main Project subplot(8,6,30); plot(data(:,45)); subplot(8,6,36); plot(data(:,46)); subplot(8,6,42); plot(data(:,47)); subplot(8,6,48); plot(data(:,48)); pause(0.1); % read receiving data end a= calllib('USB_dll','read_asyn_finish',dptr); % read the remained data % Un load DLL -'close device' a = calllib('USB_dll', 'close_dev') clear dptr; clear dptrtx; unloadlibrary USB_dll % - function US_Set_ADC_Defaults( Board ) delay = 0.5 US_Send_ADC_SPI( Board, '00', '0001' ) % Reset ADC Board US_Send_ADC_SPI( Board, '00', '0001' ) % Reset ADC Board pause(delay) US_Send_ADC_SPI( Board, '11', '0444' ) % Set drive current to 7.5 mA pause(delay) US_Send_ADC_SPI( Board, '46', '8204' ) % Set output format to two's complement pause(delay) US_Send_ADC_SPI( Board, '25', '0040' ) % Set output RAM pause(delay) function US_Send_ADC_SPI( Board, Address, Command ) % Board Number (8 bit dec) % SPI Address (8 bit hex) % SPI Data (16 bit hex) SPI_Address = dec2hex( hex2dec(Address), ) 142 THINH HUNG PHAM ELEC 5881 Main Project SPI_Command = dec2hex( hex2dec(Command), ) US_Command = [ 'AA' dec2hex(Board,2) dec2hex(128,2) '00' ] US_Data = ['00' SPI_Address SPI_Command ] % write command to DE3 board a = calllib('USB_dll', 'write_dev_parameter', hex2dec(US_Command),hex2dec(US_Data)) function US_Set_rxChannel_Enable(Rxen1, Rxen2, Rxen3, Rxen4) US_Command = [ 'AA' dec2hex(0,2) dec2hex(5,2) dec2hex(0,2) ]; %set enable 24-1 a = calllib('USB_dll', 'write_dev_parameter', hex2dec(US_Command), hex2dec(Rxen1) ); US_Command = [ 'AA' dec2hex(0,2) dec2hex(6,2) dec2hex(0,2) ]; %set enable 48-25 a = calllib('USB_dll', 'write_dev_parameter', hex2dec(US_Command), hex2dec(Rxen2) ); US_Command = [ 'AA' dec2hex(0,2) dec2hex(7,2) dec2hex(0,2) ]; %set enable 72-49 a = calllib('USB_dll', 'write_dev_parameter', hex2dec(US_Command), hex2dec(Rxen3) ); US_Command = [ 'AA' dec2hex(0,2) dec2hex(8,2) dec2hex(0,2) ]; %set enable 96-73 a = calllib('USB_dll', 'write_dev_parameter', hex2dec(US_Command), hex2dec(Rxen4) ); • C code of main file for Nios firmware #include #include #include #include "terasic_includes.h" "terasic_usb_isp1761\usb_device\bulk_device.h" #ifdef DEBUG_APP // 20100201 chau #define DEBUG_OUT(x) {printf("[APP]"); printf x;} #define DEBUG_ERR(x) {printf("[APP_ERR]!!!"); printf x;} #else #define DEBUG_OUT(x) #define DEBUG_ERR(x) #endif // Communications variables alt_u32 US_Data; alt_32 US_Command; alt_32 adc_en1, adc_en2, adc_en3, adc_en4; alt_32 US_Command; alt_u8 *pUS_Channel = (char *)&US_Command; alt_u8 *pUS_Command; alt_u8 *pUS_Board; alt_u8 *pUS_Check; // define command for testing receiver, included by Thinh #define SET_ADC_DELAY #define SET_ADC_EN_R1 #define SET_ADC_EN_R2 #define SET_ADC_EN_R3 #define SET_ADC_EN_R4 143 THINH HUNG PHAM ELEC 5881 Main Project #define SET_ADC_START #define RD_DATA_CHANNEL #define DEPTH 8*1024 // Depth of channel void welcome_led(void){ const alt_u32 led_delay = 500*1000; DEBUG_OUT(("S welcome_led\n")); // 20100201 chau IOWR(PIO_LED_BASE,0, 0xFFFF00); // blue usleep(led_delay); IOWR(PIO_LED_BASE,0, 0xFF00FF); // green usleep(led_delay); IOWR(PIO_LED_BASE,0, 0x00FFFF); // red usleep(led_delay); IOWR(PIO_LED_BASE,0, 0xFFFFFF); // black usleep(led_delay); IOWR(PIO_LED_BASE,0, 0x000000); // while usleep(led_delay); DEBUG_OUT(("E welcome_led\n")); // 20100201 chau } // #define DATAIN_LEN #define DATAOUT_LEN 2048 alt_u8 szBulkDataIn[DATAIN_LEN]; alt_u8 szBulkDataOut[DATAOUT_LEN]; BULK_HANDLE hBulk = 0; void void void void void void WriteData(BULK_HANDLE hBulk, alt_u32 length); // testing only ReadOneChannel(BULK_HANDLE hBulk, alt_u32 length); ReadChannels(BULK_HANDLE hBulk, alt_u32 position); Notify_DeviceReady(void); Notify_DataIn(alt_u8 *pData, alt_u32 bytes); Notify_DataOutComplete(void); alt_u32 Position; // 20100202 chau, testing only void WriteData(BULK_HANDLE hBulk, alt_u32 length){ alt_u8* p; DEBUG_OUT(("S WriteData\n")); // 20100201 chau p = (alt_u8*)IP_ADC_CHANNEL_1_BASE; BULK_Write(hBulk, p, length); // 20100201 chau DEBUG_OUT(("E WriteData\n")); } // included by Thinh // read reciver channels // MSB byte of position parameter indicates first channel to read // Next byte of position parameter indicates number of channel to read void ReadChannels(BULK_HANDLE hBulk, alt_u32 position){ alt_u8 ch; alt_u8 num; ch = (position >> 24) & 0xFF; num = (position >> 16) & 0xFF; alt_u8* p; p = (alt_u8*)IP_ADC_CHANNEL_1_BASE + (ch-1) * DEPTH; BULK_Write(hBulk, p, num * DEPTH); } void Notify_DeviceReady(void){ 144 THINH HUNG PHAM ELEC 5881 Main Project DEBUG_OUT(("S Notify_DeviceReady\n")); // 20100201 chau DEBUG_OUT(("Device Ready\n")); if (!hBulk) return; BULK_Read(hBulk, szBulkDataIn, sizeof(szBulkDataIn)); DEBUG_OUT(("E Notify_DeviceReady\n")); // 20100201 chau } // Call back function when Computer send command to DE3 Board void Notify_DataIn(alt_u8 *pData, alt_u32 bytes){ DEBUG_OUT(("S Notify_DataIn\n")); // 20100201 chau DEBUG_OUT(("Data In, len=%d\n", (int)bytes)); alt_u32 rxfull1, rxfull2, rxfull3, rxfull4, timeout; if (!hBulk) return; if (bytes == DATAIN_LEN){ // update led alt_u8 OP; alt_u32 Command32[2]; alt_u32 *spi_rdData; alt_u8 channel; alt_u32 shifted; memcpy(&Command32, pData, sizeof(Command32)); US_Command = Command32[0]; US_Data = Command32[1]; DEBUG_OUT(("US_Command, len=%X\n", US_Command)); DEBUG_OUT(("US_Data, len=%X\n", US_Data)); // Check if comms byte is correct if ( *pUS_Check == 0xAA ){ // Determine which card receives the command switch(*pUS_Board) { // DE3 - Stratix case 0: switch(*pUS_Command) { case : // LEDs Black IOWR(PIO_LED_BASE, 0, US_Data & 0xFFFFFF); break; case : // Pulse all transmitting channels IOWR_ALTERA_AVALON_PIO_DATA(PIO_PULSE_BASE, 0x1); IOWR_ALTERA_AVALON_PIO_DATA(PIO_PULSE_BASE, 0x1); IOWR_ALTERA_AVALON_PIO_DATA(PIO_PULSE_BASE, 0x1); IOWR_ALTERA_AVALON_PIO_DATA(PIO_PULSE_BASE, 0x0); break; case : // Disable pulse devices break; case : // Enable pulse devices break; case : // Set ADC delay IOWR(GPO_0_BASE, 0, US_Data); break; case : // Enable channel 23 - IOWR(CHANNEL_RXEN_R1_BASE, 0, US_Data); break; 145 THINH HUNG PHAM ELEC 5881 Main Project case : // Enable channel 47 - 24 IOWR(CHANNEL_RXEN_R2_BASE, 0, US_Data); break; case : // Enable channel 71 - 48 IOWR(CHANNEL_RXEN_R3_BASE, 0, US_Data); break; case : // Enable channel 95 - 72 IOWR(CHANNEL_RXEN_R4_BASE, 0, US_Data); break; case : // Start receiving after a delay time IOWR(ADC_START_BASE, 0, 0x00000000); IOWR(ADC_START_BASE, 0, 0x00000001); while (IORD(ADC_FULL_BASE, 0)); break; case 10 : // Read channels timeout =0; while ((! IORD(ADC_FULL_BASE, 0)) & (timeout