Development board for the icycam soc

Master Project Development Board for the IcyCAM Soc Tuan-Thanh VU Supervisor: René Beuchat External Expert: Edoardo Franzi Jan 2011 Table of Contents Table of Contents i List of Figures iii List of Tables iv Acknowledgments v Introduction 1.1 IcyCAM Soc [1] 1.2 Project’s Objectives System Architecture 2.1 Minimum Configuration 2.2 Complete Configuration 2.3 Decision for the development board 2.3.1 The ARM Cortex-M3 based microcontroller 2.3.2 The CPLD Development board for IcyCAM and ARM Cortex-M3 3.1 3.1.1 System Block Diagram 3.1.2 Power 3.1.3 Altera MAX II 10 3.1.4 ARM Cortex-M3 based STM32 microcontroller 11 3.1.5 Common Devices 12 3.1.6 Pseudo Static RAM 13 3.1.7 FTDI USB to JTAG 15 3.1.8 FTDI USB to FIFO 15 3.1.9 IcyCAM Daughter Connectors 16 3.2 Schematic Design Layout Design 17 Configuring the Altera MAX II 18 4.1 Bus control for common devices 18 4.2 PPI to FTDI FIFO and PSRAM Controller 20 4.3 Serial EEPROM multiplexer 21 4.4 Result 21 Software Development 22 i 5.1 Software development for STM32 microcontroller 22 5.2 Software development for IcyCAM 22 5.3 Demonstration Application 23 Conclusion 24 References 25 Annexes 26 8.1 Configuring PSRAM operation mode 26 8.2 Yagarto, OpenOCD and Eclipse for the STM32 27 8.3 IcyCAM Parallel Peripheral Interface Bridge 31 8.4 SD Card direction control in the CPLD 33 8.5 Modifications for the IcyCAM Minipack software 34 ii List of Figures Figure 1.1 : The new development board with the IcyCAM sensor board Figure 1.2: The IcyCAM Soc Block Diagram Figure 1.3 : IcyCAM Soc Specifications Figure 1.4: The CSEM IcyBoard and the IcyCAM sensor board Figure 1.5: Block Diagram of the IcyCAM MiniPack Figure 2.1: The minimum configuration for IcyCAM development board Figure 2.2: The complete configuration for IcyCAM development board Figure 3.1: System Block Schematic Figure 3.2 : Porwer supply block diagram 10 Figure 3.3: Configuring the CPLD 11 Figure 3.4: Common Elements 13 Figure 3.5: 8Mi x 16b PSRAM Function Block Diagram [5] 14 Figure 3.6: USB to JTAG and UART using FTDI 4232H 15 Figure 3.7: IcyCAM GPIOs and PPI to FTDI FIFO 16 Figure 3.8: Interaction between IcyCAM sensor board and the CPLD 16 Figure 3.9: TOP Layer 17 Figure 3.10: BOTTOM Layer 17 Figure 4.1: Function Block Diagram of Altera MAX II device 18 Figure 4.2: STM32 and IcyCAM GPIO to common elements 19 Figure 4.3: Common device access timing diagram 20 Figure 4.4: PPI to FDTI FIFO and PSRAM controller block diagram in the MAX II 20 Figure 4.5: SPI multiplexer for serial EEPROM on IcyCAM daughter board 21 Figure 5.1 : Softwrare development process 22 Figure 5.2: Software Configuration 23 Figure 5.3: Software Configuration 23 Figure 8.1 : Configuration Register WRITE, Asynchronous Mode 26 Figure 8.2: Configuration Register WRITE, Synchronous Mode 26 Figure 8.3 : Load Configuration Register 27 Figure 8.4 : The IcyCAM PPI to PSRAM controller timing diagram 32 Figure 8.5 : The IcyCAM PPI to FTDI FIFO timing diagram 33 Figure 8.6: micro SD Card multiplexer 33 Figure 8.7 : SDIO Command direction control timing diagram 34 iii List of Tables Table 3.1 : Power Consumption of Components 10 Table 3.2 : MAX II Family Features [3] 11 Table 3.3 : ARM Cortex-M3 based Microcontrollers comparision 12 Table 3.4 : PSRAM internal control registers [5] 14 Table 4.1 : Common devices address 19 iv Acknowledgments I would like to express my gratitude to: My supervisors – René Beuchat at Processor Architecture Laboratory – EPFL Though his valuable guidance, I have obtained relevant research skills as well as followed the right research direction My parents and my friends who have understood and shared with me joys and sorrows in my life Finally, for two years, my studies were sponsored by EPFL and ELCA infomatique SA Therefore, I would like to thank EPFL and ELCA for their supports Tuan-Thanh Vu Lausanne, Switzerland January, 2011 v - INTRODUCTION Introduction Nowadays, a lot of vision applications are developed in many fields Most of usual applications not work well with a high dynamic range of illumination because their data representation is linear with the environment illumination Moreover, they are often complicated designs including separated camera sensor, graphic processing unit and a microcomputer to control the whole system The IcyCAM Soc from CSEM (Swiss Center for Electronics and Microtechnology) provides a complete solution for these applications in an intra-scene dynamic range environment with a single chip With the help from CSEM, the main objective of this master project is to design a development board to explore different applications for this new and advanced Soc This new development board can be a Multiprocessor Embedded System with many development device and interfaces (minis SD Card, USB, CAN, SPI, I2C, etc…) to perform complex vision systems This section will make a resume on the IcyCAM Soc and the project’s objectives Figure 1.1 : The new development board with the IcyCAM sensor board 1.1 IcyCAM Soc [1] The IcyCAM Soc integrates a high dynamic range QVGA (320x240) monochrome camera sensor, a 32-bit DSP/MCU icyflex1 with 64-bit memory bus, 128 KiB of SRAM together with several peripheral interfaces on a single chip With a specific time-domain logarithmic encoding, the IcyCAM Soc gives higher quality images than original logarithmic representations in intra-scene dynamic range aspect Moreover, the images can be represented in contrast magnitude and direction so that the system can make some vision analyses In addition, the graphic processing unit reduces workload for the icyflex1 in specific graphic tasks Figure 1.1 and Figure 1.2 show the block diagram and the key characteristics of this Soc The main features of the IcyCAM Soc are listed below For more detail, refer to the Soc specification 1 - INTRODUCTION – – – – – – – – – – – – – High dynamic range QVGA (320x240) pixel array 32-bit DSP / MCU icyflex1 processor DMA function, 64-bit data bus Contrast and Orientation computation in the data readout path Graphical Processing Unit (GPU) 32-bit 100 MHz SDRAM interface 12-bit Parallel Peripheral Interface (PPI) Serial Peripheral Interfaces (SPI) 16-bit General Purpose I / O Interface (GPIO) UART interface JTAG interface Programmable in C (GNU tool suite) Max system clock rate: 33 MHz Figure 1.2: The IcyCAM Soc Block Diagram Figure 1.3 : IcyCAM Soc Specifications - INTRODUCTION To help developers getting start with this new Soc, CSEM provide the smallest development board called the IcyCAM MiniPack accompanied with development tools The IcyCAM MiniPack includes – A PCB motherboard called IcyBoard – A daughter board on which IcyCAM is mounted – Power management, switches, LED, USB interfaces to a PC – Eclipse IDE with CDT C/C++, GNU C/ASM Compiler for icyflex1 plug-in Figure 1.4 shows the real view of this kit, and the block schematic of the IcyBoard is illustrated in next figure Figure 1.4: The CSEM IcyBoard and the IcyCAM sensor board Figure 1.5: Block Diagram of the IcyCAM MiniPack 1.2 Project’s Objectives The objective of this master project is to expand the IcyCAM MiniPack to a complex vision system which is based on the IcyCAM Soc One of the applications is called “last minute images” that can store pictures from the IcyCAM Soc into a SD Card so that we can review the environment images offline for security, surveillance purposes Moreover, the system should have capability to communicate with other systems to increase its functionality According to the objectives, following tasks were proposed and finished during the master project time: - Investigate the system architecture and software development of the IcyCAM Soc as well as the MiniPack - INTRODUCTION - Propose and decide system architecture for the new design Design PCB schematic and layout of the development board using Altium Design Summer 09 – a well-known tool for electrics design Test the implemented PCB Develop demonstration applications The four next sections will describe the works that have been done during the project They include system architecture, schematic and layout design, hardware configuration and software development 4 – CONFIGURING THE ALTERA MAX II To start a data transfer on PPI, the IcyCAM Soc has to send the address 0x4 to the bus control (section 4.1) The bits 7-6 of the written byte will decide the destination of PPI data – “10” for FTDI FIFO, “11” for the PSRAM, and “0x” for none In case of the PSRAM, PPI will send the memory address in four first words, then the data length in next four words (only 8bit/word is used for both address and length) and finally the data themselves Because both processors can access to the memory it is necessary to have an arbitrator scheme in this case There are two specific signals between the controller and the ARM side: bus request and bus grant In this design, the memory arbitrator is placed in the ARM side Therefore, when PSRAM controller in the CPLD wants to access the memory, it sends a bus request signal to the STM32 and wait for bus grant signal If the bus grant is active, the PPI data is started writing to the memory During the writing time, the request signal is always active until the last word so that the ARM will know when the transfer is finished and take control of the memory According to this implement, image data are sent to the onboard memory from IcyCAM so that the STM32 can access them, make some processing and store the pictures to the SD Card 4.3 Serial EEPROM multiplexer As mention in section 3.1.9, there is not flash ROM inside the IcyCAM Soc and therefore he serial EEPROM will store program offline This code will be loaded to IcyCAM SRAM through its SPI1 at reset time The designed board allows different ways to access this EEPROM: external SPI device, the STM32 and the IcyCAM itself The CPLD provides a multiplexer (Figure 4.5) so that we can choose which one can access to the EEPROM on the Icy daughter board ICYCAM SPI 00 01 STM32 SPI External SPI (Aardvark SPI) EEPROM MUX 10 SPI EEPROM 11 SELECT[1 0] Figure 4.5: SPI multiplexer for serial EEPROM on IcyCAM daughter board 4.4 Result In addition to three main functions, the MAX II connects other interfaces from the STM32 and the IcyCAM Soc to RS232 transceiver, mini SD Card connector, etc…All functions require about 800 logic element, most of them are used by the PPI to PSRAM controller This number takes 37% of EPM2210 and 63% of EPM1270 Thus, with remain resources we can implement other bridges and controllers such as PPI to SDIO controller so that the IcyCAM SoC can use its PPI to transfer image data to a SD Card directly with higher speed than SPI 21 – SOFTWARE DEVELOPMENT Software Development The final job of the project is to investigate the software development process for the development board including the STM32 and the IcyCAM Soc and develop some test applications to ensure that the board performs its objectives correctly For the STM32, there are a lot of instructions how to develop software for the device on the Internet This section only makes some remarks on using open source GCC for the ARM core and OpenOCD to debug through FTDI USB to JTAG emulator On the IcyCAM Soc side, CSEM provides development toolchains accompanied with sample applications for the IcyCAM MiniPack These examples can be reused for the new design Figure 5.1 gives an overview of the tools used for debugging and programming the both processors ECLIPSE C/C++ IDE YAGARTO STM32 Port 3333 OpenOCD JTAG STM32 JTAG ICYCAM USB FTDI 2232 DLL ECLIPSE C/C++ IDE ICYFLEX1 GNU TOOL FTDI 4232 ICFX1 RUN JTAG DEV BOARD PC Figure 5.1 : Softwrare development process 5.1 Software development for STM32 microcontroller The tools which are used to develop software for the STM32 include: - Yagarto: a free GNU ARM toolchain (compiler, linker, debugger) OpenOCD: the Open On-Chip Debugger, a gdb server interface with JTAG adapter Eclipse: a free IDE to develop the C/C++ program for embedded processor There are some remarks on configuring OpenOCD to interface with the FTDI 4232, please refer to Annex 8.2 for more technical detail Finally, some simple examples have been developed to test basic functions of the STM32 such as GPIO, UART, External Interrupt, SDIO and Timer We can find these projects in my master project’s CD In this CD, there is also a project that ports microC/ OS II RTOS to the ARM core From this example, we can develop a system in the STM32 with microC/OS II RTOS For more detail on the microC/ OS II porting for the STM32, please refer to Micrium webpage [8] 5.2 Software development for IcyCAM Thanks to CSEM, they provide a complete solution to develop application for the IcyCAM Soc in the IcyCAM MiniPack The development tools include: 22 – SOFTWARE DEVELOPMENT - Cross-compiler tools for different platforms with documents Example source code to get start with the IcyCAM Soc Then, we can configure an Eclipse IDE to use these tools to develop software The developed source code includes drivers for most of standard interfaces (GPIO, FTDI USB2FIFO, PPI, etc…) Thus, we can reuse these drivers and adapt to the new board design with minor modifications The tutorial how to use IcyCAM tools is showed in the IcyCAM MiniPack document [9] 5.3 Demonstration Application A demonstration application has been proposed and developed to demo the whole operation of the designed board Because of reconfigurable capacity there are some configurations for the application The main configuration is that the IcyCAM Soc captures images and sends them to the PSRAM Then the STM32 reads these images and stores into a mini SD Card (Figure 5.2) IcyCAM Soc Image data 128Mb PSRAM Image data STM32 Image data SD Card Figure 5.2: Software Configuration Another one is that the STM23 and the IcyCAM Soc operate independently (Figure 5.3) In this configuration, the STM32 acts as a USB to SD Card reader so that the images in SD card can be viewed and modified through STM32 USB interface In the mean time, the IcyCAM Soc can communicate with a PC to send capturing pictures and other data via FTDI USB to FIFO USB Cable FT2232H Image data IcyCAM Soc USB Cable STM32 Figure 5.3: Software Configuration 23 Image data SD Card – CONCLUSION Conclusion The architecture for the project which can be a multiprocessor vision system was proposed and analyzed There are connectors to the IcyCAM daughter board The FTD2232 device provides image transfer between the IcyCAM Soc and a PC The ARM Cortex-M3 based STM32 microcontroller is integrated to the design and makes the system powerful The FTD4232 provides JTAG debugger and programmer for both the STM32 and the icyflex1 The 8Mi x16b PSRAM from Micron expands the program and data memory for the STM32 or play as a shared memory between the two processors The mini SD Card connector allows a SD Card to connect to the board and store captured images Several common devices are also included for input/output purposes The last and important component is the Altera MAX II It performs a router in the center of the design that provides reconfigurable connections and bridges between other components The design board is finished developing by using Altium tools The PCB has been tested and mounted by myself There is not serious error, we can program and debug the STM32 through FTD4232 JTAG emulator The IcyCAM Soc and the FTD2232 also perform correctly their functionality In the mean time, the demo software is being developed Finally, the main objectives have been done In the future, the board can be used to develop more complex applications such as implement some image compression algorithm in the STM32 and perform some graphic processing in the IcyCAM Soc The design can be improved by replacing with new ARM based microcontroller to have both Ethernet and SDIO, adding some develop components that communicate via standard interfaces (I2C, UART or SPI) 24 References [1] CSEM The IcyCAM Soc specification, 2009 [2] NRTR project https://wiki.lii.eig.ch/index.php/Projet_NTRT [3] Altera MAX II Device Family Data Sheet, 2009 [4] STMicroelectronics Technology STM32F MCUs, http://www.st.com/internet/mcu/subclass/1169.jsp [5] Micron Technology Async/Page/Burst CellularRAM 1.5 MT45W8MW16BGX, 2007 [6] YAGARTO Yet another GNU ARM toolchain, http://www.yagarto.de/ [7] OpenOCD Open On-Chip Debugger http://openocd.berlios.de/web/ [8] Micrium STM32 http://micrium.com/page/downloads/ports/st/stm32 [9] CSEM The IcyCAM MiniPack Documents v1.4, 2010 [10] Future Technology Devices International Ltd FT2232H Dual High Speed USB to Multipurpose UART/FIFO IC, 2010 [11] Future Technology Devices International Ltd FT2232H Quad High Speed USB to Multipurpose UART/MPSSE IC, 2010 25 – ANNEXES Annexes 8.1 Configuring PSRAM operation mode There are two ways to access the PSRAM control registers before using it in the chosen mode First, when the control register enable (CRE) input pin is HIGH, the Cellular RAM goes to configure mode either in synchronous or asynchronous mode The A19:A18 select a register and the value will be placed on other address lines Figure 8.1 and Figure 8.2 show timing diagram to write the registers in both operation modes Figure 8.1 : Configuration Register WRITE, Asynchronous Mode Figure 8.2: Configuration Register WRITE, Synchronous Mode Another way to access the registers without using CRE pin is to use a sequence of asynchronous READ and WRITE operations This is called software configuration Figure 26 – ANNEXES 8.3 describes this sequence For more detail on this memory device, please refer to its datasheet [5] from Micron website Figure 8.3 : Load Configuration Register 8.2 Yagarto, OpenOCD and Eclipse for the STM32 Yagarto [6] is a free GNU tool chain for the ARM processor developed by Michael Fischer The main features are that it is not based on Cygwin, works with Eclipse IDE and free It has been developing and completing by open community However, this tool is good for nonprofit and students’ projects For more detail and toolchain download, please visit Yagarto website at http://www.yagarto.de Together with Yagarto, OpenOCD [7] (open on-chip debugger) provides debugging, in system programming and boundary-scan testing for the embedded processor (including ARM core) It plays a role of a local gdb debug server on a PC that receives command from gdb and uses a JTAG adapter to communicate with the JTAG complaints TAPs on target board Many of the available JTAG adapters are based on FTDI FT2232 chip from “Future Technology Devices international” This project also refers to these adapters’ design so that we can use free OpenOCD to debug and program the ARM Cortex-M3 core We can download this open source and a lot of documents at its homepage http://openocd.berlios.de OpenOCD uses default FTDI channel A for JTAG emulator However, in this project the channel A is reserved for IcyCAM JTAG, and the JTAG channel for the ARM is moved to channel B Unfortunately, with the newest version of OpenOCD we cannot change the FTDI channel without modifying the source code and rebuild the OpenOCD If libusb_ftd2232 is used to build OpenOCD, we have to go to line 2016 of the file ft2232.c and modify INTERFACE_A to INTERFACE_B 27 – ANNEXES In case of using D2XX Direct Drivers FTDI, OpenOCD will check the channel description that is input from a cfg file when run OpenOCD However, it only accept channel A description (has letter “A” at the end of descriptor) To change this we can go to line 2845 and 2856 in the file ft2232.c and change letter “A” to “B” After making these modification, rebuild OpenOCD according to [2] and then we can use for this project The well-known Eclipse provides a free IDE to develop the C/C++ program for embedded processor This IDE can be configured to work with different cross-compilers and provide graphic user interface for gdb debugger The three Yagarto, OpenOCD and Eclipse provide a complete solution to develop applications for this project on the ARM processor The tutorial how to use these tools for the ARM Cortex-M3 core is based on the wiki of the NRTR project [2] This tutorial uses Sourcery G++ Lite Edition for ARM EABI instead of Yagarto However, there is the same way to configure the Eclipse to use Yagarto and Sourcery If we want to program directly to the ARM device without run the gdp, we can configure the OpenOCD run as external tool in the Eclipse with an extra configuring file together with a usual openocd.cfg file The extra configuration file in this demo named openocd_burn.cfg with the following content init soft_reset_halt sleep 1000 stm32x mass_erase flash write_image /out/icyarm_demo.bin 0x08000000 reset run shutdown The following tutorial shows steps to setup the OpenOCD run as external tool in Eclipse 28 – ANNEXES First, we setup a new external tool Then, create new external tool, select openocd.exe for the executing tool, and enter the parameter (configuration file) Finally click Apply and Run to download program 29 – ANNEXES After the board is plugged into the PC, for the first time when run this external tool, an error message will happen like this Ignore this message; retry again and from the second time there is no error 30 – ANNEXES In case of not using Eclipse to invoke the OpenOCD, we can run the OpenOCD from a system command line tool by typing this line openocd.exe –f openocd.cfg –f openocd_burn.cfg Another important when using the OpenOCD is a configuration file which stores the information of the FTDI device of the JTAG adapter In this demo, its name is jtagIcyCAM_ARM.cfg This configuration file is called from the openocd.cfg file To adapt with the FTDI device, the device descriptor, VIP and PID must be set to the right value according to the using FTDI These FTDI parameters can be program for the device by using FT_PROG program from FTDI site (www.ftdichip.com) 8.3 IcyCAM Parallel Peripheral Interface Bridge This annex describe timing diagram for data transfer between IcyCAM Parallel Peripheral Interface (PPI) to the PSRAM memory and the FTDI FIFO via the bridge inside the CPLD From IcyCAM PPI the data can transfer to the PSRAM or the FTDI FIFO, there is a demultiplexer to switch the destination of the data To enable this switch, a pseudo GPIOs command is written to the PPI address inside the CPLD The CPLD PPI address is 0x04, and the MSB (b7) of written byte will enable or disable transfer, the next bit (b6) will decide destination of the transfer (0: FTDI FIFO, 1: PSRAM) Once the command is executed, the demultiplexer will send the data to the corresponding bridge The PPI_DVALID signal is generated by the bridge to the IcyCAM PPI; the PPI will look this signal on the falling edge of PPI_CLK to send out the next data 31 – ANNEXES At this time the PSRAM controller for IcyCAM PPI was implemented in asynchronous mode and works correctly There is no FIFO buffer between IcyCAM PPI and the controller, therefore the PPI will wait until the data is finished writing to the memory First of all, to start a transaction to the PSRAM, the PPI sends out byte address, the bridge get these address bytes as start address then look on the BusGrant_n signal from the ARM to get the access right When it has the memory bus, the controller enables PPI_DVALID signal to the PPI to get data, two data bytes from the PPI are encoded to one 16b word Then the bridge writes to the memory in two PPI_CLK cycles (120ns) Thus, it takes four PPI_CLK cycles two finished writing two PPI data bytes The entire PSRAM interface signals will be in High-Z when the BusGrant_n is inactive After the last PPI data is sent, a stop command must be issue by using pseudo GPIO bus Figure 8.4 shows the timing diagram of this bridge BusR eq_n (Icy CAM) Start cmd Stop cmd ~60ns PPI_CLK PPI_DVALID_NEXT PP_DVALID PPI_DATA[7 0] AD_B0 AD_B1 AD_B2AD_B3 D0 D1 BusGrant_n (AR M) PSRAM_AD V_n PSRAM_OE_n PSRAM_WE_n PSRAM_D ATA[15 0] D3 PSRAM bridge access the memory PSRAM_AD [22 0] PSRAM_C E_n D2 AD AD+1 High-Z High-Z Write cy cle High-Z write 16bit data High-Z High-Z D0 D1_D0 D2 write second data D3_D2 Figure 8.4 : The IcyCAM PPI to PSRAM controller timing diagram The synchronous mode have been designed, there is an Altera dual clock FIFO buffer between the IcyCAM PPI and the PSRAM Controller However, this FIFO buffer does not work correctly Therefore, this design can be improved in the future so that the advance synchronous burst mode can be use The FTDI FIFO bridge for the IcyCAM PPI is referred from the Minipack software, it takes four PPI_CLK to write one byte to the FTDI, because the inactive TXE_n (transmit buffer empty) which comes from the FTDI chip after write cycle is about 80ns, therefore some PPI_CLK cycles are insert to ensure the right timing For more detail please refer to the FTD2232 datasheet Figure 8.5 illustrates the timing diagram for this bridge 32 – ANNEXES PPI_FTD I_EN ABLE Start Stop ~60ns PPI_CLK PP_DVALID PPI_DATA[7 0] D0 D1 write D D2 write D D3 write D write D FDTI_WR_n FDTI_DATA[7 0] High-Z D0 D1 20ns 80ns D2 20ns D3 20ns 20ns FTDI_TXE_n Figure 8.5 : The IcyCAM PPI to FTDI FIFO timing diagram 8.4 SD Card direction control in the CPLD The SD Card can be accessed by both the IcyCAM and the STM32 MCU The CPLD provides capability of switching between the IcyCAM SPI and the STM32 SDIO The SPI mode uses unidirectional pins to transfer data and command therefore there is no problem when they connect directly via the CPLD pins On another side, the SDIO interface uses bidirectional pins to transmit or receive command, response and data However, the MAX II CPLD cannot connect directly two bidirectional pins thus the tristate buffers are used to simulate these connections The tristate buffers must be controlled to switch the data and command direction A specific hardware controller is implemented in the CPLD to this task Figure 8.6 shows the block diagram of this controller For the SDIO protocol, please refer to the SD Card specification (including in the CD Card) STM32 SDIO SDIO command parsing and clock counter MUX ICYCAM SPI Figure 8.6: micro SD Card multiplexer There is a start signal indicating the beginning of the command transfer, then the controller will wait for start bit on the command line and count for 48 SDIO clock cycles (each commend is 48bits) and finally switch the direction so that the STM32 SDIO can receive the response from the SD Card This simple counter is illustrated in the follow timing diagram 33 – ANNEXES CMD_STAR T Start Stop 48 SD IO clock cy cles SDIO_C LK SDIO_C MD CMD_DIR Sending Command Receiv ing Response STM32 SD IO to SD Card SD C ard to SDIO Figure 8.7 : SDIO Command direction control timing diagram For data direction, we just only care about write command because the direction is switch to receive response CRC and busy signal when the data are finished transmitting to SD Card In order to know the length of the sent data, this hardware controller will parse the command to get the data length (SET_BLOCK_LENGTH command) so that after the fooling write command (WRITE_BLOCK command) we can know how many clock cycles need for sending data and switch the data pins direction 8.5 Modifications for the IcyCAM Minipack software The CPLD is configured so that most of things are compatible with the software inside the IcyCAM Soc which comes with the MiniPack However, there are some modifications in order to work with then new board These new modifications not affect the default program of the IcyCAM Soc First, one new function misc_onPPI_PSRAM() was added to misc driver so that we can enable PPI to PSRAM controller, the old misc_onPPI() is used to activate the PPI to FTDI FIFO bridge The pseudo GBIO bus address is still 0x04, but the written byte is changed for the new function Then, two new functions were included to write and read data to the STM32 through pseudo bus The address for the STM32 is 0x07 Finally, these functions will call local functions in stub.c source file Therefore new stb functions are also created to the job 34 – ANNEXES 35 ... 1.1 : The new development board with the IcyCAM sensor board Figure 1.2: The IcyCAM Soc Block Diagram Figure 1.3 : IcyCAM Soc Specifications Figure 1.4: The CSEM IcyBoard... Connector IcyCAM JTAG Connector DEV BOARD Figure 2.1: The minimum configuration for IcyCAM development board 2.2 Complete Configuration To expand the applications for the development board, another... 2.2: The complete configuration for IcyCAM development board 2.3 Decision for the development board The final decision for next design steps is the complete solution which consists of another