Quickstart practical guide to simulation synthesis in verilog 2002 3rd ed

VERILOG® QUICKSTART A Practical Guide to Simulation and Synthesis in Verilog Third Edition THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE VERILOG® QUICKSTART A Practical Guide to Simulation and Synthesis in Verilog Third Edition James M Lee Intrinsix Corp KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW eBook ISBN: Print ISBN: 0-306-47680-0 0-7923-7672-2 ©2002 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print ©2002 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's eBookstore at: http://kluweronline.com http://ebooks.kluweronline.com TABLE OF CONTENTS LIST OF FIGURES LIST OF EXAMPLES LIST OF TABLES xiii xv xxi INTRODUCTION Framing Verilog Concepts The Design Abstraction Hierarchy Types of Simulation Types of Languages Simulation versus Programming HDL Learning Paradigms Where To Get More Information Reference Manuals Usenet INTRODUCTION TO THE VERILOG LANGUAGE Identifiers Escaped Identifiers White Space Comments Numbers Text Macros Modules Semicolons Value Set Strengths Numbers, Values, and Unknowns 3 4 5 8 9 10 11 12 12 13 14 14 15 15 16 Verilog Quickstart vi STRUCTURAL MODELING 19 Primitives Ports Ports in Primitives Ports in Modules Instances Hierarchy Hierarchical Names Connect by Name Top-Level Modules You Are Now Ready to Run Your First Simulations Exercise The Hello Simulation Exercise The 8-Bit Hierarchical Adder 19 20 20 21 22 22 24 26 27 28 28 28 STARTING PROCEDURAL MODELING 33 Starting Places for Blocks of Procedural Code The initial Keyword The always Keyword Delays begin-end Blocks fork-join Blocks Summary of Procedural Timing SYSTEM TASKS FOR DISPLAYING RESULTS What is a System Task? $display and Its Relatives Other Commands to Print Results Writing to Files Advanced File IO Functions Setting the Default Radix Special Characters The Current Simulation Time Suppressing Spaces in Your Output Periodic Printouts When to Printout Results A Final System Task Exercise Printing Out Results from Wires Buried in the Hierarchy DATA OBJECTS Data Objects in Verilog Nets Ranges 34 34 34 35 36 39 46 47 47 47 49 51 53 53 54 55 56 58 59 59 59 61 61 61 63 vii Implicit Nets Ports Regs Memories Initial Value of Regs Integers and Reals Time and Realtime Parameters Events Strings Multi-Dimensional Arrays Accessing Words and Bits of Multi-Dimensional Arrays Ports and Regs PROCEDURAL ASSIGNMENTS Procedural Assignments, Ports and Regs Best Practices with Procedural Assignments Procedural Assignment for Combinatorial Logic Procedural Assignment for Sequential Logic Philosophy of Intra-Assignment Delays for Sequential Assignments Conventions Moving Forward OPERATORS Binary Operators Unary Operators Reduction Operators Ternary Operator Equality Operators Concatenations Logical Versus Bit-Wise Operations Operations That Are Not Legal On Reals Working With Strings Combining Operators Sizing Expressions Signed Operations Signed Constants 64 64 65 65 66 66 67 68 68 69 69 70 70 73 77 78 78 78 79 80 81 81 83 84 85 86 89 91 92 93 93 94 94 95 CREATING COMBINATORIAL AND SEQUENTIAL LOGIC 97 Continuous Assignment Event Control The always Block for Combinatorial Logic Event Control Explained 97 101 102 103 viii Verilog Quickstart Summary of Procedural Timing 10 PROCEDURAL FLOW CONTROL The if Statement The case Statement Loops The forever Loop The repeat Loop The while Loop The for Loop Exercise Using Expressions and case 11 TASKS AND FUNCTIONS 106 109 109 110 114 114 115 116 117 118 125 Tasks Automatic Tasks Common Uses for Tasks Functions Functions and Integers Automatic Functions Exercise Functions and Continuous Assignments 125 129 130 132 134 135 136 12 ADVANCED PROCEDURAL MODELING 137 Using The Event Data Type Procedural Continuous Assignments A Reminder About Ports and Regs Modeling with Inout Ports Named Blocks The Disable Statement When is a Simulation Done? 13 USER-DEFINED PRIMITIVES Combinatorial Udps Optimistic Mux Pessimistic Mux The Gritty Details Sequential UDPS UDP Instances The Final Details Exercise Using UDPs 14 PARAMETERIZED MODULES 137 139 144 144 146 146 149 151 152 152 152 153 154 157 157 158 161 ix N-Bit Mux N-Bit Adder N By M Mux N By M Ram Using Parameterized Modules Parameter Passing by Name Parameter Passing by Order Parameter Passing by Named List Values of Parameters in Module Instances 15 STATE MACHINES State Machine Types State Machine Modeling Style State Encoding Methods Default Conditions Implicit State Machines Registered And Unregistered Outputs Factors in Choosing a State Machine Modeling Style 16 MODELING TIPS Modeling Combinatorial Logic Combinatorial Models Using Continuous Assignments Combinatorial Models Using the always Block and regs Combinatorial Models Using Functions Modeling Sequential Logic Sequential Models Using always Sequential Models Using initial Sequential Models Using Tasks Modeling Asynchronous Circuits Modeling a One-Shot Modeling Asynchronous Systems Special-Purpose Models Two-Dimensional Arrays Z-Detectors Multiplier Examples A Proven, Successful Approach to Modeling 17 MODELING STYLE TRADE-OFFS Forces That Influence Modeling Style Evolution of a Model Modeling Style and Synthesis Is It Synthesizable? 162 162 163 164 165 165 165 166 167 169 169 171 179 181 182 183 185 187 187 188 189 192 193 193 193 196 198 198 199 205 205 206 207 217 219 219 220 221 222 Gate-Level Details 341 The drive strength of an instance is specified before the delay and the order of strength declarations may be either strength1 or strength0 first Example A-3 shows declarations including strengths and delays Example A-3 Strength Declarations module strength; nand (strong0, highz1) oc1(z, a, b) oc2(w, d, e); buf (weak1, weak0) #6 wimpo(out, in); myudp (pull0, pull1) #(2:3:4,1:2:3) u1(q, c, d, r, s); endmodule Instances oc1 and oc2 in Example A-3 could be an example of a TTL open collector NAND gate such as the 7401 As you may know, open collector drivers have strong drive low, but no drive high, so they need a pullup resistor to achieve a value of The example buffer shows combining the syntax for specifying strengths with the syntax of specifying a delay The final instance, u1, is an example of a user-defined primitive The user-defined primitive myudp is assumed to be declared elsewhere UDP instances also allow the specification of both strengths and delays Displaying Strengths with %v The format code %v provides more information than %b The output produced by %v is three characters, which describe in more detail the value and strength of a net The first two characters describe the strength as described in Table A-20 The third character describes the value Two new value codes are added to the 0, 1, X, Z set The two new codes are H and L The value H represents either a or a Z The value L represents either a or a Z 342 Verilog Quickstart Nets in Verilog may be one of 120 possible values All of these values can be printed out with %v Some of the values not print out as nicely as the codes from Table A-20 These values print out the strength portion of the value with a two-digit numeric code Values such as 65X and 241 can be printed out by %v If the third character in the value is X, the first number represents the zero strength and the second number represents the one strength If the third character in the value is or 1, then the first two numbers represent a possible range of strength for the value Strength Reduction of Switch Primitives Table A-21 shows the output strength for the switch primitives The nmos, pmos, cmos, tran, tranif0, and tranif1 primitives are considered to be ideal devices since the strength is not reduced through them, except that supply strength is reduced to strong The rnmos, rpmos, rcmos, rtran, rtranif0, and rtranif1 primitives are considered to be resistive devices since the strength is reduced through them All this detail with strengths is important for switch-level modeling, but is not used in behavioral modeling INDEX #include, 264 - negative numbers, 95 - no change, 155 - subtraction, 82 See also Command line option ! !, 83 !=, 87 != =, 87 " and white space, 11 ", 10 # #, 36, 46, 107 $ $, 47 $cleartrace, 309 $display, 47, 234 for debug, 283 specifying format, 49 supressing spaces, 56 $dumpfile, 285 $dumpvars, 285 $fclose, 51 $fdisplay, 52, 258 $ferror, 53 $fflush, 53 $fgetc, 53 $fgets, 53 $finish, 59, 149 $fmonitor, 51 $fopen, 51, 53 Verilog Quickstart 344 $fread, 53 $fscanf, 53 $fseek, 53 $fsscanf, 53 $fstrobe, 258 $ftel, 53 $fwrite, 51 $incpattern, 262 $input, 300 $key, 301 $list, 306 $monitor, 50, 234 $monitoroff, 50 $monitoron, 50 $nokey, 301 $random, 264 example, $readmemb, 251 $readmemh, 251 $realtime, 55, 67, 340 $restart, 309 $rewind, 53 $save, 309 $scope, 303 $settrace, 309 $sformat, 53 $shmopen, 285 $shmprobe, 285 $showscopes, 303 $showvars, 307 $stop, 286 $strobe, 49, 50 $strobe_compare, 262 $swrite, 53 $time, 55, 67, 340 $timeformat, 55 $ungetc, 53 $write, 49 %0h, 54 %0o, 54 %b, 54 %c, 54 %d, 54 %e, 54 %f, 54 %h, 54 %m, 54 %o, 54 %s, 54 %t, 54, 340 %v, 54, 341 & &, 82 &&, 83 * *, 82 * any change, 155 **, 82 ’ , continue, 294 connect by name, 26 hierarchical names, 25 run, 294 / /, 82 /*, 12 //, 12 ? ? % %, 82 %%, 54 %0b, 54 %0d, 54 in testbench, 249 in case statement, 113 in udp table, 153 ?:, 85, 188 Index 345 @ @, 101, 107 memory address, 253 with 137 ^ synthesis, 231 = =, 87 synthesis, 87 = = =, 87 ^ , 82 ` `defaultnettype, 64 `define, 13, 270 `else, 269 `endif, 269 `ifdef, 269 ` include, 264 `timescale, 55, 67, 264, 339 { {}, 90 {{}}, 90 > 107, 137, 267 > =, 87 >>, 82 >>>, 82 0 value, 15 1 value, 15 I I, 82 II, 83 2001 standard, 66, 69, 82, 94, 102, 166, 266 ~, 83 abstraction levels, active low signals, 10 adder, 191 schematic, 28 simulation, 28 address in file, 253 alarm, 200 always, 34, 46, 107 combinatorial for synthesis, 190 explained, 104 sensitivity list, 102 sequential, 193 synthesis, 193 synthesizable combinatorial logic, 102 zero delay, 149 A + + addition, 82 ++, 117 +define, 270 +incdir, 265 <