Bài giảng Computer Organization and Architecture: Chapter 3 - System Buses tập trung trình bày Hardwired systems are inflexible; General purpose hardware can do different tasks, given correct control signals; Instead of re-wiring, supply a new set of control signals.
Trang 1William Stallings
Computer Organization and Architecture
6th Edition
Chapter 3
System Buses
Trang 4Function of Control Unit
Trang 6Computer Components:Top Level View
Trang 7Instruction Cycle
• Two steps:
—Fetch
—Execute
Trang 10Example of Program Execution
Trang 11Instruction Cycle - State Diagram
Trang 13Program Flow Control
Trang 15Transfer of Control via Interrupts
Trang 16Instruction Cycle with Interrupts
Trang 17Program TimingShort I/O Wait
Trang 18Program TimingLong I/O Wait
Trang 19Instruction Cycle (with Interrupts) - State Diagram
Trang 21Multiple Interrupts - Sequential
Trang 22Multiple Interrupts – Nested
Trang 23Time Sequence of Multiple Interrupts
Trang 25Computer Modules
Trang 35Bus Interconnection Scheme
Trang 36Big and Yellow?
Trang 37Single Bus Problems
Trang 38Traditional (ISA)(with cache)
Trang 39High Performance Bus
Trang 43Distributed Arbitration
• Each module may claim the bus
• Control logic on all modules
Trang 45Synchronous Timing Diagram
Trang 46Asynchronous Timing – Read Diagram
Trang 47Asynchronous Timing – Write Diagram
Trang 49PCI Bus Lines (required)
Trang 50PCI Bus Lines (Optional)
Trang 52PCI Read Timing Diagram
Trang 53PCI Bus Arbitration