VIETNAM NATIONAL UNIVERSITY - HO CHI MINH CITYUNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING NGUYEN VAN DUNG THESIS NGHIEN CUU, HIEN THUC VA TONG HOP ARM CORTEX-M0
The Synthesis 0T
Figure 3-2 shows a basic synthesis flow [6] The details of the steps will be explained from 3.2 to 3.9 and chapter 4.
Design rule constraints set_max_trainsition set_max_fanout set_max_capacitance Design optimization constraints create_clock set_clock_latency set_clock_uncertainty set_input_delay set_output_delay set_max_area
Library objects link_libraries target_library symbol_library Select compile strategy
Read Design top down bottom up flat Design hierarchical Design analyze read_file
Synthesize and optimize the design Define design environment, b SG compile_ultra set_operating_conditions set_drive set_load set_fanout_load set_wire_load_model
Analyze and resolve design problems check_design report_area report_constraint report_timing
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The input design files for Design Compiler are written using a hardware description language (HDL) such as Verilog or VHDL It is also important to consider HDL coding strategies HDL coding is the foundation for synthesis because it implies the initial structure of the design When preparing the HDL code, you need to consider design data management, design partitioning, and your HDL coding style.
OUTi); module MYREG (IN1, IN2, IN3, IN4, SEL, CLK1, input IN1, IN2, IN3, IN4, SEL, CLK1; output OUT1; reg OUT1; always 6 (posedge CLKI)| begin if (SEL) OUT1 rw rw usr99 COS 3756037 May
UIT_2021/Project/work/Synthesis/22.run_06052021 midterm/output > LL
22:38 11:96 22:21 fpga_top.ddc fpga_ top sdc fpga_top.v lanaana
- Reports: Where to store parameters for post synthesis analysis.
Scripts report Purpose report_name_rules verilog
This command reports the values of a set of name rules report_net Reports net information for the design of the current instance or for the current design report_cell Displays information about cells in the current instance or current design. report_qgor Displays QoR information and statistics for the current design. report_area Lists the area statistics for the current instance or the current design. report_design Lists information about the attributes of the design. report_port Displays information about ports in the design of the current instance or the current design. report_clock Displays all clock-related information for a design. report_timing Displays timing information about a design. report_hierarchy Displays the indented reference hierarchy of the current instance or the current design. report_constraint Displays the following information for the constraints on the current design:
- Logs file: Directory where the jobs performed by the DC tool are stored The log displays the output, such as the commands that are processed and the error messages for each Design Compiler run on the screen for quick viewing and debugging.
Specify libraries . -cc 5c c2 tt SH 212101112 re 33 3.5 Read Design Ă St HH 22 HH ườn 36 3.5.1 Running the analyze and elaborate Comimmands -‹ ô+ 36 3.5.2 Issue step read design chen HH niên 37 3.6 Define design enVirORIN€II -¿- + + +52 S*+E+E£E+EvEtEkrErkererkrkrkrkrrereree 38 3.6.1 Operating ConditiOns -c+c+cssketeterererrkerrrerrree 39 3.6.2 Drive Characteristics for Input POFS - es 55+ 5++x+<cxcrcre 40 3.6.3 Defining Loads on Output POFS - - ô¿c5 SekeEtrekekekerree 4I 3.6.4 Defining Fanout Loads on Output POrts : -555555+ 42 3.6.5 Wire Load Model for Design
Specify the link, target, symbol, synthetic, and physical libraries Design Compiler uses logic, symbol, and DesignWare libraries to implement design functions and display synthesis results graphically The logic libraries that Design Compiler maps to during optimization are called target library definition libraries target design function target libraries Target libraries contain the cells used to generate the netlist and definitions for the design’s operating conditions The target libraries are the subset of the link libraries that are used to compile or translate a design Link libraries define timing values, the delay models that are used to calculate timing values and path delays.
Target Libraries: Design Compiler selects functionally correct gates from the target libraries to build a circuit during mapping It also calculates the timing of the circuit by using the vendor-supplied timing data for these gates To specify the target libraries, use the target_library variable You should specify only the standard cell libraries that you want Design Compiler to use for mapping the standard cells in your design, such as combinational logic and registers.
Link Libraries: For a design to be complete, all cell instances in the design must be linked to the library components and designs that are referenced This process is called linking the design or resolving reference solving design linking references To resolve references, Design Compiler uses the link libraries set by the following variables and attribute: The link_library application variable lists the libraries and design files that Design Compiler uses to resolve references.
Symbol Libraries: Symbol libraries defined libraries symbol contain definitions of the graphic symbols that represent library cells in design schematics Semiconductor vendors maintain and distribute the symbol libraries.
Table 3-4 lists the variables that control library reading for each library type and the typical file name.
Library type Variable Default File Extension
Target library Target_library {your_library.db} db
Link library Link_library {* your_library.db} db
Symbol library | Symbol_library | {your_library.sdb} sdb
Technology file | Tech_file {your_library.tf } tf
TLUPlus file TLUplus_file {your_library.tluplus } tluplus
Map file Map_file {your_library.map} -map ii TER
User-defined variables for logical library setup in dc setup.tcL
OLE 1.3L € €.101418t40040114441102141404001404441400001040400140001141819140202 set ADDITIONAL SEARCH PATH "/hone/usr99/KLTN UIT 2021/Project/work/Synthesis/libs/libss \.
„/RTL code \ /misc/too\/SYN0PSYS/DC/N-2617.69-SP5-2/Libraries/syn_\
/misc/tool/SYNOPSYS/DC/N-2017,09-SP5-2/minpower/syn \ /misc/tool/SYNOPSYS/0C/N-2017,09-SP5-2/dw/syn_ver \ /misc/tool/SYNOPSYS/DC/N-2017,09-SP5-2/dw/sim ver \
;# Directories containing logic libraries, 3# logic design and script files. ket TARGET LIBRARY FILES "saed32hvt_ss0p95v125c.db"
LINK_LIBRARY FILES "saed32hvt_ss0p95v125c.db saed32Lvt_ss0p95v125c.db saed32rvt_ss0p95v125c db"
Eer SYMBOL_LIBRARY FILES “sc.sdb generic sdb" ¿# Symbol library file
Figure 3-14 Specifying logic libraries aAEREEERESRERRBEREPRESRERATOREERRABERNERESEIEERNEREERRER TERT TREE INTRA RATEREERROTEED
User-defined variables for physical library setup in dc setup tcl
HI290)003)034041031034444000021404400114440040004246 et MW_DESIGN LIB fpga_top i# User-defined Milkyway design Library name et MW_REFERENCE LIB DIRS /hone/usr99/KLTN_UTT_ 2621/Project/work/Synthes‡s/Libs/Libss
;# Milkyway physical cell Libraries et TECH FILE ‘/nome/usr99/KLTN_UIT_2021/Project/work/Synthesis/1ibs/libss/saed32nm_1p9m_mw.tf i# Milkyway technology file et TLUPLUS_MAX_FILE /home/usr99/KLTN_UIT_2021/Project/work/Synthesis/Libs/Libss/saed32nm_1p9m_Cmax.tluplus
;# Max TLUPLus file et MAP_FILE /home/usr99/KLTN_UIT_2621/Project/work/Synthesis/Libs/libss/saed32nm_1p9m_gdsout.map
Figure 3-15 Specifying physical libraries Figure 3-16 shows a dc_setup.tcl This file is automatically executed first upon tool startup.
BERAHERAAEBAAHAE AAA E AAR EAA RAR AREA AAR HA RAHA HAHAHAHAHAHA AR ER RE AER E EE ES set app var search path “SADDITIONAL SEARCH PATH" set app var target library “STARGET LIBRARY FILES” set app var symbol library "$SYMBOL_LIBRARY FILES" set app var synthetic library "dw foundation.sLdb" set app var Link tibrary "* SLINK LIBRARY FILES $synthetic library"
HHPHHHAHAHAHAHHHHHHHHHKHHHRAHRHRH RH HHRMA HRH SHAH HaH AHHH HHH Hes e se Hse Hees set_app_var mw_reference library $MW_REFERENCE LIB DIRS set app var mw_design library $MW DESIGN LIB
# Only create new Milkyway design library if it doesn't already exist if {!{file isdirectory $smw design library ]} If create mw Lib -technology sTECH FILE \
-mw_reference library smw_reference library \
$mw_design_ library open_mw lib $mw design library set tLu pLus files -max ttuptus $TLUPLUS MAX FILE \
-tech2itf map $#AP FILE
Figure 3-16 Setup libraries for DC tool
Design Compiler can read both RTL designs and gate-level netlists Design Compiler uses HDL Compiler to read Verilog and VHDL RTL designs and Verilog.
The logic function must be descriptive in type so that EDA tools can be read and analyzed Some standard types. e RTL: Programming language base description Description both connections between modules/element or function -> Friendly to verification tools. e Gate_Level_Netlist : Design language base description (friendly with
Physical EDA tool) Descript connection between modules/elements only.
No description about function -> Need read additional netlist of function in case of verification tool.
3.5.1 Running the analyze and elaborate Commands
Analyzes the specified HDL source files and stores the resulting templates into the specified library in a format ready to specialize and elaborate to form linkable cells of a full design.
The analyze command performs the following tasks: e Reads an HDL source file ¢ Checks for errors without building generic logic for the design e Creates HDL library objects in an HDL-independent intermediate format ¢ Stores the intermediate files in a location you define
If the analyze command reports errors, fix them in the HDL source file and then run the analyze command again After a design is analyzed, you must reanalyze it only when you change it.
The elaborate command builds a design from its intermediate representation using the specified parameters.
The elaborate command performs the following tasks: e Translates the design into a technology-independent design
(GTECH) from the e intermediate files produced during analysis e Allows changing of parameter values defined in the source code e Allows VHDL architecture selection e Replaces the HDL arithmetic operators in the code with DesignWare components e Automatically executes the link command, which resolves design references
To use this method, analyze the top-level design and all subdesigns in bottom-up order and then elaborate the top-level design and any subdesigns that require parameters to be assigned or overwritten: dc_shell> analyze -format verilog .v dc_shell> elaborate fpga_top
3.5.2 Issue step read design Issue : Can't synthesize input RTL code with GTECH library
- The macros have not been defined (invalid macro) => Tool cannot read the design That is, some variables in the module do not match the value in other blocks.
- Lots of syntax errors because the previous designer - Vinh Khang, does not use all design functions, so he doesn’t care to define for not-used functions in each verilog file clearly This causes errors in the ports, pins, module names, namely the blocks cortexm0_ designstart ver 1 (He only uses ver2), cxapbasyncbridge, cmsdk_ahb_busmatrix.
- Ihave reviewed the block diagram from the old project + report thesis to filter out the files, the blocks that Mr Khang used That means the total number of files he used is 109/305 The not-used files that are removed can cause syntax errors and unmatched function blocks.
- The error files and error macros have not been defined (there are three files user_partition.v, cmsdk_mcu_defs.v and scc.v) I have fixed this by finding and redefining these values in function blocks with the correct connection.
Result : Successfully Mapping RTL code with GTECH library current_design fpga top
Logical Hierarchy Current design is 'fpga_top'. wo {fpga_top}
[BH] u fpga sys bus mux Linking design 'fpga top"
[RE] u spi2apb3 Using the following designs and libraries
[Fu fpga mt sync se,
= [A] _u fpga apb subsystem * (109 designs) /hone/usr99/KLTN_UIT_2021/Proj
TH) uscc saed32hvt_ss0p95v125c (library) /home/usr99/KLTN UIT 2021/
FT 0 TS REi is saed32lvt_ss0p95v125c (library) /hone/usr99/KLTN UIT 2021/
WpiEroo saed32rvt_ss0p95v125c (library) /hone/usr99/KLTN UIT 2021/ u i2s_m_overrun_sync A visit Figure 3-17 The announcement has read design u_syne_codec.tst usyne_bten JSpga_top u_ fifo ui2s_async_n_dest 12s asy
U i2 a9y u_tx fifo u-apb if u_fpga rst sync 1 u_fpga_io_regs u_ahb_to_apb ®[H] u_ahb.gpio.3
] u ahb gpio 2 u_emsdk_ahb_to_extmem16 u_ahb_sdram_3 u_ahb sdram_2
[5] u_ahb defaut siave_0 u_ahb_slave_mux_sys_bus u_ahb_zbtram_32_ad u_ahb_blockram_32 u_cmsdlk mcu_system. j m mỊ m Em]
[TH] u fpga 100hz gen [RH] ufpga rtsync 3 TH) ufpga rstsync 2 TR] ufpga rstsync 1 m m ú_fpga rst sync_0
Figure 3-19 Schematic fpga_top by DC tool