1.3 HIGH FREQUENCY ULTRASOUND IMAGING: ARRAYS 8 2.2.4 FRACTIONAL-DELAY INTERPOLATION BEAMFORMING 27 Chapter 3: DIGITAL BEAMFORMING IMPLEMENTATION 34 3.1 FIELD PROGRAMMABLE GATE ARRAY FP
SYSTEM HARDWARE 56
ANALOG FRONT-END CIRCUIT AND TRANSMIT BEAMFORMER 57
The analog circuit includes the pulser, receiver, variable gain amplifiers, TGC, and transmit beamformer The pulser is triggered by a 5-volt rising-edge signal The width of the signal is programmable with a minimum of 10 ns and an increment of 2.5 ns based on the DS1040 (Dallas Semiconductor.) one-shot pulser generator This signal triggers the pulser to generate a negative 66V, 10 ns duration impulse to excite the transducer A synchronized T/R switch works as a voltage limiter to avoid high voltage impulses into the receiver Once the echo signals are received, the preamplifier (MAX4107, Dallas Semiconductor), which is placed directly after the T/R circuit, provides an ultra-low-noise amplification, a gain of 10 dB and a bandwidth of 200 MHz Next, two-stage amplification including a TGC amplifier and a variable gain amplifier provides another 30 to 70 dB gain to the echoes Two AD603s (Analog Devices Inc.) are used as the TGC and the gain- adjustable amplifier A 4-tap Butterworth passive band-pass LC filter with a –3 dB bandwidth of 15 ~ 75 MHz is chained directly after the second stage AD603 to remove noise outside the transducer bandwidth and the noise from the amplifier Finally, an AD8009 (Analog Devices Inc.) is used to provide another 10 dB gain to compensate the loss through passive LC filter
The transmit focusing circuit provides six trigger signals, corresponding to each annuli, with a precalculated delay These relatively delayed signals trigger to generate a pulse to each transducer element so that the transmit focusing is implemented A Scenix microprocessor (SDX52, Configurable Communications Controllers) that has a pipeline structure working at 100 MHz is the core part It controls six programmable delay chips (PDU13F-2, Data Delay Device, Inc.), which provide 2 ns minimum delay Each delay is achieved in two steps The delays that are the integer multiples of 10 ns are fulfilled by software, and the delays less than
10 ns are implemented by the delay chips.
DIGITAL BEAMFORMER CIRCUIT 59
In this effort, the time-domain beamformer is implemented using the delay- sum architecture, and it requires sampling the echo at a rate much higher than the Nyquist rate in order to achieve the smallest time quantization interval and guaranteeing the accuracy of the time-delay Coarse delay is determined by the sampling period, and the fine delay needs to be generated The fine delay can be realized either using tapped delay-lines (Odell and Meador, 1991) or a shift register and RAM buffers (Peterson and Kino, 1984) The drawback of these methods is that the precision of the delay depends on the sampling frequency One solution is using interpolation Interpolation increases the resolution of the signals while allowing the signals to be sampled at a lower frequency
The photograph of completed electronic boards is shown in Figure 4.5 The PCB boards have four layers with two signal layers on the surfaces and two inner layers for ground and power planes, respectively On the beamformer board, the A/D converters are carefully laid around the XCV300E chip to avoid unexpected signal delays Pairs of 0.1 àF, and 1 nF capacitors and chokes are used for decoupling at each important power pin
Figure 4.5 The photograph of the assembled transceiver and beamformer board.
EXPERIMENTAL RESULTS 60
Cross-sectional images were obtained from a wire-target phantom The phantom with 5 wires was placed in the axial direction and the wires were made of
20 àm diameter tungsten wires Five wires were arranged diagonally with equal distance in the axial (1.55 mm) and lateral (0.65 mm) directions The pulse-echo image was acquired as the annular array scans across the wire phantom in degassed water By using the system, two annular arrays have been used to test the performance The first annular array is the 6-ring PbTiO3 array (Snook et al, 2001) and the second is the 8-ring P(VDF-TrFE) array (Gottlieb, 2005)
Figure 4.6(A) compares the wire phantom image obtained with a single element (right) to that with the annular array (left, PbTiO3) Figure 4.6(B) compares the wire phantom image obtained with a single element to that with the annular array (P(VDF-TrFE), left) Both images are displayed with a dynamic range of 30 dB The wire phantom image from the single element transducer (Figure 4.6(A), left) was obtained by placing the phantom at the focal point when only one channel of this system was used The single element transducer is a 45 MHz, lens-focused LiNbO3 transducer with an F# of 2.34 (Cannata et al., 2003) One of the advantages of the annular array over single element transducers is that it maintains an almost uniform lateral resolution because of the multi-focal zone formed by dynamic focusing This can be easily demonstrated in Figure 4.6(A) The wire phantom image from the single element transducer shows significantly lower resolution at a depth of 5.5 mm, which gradually converges at the focal point of 8.7 mm, and then become wider after focal point In comparison, the phantom image from the annular array shows improved lateral resolution throughout the entire depth, especially in the near field
The ex vivo rabbit eye images were acquired by placing the eye in the saline tank The array transducer was then scanned across the eyeball Figure 4.7 shows the eye tissue images The anterior region, consisting of structures such as cornea and lens, is clearly defined.
DEVELOPMENT OF A HIGH FREQUENCY ULTRASOUND DIGITAL BEAMFORMER WITH LINEAR ARRAY TRANSDUCERS 67
INTRODUCTION 67
As discussed in Chapter 1, the applications of the high frequency (> 20MHz) ultrasonic imaging in ophthalmology, dermatology, and small animal imaging exclusively employed only single element transducers Compared to single element transducers, linear arrays allow for dynamic focusing that improves the lateral resolution throughout the depth of view and electronic scanning that provides a high frame rate Furthermore, the hand-held operation and lack of scanning motion of linear array imaging systems is more clinically convenient, safer and more reliable However, linear array design requires an element pitch, defined as the distance between the centers of two adjacent elements, to be less than one ultrasound wavelength in order to fully suppress grating lobes (Shung et al., 1992) This brings great difficulties to the fabrication of high frequency linear array transducers when the ultrasound wavelength is only approximately 50 àm at a frequency of 30 MHz for example Moreover, the relatively small elements in a linear array have higher electrical impedance resulting in poor sensitivity Lastly, the beamforming electronics are not yet commercially available due to cost and complexity (Ritter et al., 2002; Cannata et al., 2006) All of these difficulties have prevented the widespread fabrication and application of the high frequency linear arrays Nevertherless, Ritter (2002) developed the first 30 MHz, 48-element linear array transducer with a 100 àm pitch using piezo-composite material Cannata (2006) reported the fabrication of a 35 MHz linear array with a 50 àm pitch, which is the highest frequency medical imaging linear array fabricated to date For consistency in the following text, the two linear arrays used with this digital beamformer are referred to by the center frequencies of 30 MHz and 35 MHz More details about fabrication and evaluation of the 30 MHz and 35 MHz linear arrays can be found in (Ritter et al., 2002; Cannata et al., 2006)
Several imaging systems and beamformers associated with linear arrays at lower frequency (< 20 MHz) were reported (Payne et al., 1989; O’Donnell et al., 1990; Payne et al., 1994; Jensen et al., 1999; O’Donnell et al., 1999; Schulze-Clewing et al., 2000) A real-time phased array imaging system using digital base- band interpolation, constructed on a custom very large-scale integrated circuit (VLSI), was developed for a 64 element, 3.33 MHz, 40% bandwidth array (O’Donnell et al., 1990) In order to minimize the length of electrical connection between the transducer elements and the transmit/receive circuits, the transmit/receive circuitry has been integrate with a up to 64 elements, 15 MHz transducer (Payne et al., 1994) An experimental ultrasound system, capable of exciting 128 element transducer and receiving 64 elements simultaneously, was designed for 1-10 MHz arrays (Jensen et al., 1999) With the ultrasound changing from the low frequency to very high frequency (> 20 MHz), it will be more challenging for systems to provide reliable operations The system prototype for linear array at center frequency of around 20-25 MHz was reported and only five elements were used in a group to produce the focused beam (Payne et al., 1989) The
20 MHz, 64 element circular array with the intravascular application was developed with integrated front-end circuitry (O’Donnell et al., 1999; Schulze-Clewing et al., 2000) For these linear arrays, most images were obtained using synthetic aperture approach (Ritter et al., 2002; Payne et al., 1989; O’Donnell et al., 1999; Schulze- Clewing et al., 2000) In synthetic aperture method, only limited numbers of elements are activated at a time, which causes elevated sidelobe, grating lobe and motion artifacts Stitt (2002) developed a sixteen-channel analog beamformer for the linear array fabricated by Ritter et al (2002) The architecture of this beamformer was bulky It has to be miniaturized and the frame rate increased to have any practical application
Although digital beamformer methods have been successfully used in conventional array imaging, there are still some practical challenges special for high frequency ultrasonic transducer arrays: more sufficient sampling rate is used to obtain the fine delay, and high bit A/D converter is needed to capture all of the information in the array bandwidth (Peterson and Kino 1984; Steinberg, 1992) The sampling rate should be at least 4-10 times higher than the center frequency of the arrays so that the signals are greatly over-sampled to obtain the accurate time delays (O’Donnell et al., 1990; Peterson and Kino 1984; Steinberg, 1992) In this study, the linear array transducer has a center frequency of 30-35 MHz, A/D converters should work at least 120-350 MHz in order to satisfy this criteria This, however, raises the cost and system complexity Therefore, the tradeoff is using sampling rate of 100 MHz in this study, and the time between two samples is 10 ns Based on the 100 MHz sampled data, the fractional-delay interpolation is used to generate the fine delay as small as 1 ns inside the beamformer Furthermore, there are several hurdles that have to be overcome in the development of a high frequency imaging system (1) High-speed and wide bandwidth electrical components are necessary for high frequency imaging (2) Higher computation power and large data storage capability are desired for a real-time beamformer (3) Noise tolerance is stricter for high frequency arrays because of the higher attenuation
A sixteen-channel Field Programmable Gate Array (FPGA) based real-time digital beamformer has been developed The digital beamfoming is implemented inside the FPGA for the digitized echoes from 16 adjacent transducer elements The hardware architecture of the design provides great flexibility for beamforming, such as dynamic receive focusing and receive apodization Due to the high work speed (maximum speed is 400 MHz for the Xilinx FPGA XC2VP20), reprogrammability, and flexibility, FPGAs are an ideal platform for developing the beamformer, and have been successfully applied to digital beamfomers, including a system for the 5 MHz center frequency linear array (Tomov and Jensen, 2001) and a system for the
50 MHz center frequency annular array transducer (Cao and Shung 2002; Cao at al., 2003) For a high performance imaging system both dynamic focusing in transmit and receive at all location is necessary, but considering the complexity of circuit design and frame rate (real-time), the first generation of design is implemented with only dynamic focusing in reception
This chapter describes the design of a real-time ultrasonic imaging system using linear array specifically for research purpose The FPGA shows the flexibility in digital beamformering The images from wire target and rabbit eye are shown, which demonstrates the feasibility of using high frequency linear array to image the microscopic structure.
LINEAR ARRAY FABRICATION AND DESIGN CONSIDERATIONS 71
The detailed fabrication process of the two linear arrays was given (Ritter et al., 2002; Cannata et al., 2006) The parameters of the linear arrays in this study are shown in Table 5.1
For the design of a digital beamformer for linear arrays, parameters such as aperture size, delay and delay implementation must be considered and evaluated
Because beam patterns and lateral resolution are affected by the aperture size, the beam patterns are used to compare and evaluate the effect of the aperture size chosen for beamformer The beam pattern of the linear array is simulated using Field II
(Jensen, 1996) The models are implemented with parameters such as the array center frequency, bandwidth, element width, kerf width and transmit focal distance specified in Table 5.1
Table 5.1 Parameters of the Linear Array Used in this Study
Element dimensions 1.5 mm x 82 àm 3 mm x 36 àm
The beam pattern on the azimuthal plane can be varied by modifying the activated number of array elements The –6 dB contours of the simulated beam patterns on the azimuthal plane and the corresponding –6 dB 1-D intensity profiles at the focal point using different number of active elements for the 30 MHz linear array (Table 5.1) are plotted in Figure 5.1 It is readily apparent that activating more elements, thus yielding a larger aperture size, would result in a better lateral resolution When the number of activated elements is less than 8, there is significant divergence of the –6 dB contour, which results in a wider beam width As more elements are activated, a tighter focus results The –6 dB contour of the simulated beam pattern on the azimuthal plane and the corresponding –6 dB 1-D intensity profile at focal point using different number of active elements for the 35 MHz linear array (Table 5.1) are plotted in Figure 5.2 For this 35 MHz linear array, the depth of focus does not vary as much as the 30 MHz array with the aperture size due to its smaller pitch The lateral resolution improves with the increased aperture size
The major differences between these two linear arrays are the pitch and focal distance The #f , which is define as the ratio of focal length to the aperture size are determined by the pitch size and focal distance The lateral resolution of a linear array on the azimuthal plane is given by:
= × where N is the active number of elements to achieve the beamformer, PS is the pitch, and FD is the focal distance The array in Table 5.1 has a pitch (PS) of 100 àm with 6.4 mm focal distance (FD) while the second one has the pitch of 50 àm with 9.5 mm focal distance The further comparison of the calculated results between arrays is carried out For example, if the 16 elements are used to generate a beam, the first array transducer has a R lateral 50 204 àm
6 = × while the second array has a R lateral 45 534.4 àm
9 = × , which are similar to the results from the simulation which shows 225 àm and 590 àm in axial and lateral direction, respectively This explains why the second array has lower lateral resolution although it is at a higher frequency unless a bigger aperture size is adopted
The comparison of the –6 dB lateral beam width and the depth of focus with variable active elements for 30 MHz linear array and 35 MHz array between the simulation and theoretical value is shown in Table 5.2 and Table 5.3, respectively
This beamformer presented here was initially designed to image with a 30 MHz, 48-element linear array with 16 electronic channels to activate 16 simultaneously to form one beam It was arrived at primarily from a consideration of cost and complexity High sampling rate analog to digital converters are extremely expansive Another reason for adopting such a design is that the major function of this imaging system is to test the performance of the arrays under development Therefore flexibility is an important criterion
In certain cases, the weighting function (apodization) is employed in beamforming The main reason for doing this is to decrease the sidelobe level Functions generally used for apodization are Hamming, Hanning, Gaussian, Blackman, and Chebeycheff windows (Kino, 1987) Using all these apodization functions, the comparison of the –6 dB contour of simulation beam pattern is show in Figure 5.3 The corresponding lateral intensity profile with above apodization functions at focal point is also shown in Figure 5.4 In order to further evaluate the affect of the apodization, the –6 dB beam width along the axial direction is measured and shown in Figure 5.5 The –6 dB width of one-way intensity along the axial direction is smallest when no apodization function is used However, the drawbacks of using apodization are that the main lobe becomes wider with consequent reduction in axial resolution and the amplitude is reduced compared with original one
Distance (mm) along beam axis
Distance(mm) perpendicular to beam axis
Figure 5.1 The –6 dB contour of simulation beam pattern (Top) and lateral intensity profile at focal point (Bottom) of linear array transducer (30 MHz, 100 àm pitch) in lateral-depth (XZ) plane with different active elements
Distance (mm) along beam axis
Distance(mm) perpendicular to beam axis
Figure 5.2 The –6 dB contour of simulation beam pattern (Top) and lateral intensity profile at focal point (Bottom) of linear array transducer (35 MHz, 50 àm pitch) in lateral-depth (XZ) plane with different active elements
Table 5.2 Comparison of the –6 dB lateral beam width and the depth of focus with variable active elements for linear array (30 MHz) between simulation and theoretical calculation
Table 5.3 Comparison of the –6 dB lateral beam width and the depth of focus with variable active elements for linear array (35 MHz) between simulation and theoretical calculation
Following the general delay calculation described in Chapter 2, for the linear array, we have:
Therefore the delay for ith element is
2τ τ i =k where a 0 is the pitch, a i is the distance for the kth element to the center element, d is the distance from point source to the surface of transducer, c is the speed of the sound, and τ i is thus the delay
Figure 5.3 The comparison of the –6 dB contour of simulation beam pattern using apodization functions
Figure 5.4 The comparison of lateral intensity profile using apodization functions at focal point
Figure 5.5 The comparison of –6 dB width using different apodization functions.
SYSTEM HARDWARE 82
The imaging system consists of 1) A PC computer for displaying the image 2) A 16-channel FPGA-based beamformer 3) A 16-channel analog variable gain amplifer (VGA) and time gain compensation (TGC) amplifiers 4) A 16-channel transmit focusing control 5) A 64-channel transceiver 6) Either a 30 MHz or a 35 MHz linear array The main concern of the system design is to digitize the 16- channel RF data, and process the acquired data fast enough for real-time imaging
As shown in the system diagram (Figure 5.6), the PC computer serves as the user interface Upon each frame trigger signal given by the PC, the microprocessor inside USB (CY7C68013, Cypress, Inc.) sequentially sends out trigger signals to other blocks The line trigger is first delivered to the 16-channel transmit focusing control, which consists of three SX52BD (Ubicom Inc.) high-speed microcontrollers The microcontrollers are used as the central timing controller for transmit focusing They send the trigger signals to the pulsers, and control signals to the demultiplexers which interfaces to the transducer elements and the 16-channel transceiver Coaxial cables are used to connect transceiver with linear array The amplified echoes are first digitized using sixteen 8-bit analog-to-digital converters (AD9054A, Analog Devices, Inc.) at 100 MHz and then aligned by an FPGA (XC2VP20-6FF896C, Xilinx, Inc.) based beamformer The delay of the beam data is implemented in two steps: coarse delays, which are integer multiples of the clock period, are obtained by the coarse delay unit and finer delays less than one clock period are processed by fractional delay filters The beamformed data is then transferred to a PC computer through the USB port for real-time display (30 frames per second) A graphic user interface (GUI) software is developed using Visual C++ (Microsoft Corp.) for real time display
Figure 5.6 Block diagram of the overall imaging system
FPGA- based digital beamfor ming
5.3.1 ANALOG FRONT CIRCUIT AND TRANSMIT BEAMFORMER
The analog frond-end circuit consists of three boards: a 64-channel transceiver board, a 16-channel three-stage amplification board and a transmit focus circuit board
The transceiver board is triggered by sixteen 5-volt rising-edge signals The signals pass through sixteen 1-of-4 demultiplxers (74AC139, National Semiconductor Inc.) so that 16 adjacent elements are chosen Triggered by these rising-edge signals, the pulser circuit generates a -66 volt impulse of 10 ns duration for each chosen element This pulser design can support broadband transducer excitation up to 88MHz, –6dB bandwidth A transmiter/receiver (T/R) switch is then used as a voltage limiter to avoid high voltage impulse into the receiver Immediately following T/R switch, 16 4-to-1 multiplexers (AD8184, Analog Devices Inc.) are used to select the corresponding activated element out of 64-element The 16 preamplifiers (MAX4107, Dallas Semiconductor), an ultra low-noise Op Amp with a gain of 10 dB and a bandwidth of 200MHz, are employed to amplify signals The demultiplexers and multiplexers are controlled by the same control signals to keep the synchronization
A three-stage, 16-channel amplification board, including one fixed gain amplifier, a TGC amplifier and a variable gain amplifier, provides another 30 to 70 dB gain to the echoes Two AD603 are involved in the TGC and the gain-adjustable amplifier A passive band-pass LC filter with the –3dB cutoff frequency from 10 MHz to 50 MHz is used directly after second stage AD603 to remove the noise outside the transducer bandwidth and the noise from amplifier An AD8009 (Analog Devices Inc.) is used to provide more gain of 10 dB to compensate the 6dB insertion loss through the passive LC filter
Figure 5.7 Excitation pulse and its spectrum
A 4-tap Butterworth band-pass filter with a bandwidth of 12 ~ 65 MHz is chained in the signal path to remove the noise LC Band pass filters are usually LC filters containing resonator combinations of inductance and capacitance which are designed mathematically to respond to design frequencies while rejecting all other out of band frequencies Due to the complementary nature of capacitor (C) and inductor (L), LC filter provides good filtering action over a wide range of currents (Hagen, 1996) Figure 5.8 shows the schematic of the LC filter used in this design Both the FFT of real echoes from on element of linear array and the FFT of Butterworth filter are given in Figure 5.9 Generally, in order to make the bandwidth of filter cove the bandwidth of the echoes, the bandwidth of filters is wider considering the center frequency down shift due to the tissue attenuation as discussed in Chapter 1
Figure 5.8 Schematic of the 4 th Butterworth filter
Figure 5.9 Spectrum of the filter (solid line) and the spectrum of the signal
As shown in Figure 5.10, each multiplexer switches among four transducer elements Therefore, each scan line presents a different order of 16 elements, and the
16 channel RF data cannot be connected directly to digital beamformer For example, the first line has the order of E1, E2, … E16, and the second line become E17,E2,…E16 before feeding to the beamformer Because the beamformer is designed with the delays only based on the geometrical structure for each channel (Fig 3), the second line must be rearranged as the order of E2E3…E16E17 In this design, a high speed 16 x 16 video crosspoint switch (AD8114, Analog Devices Inc.) is used to rearrange the order of the analog outputs
The transmit focusing circuit board provides sixteen trigger signals with a relative delay resolution of 2 ns between pulsers In order to control the transceiver circuit and amplification circuit, two requirements are considered: 1) High speed for real time imaging purpose 2) Large amount of control signals (up to 120 control signals) Scenix microprocessors (SDX52, Ubicom, Inc.) using pipeline structure working at 100MHz has one instruct cycle of 10 ns and the 40 flexible I/O pins Therefore, 3 microprocessors are employed The first microprocessor generates the control signal to demultiplexer and multiplxer The second microprocessor sends out
16 triggers to sixteen programmable delay chips (PDU13F-2, Data Delay Device, Inc.) Each delay is achieved in two steps The delay amount that is the integer multiples of 10 ns is fulfilled by software and the delays less then 10 ns is implemented by the delay chips The third microprocessor controls 16 x 16 video crosspoint switch Immediately after the first and the third microcontroller send out the signals, they will trigger the “ready” signal to second controller The second microcontroller, in turn, triggers pulser circuitry to work
The pulses are transferred using shielded, balanced cable A power supply board was also build to provide the power consumption at the reasonable level The board draws its power from dedicated linear power supplier
Figure 5.10 Block diagram of the crosspoint switch
The geometric differences for different transducer elements are needed to be removed so that the final beams are formed By following this way, the echoes for
Element number the desired locations are enhanced and the summation of all the elements is maximized In this study, the time-domain beamformer is used with the delay-sum architecture In order to guarantee the precision of the beamformer in time domain, ADCs with much higher sampling rate are needed to achieve the smallest time quantization interval However, considering working limits of FPGAs and FIFOs, the ADCs cannot be too high for the high frequency arrays in order to implement the real time imaging In this system design, the 100 MHz ADCs are employed Therefore, the time interval (10 ns) between two sampling data is too coarse to accurately align all the echoes The solution is to use interpolation method digital domain, which increases the resolution of the signals while allowing the signals to be sampled at a lower frequency
A combination of coarse and fine delay strategy is adapted in this study The coarse delay, which is the integer multiples of the clock periods, is completed by using a programmable FIFO structure, a 4-tap FD FIR filter generates delays less than one clock period The beamformer in this system is implemented inside a Xilinx VirtexII series FPGA chip (XC2VP20-6FF896C, Xilinx, Inc), where the FPGA has
564 I/O pads, 9280 slices, and 1584 kb block ram In the present design, the dynamic focusing procedure is performed by updating the receive delay for different focus depth Instead of calculating the coefficients in real time, the calculation results are stored in finite state machines and are popped out in sequence according to the depth of the echoes Due to the geometrical symmetry of the linear array, for example, channel 1 and 16 have same time delay coefficient, total 8 finite element machines are used The transition between two states is determined according to distance the dynamic focusing is implemented along the axial direction The detailed discussion of the dynamic focusing is given in Chapter 3
The photograph of completed electronic boards is shown in the Appendix The PCB boards have six layers with four signal layers and two inner layers are for ground and power plane respectively The clock skew and clock signal quality are two main problems for the high speed PCB board design due to the transmission line effect Therefore, the 1-line to 6-line low-skew clock drivers (CDC391, Texas Instruments Inc.) are used One driver is connected directly to the crystal The other three drives are then driven with the 6 clocks generated from the first one
By electrically scanning the beam along the array one element at a time, a series of echo lines can be obtained for one frame This produces a rectangular image with a field of view with a width limited by the length of the array Therefore, the final image contains 33 lines and each line has 1024 sampled data The height of image covers the total depth is 7.88 mm, which is deep enough for high frequency transducer imaging
Considering the possible communication interfaces between external devices and PC, the RS-232 has lower data transferring rate, ISA and PCI are complex and space limited for multichannel application even though they provides very fast transferring speed, the universal serial bus (USB) shows advantages for in this study, such as, high speed (20 MHz) linear ultrasonic arrays has been developed The system can handle up to 64-element linear array transducers and excite 16 channels and receive simultaneously at 100 MHz sampling frequency with 8-bit precision Radio frequency (RF) signals are digitized, delayed and summed through a real-time digital beamformer, which is implemented using a Field Programmable Gate Array (FPGA) Using fractional delay filters, fine delays as small as 1ns can be implemented A frame rate of 30 frames per second is achieved Wire phantom (20 àm tungsten) images were obtained and –6 dB axial and lateral widths were measured The results showed that using a 30 MHz, 48-element array with a pitch of 100 àm produced a -6 dB width of 68 àm in the axial and 270 àm in the lateral direction while using a 35 MHz, 64-element array with a pitch of 50 àm produced the –6 dB width of 65 àm and 550 àm in the axial and lateral direction, respectively Images from an excised rabbit eye sample were also acquired, and fine anatomical structures, such as the cornea, lens and iris, were resolved.
FUTURE WORK 102
There are several ways to improve the image quality The modifications, such as using bipolar pulser instead of negative spike pulser, using high energy pulser, using higher-level FPGA products and increase beamforming channels, are discussed
In Figure 6.1, the spectrum of both negative spike pulser and bipolar pulser are given The –6 dB width of the negative spike pulser is 88 MHz, which is much broader than the bandwidth of the bipolar pulser In other words, if the center frequency of the bipolar pulser is optimized to match the spectrum of the transducer response, more power will be driven to the transducer compared to the negative spike one For example, for a 40 MHz transducer with 50% bandwidth, the spectrum of negative spike pulser will not completely cover the spectrum of the transducer response and the partial power will not be transferred to the transducer
A bipolar pulser has been successfully designed and fabricated Figure 6.2 shows the snapshot the bipolare pulser output from the oscilloscope The highest center frequency of this pulse design is 43 MHz, which depends on the rising/ falling response of the driving circuit This design can generate single cycle or multi-cycle pulse with the maximum amplitude form +100V to -100V The multicycle pulser can be used for the pulsed-wave Doppler processing in the next generation design The further study should be carried out on the design of the pulser with adjustable center frequency, adjustable amplitude and more symmetrical shape
Figure 6.1 Spectrums of the negative spike and bipolar pulser
Figure 6.2 Snapshot of the bipolar pulser
In order to improve the SNR or to allow further tissue penetration depth, the energy transmitted from the pulser to the transducer should be increased Two ways are usually adopted to increase the energy of the pulser: either increasing the pulse amplitude or the pulser duration One solution of extending pulse duration is to use the coded excitation to improve SNR under same conditions, which increases the energy transmitted to the transducer (O’Donnell, 1992; Chiao and Hao, 2003) However, the coded excitation needs “encoding” the pulsers in transmit and use
“decoding” filter in reception in order to maintain the axial resolution This, in turn, increases the complexity of the system design The more direct way is to increase the peak-to-peak value while keeping the duration of the pulsers unchanged The peak acoustic power, rather than average power, limits the signal-to-noise ration (SNR) of real-time images (O’Donnell, 1992) The effect of the increasing amplitude of the pulse while keeping the shape of the pulser unchanged was investigated The monocycle generator (AVB2-TB-C, Avtech Eletrosystems Ltd) was used to excite the one element from 35 MHz, 64 elements array The center frequency of monocycle generator was set to be 35 MHz with the peak-to-peak value increasing from 40 Volts to 320 Volts The waves were displayed using oscilloscope (TDS
5052, Tektronix Inc.) The result is shown in Figure 6.3 The significant increase in echo amplitude is observed when the pulser amplitude increases from 80 Volts to
200 Volts For all the pulses we used, the effective peak-to-peak value is 60 volts, which means there still have the room to increase the energy transmitted to the transducers
An important issue for a real-time beamformer is the data throughput rate There are several ways to improve the data throughput rate within the existing distributed processing architecture The most obvious and relatively easy way to achieve this goal is to replace the XC2VP20-6FF896C (Xilinx, Inc) with higher level of FPGA products, such as Virtex 4 The Virtex 4 will have 12% increase in system beam throughput It is possible to upgrade only the existing memory components to compensate for the new shorter data and program memory access cycles
Figure 6.3 The peak-to-peak value of echo from quartz target using one element from the 35 MHz, 64 elements linear array transducer with variable peak-to-peak value of the monocycle
The lateral resolution can be improved by increasing the number of active channels, such as from 16 channels to 32 channels It is possible to add more input channels to the beamformer However, each added channel requires some additional decoding circuitry on the transmit/receive and control boards One problem associated with more channels is an increase of the total number of controlling signals As shown in Table 6.1 and Table 6.2, if the 32 channel beamforming is adopted, total 284 control lines are required Using current multi-microcontroller structure, it is very difficult to implement those control signals Complex Programmable Logic Device (CPLD) may be the solution for generating control circuitry CPLD is a combination of a fully programmable AND/OR array and a bank of macrocells The AND/OR array is reprogrammable and can perform a multitude of logic functions Macrocells are functional blocks that perform combinatorial or sequential logic, and also have the added flexibility for true or complement, along with varied feedback paths
With the development of the 30 MHz, 64-element phased array in the future, the 64 channel digital beamformer with a 200 MHz sampling rate will be developed This system will provide the necessary electronics for higher frequency arrays with large numbers of elements for larger linear arrays and the proposed 64-element phased arrays Prior to building the entire 64-channel system, two tasks will be performed First, a single channel A/D using a 12-bit analog-to-digital converter (AD9430-210) will be developed based on the layout given in the datasheet for an evaluation board (http://www.analog.com) This task will allow us to evaluate the performance of this A/D in a single-channel environment Second, a 200 MHz clock distribution system will be designed, prototyped, and evaluated
Due to the limited size of the PCB boards, this proposed 64-channel, 200 MHz digital beamformer will be designed using stackable structure (Figure 6.4) By designing in this way, the digital system provides more flexibility and versatility
Table 6.1 Number of control signals require for current design
Components Channels Number/channel Total
Table 6.2 Number of control signals require for new design
Components Channels Number/channel Total
Total 284 compared to the design of laying out all the channels in one single PCB board This digital system is divided into two main PCB boards design: one mother board and 8 daughter boards The mother board has 8 sockets in which the daughter boards can be plugged The system diagram is shown in Fig 101 The 64 channels are grouped by eight In each daughter board, the 8 ADCs (AD9430-210, 12 bits, 210MHz; Analog Devices Inc.) will be used to digitize the RF signals After all 8-channel signals have been digitized simultaneously, the digitized data (12 bits) from each channel will be fed into FPGA (Virtex II, Xilinx Inc.) where the channel allocation and partial beamformer are implemented The summed RF data (16 bits) will be fed into the FPGA in the mother board through the high speed socket (Samtec, Inc Los Gatos, CA) In the mother board the FPGA receive the digital data from the daughter board The other partial beamformer is then implemented in this FPGA Eventually, the summed signal (20 bits) will be send to the PC for display by USB (CY7C68013, Cypress Inc.)
Most beamforming research today has moved away from data-independent beamforming to time-varying algorithms that alter the beamformer according to information extracted from the sensor and beamformer outputs One large sub- category of this is adaptive beamforming, which varies the weights on the different sensors so that the beamformer converges to some statistical optimum Such adaptive algorithms lie outside the scope of this project, but they should benefit from the results found here since many of their algorithms rely on well-known data- independent beamforming methods
Figure 6.4 Schematic of proposed 64-channel digital beamformer
In the current design, the coaxial cables (RG-174), with the characteristic impedance of 50, are used to interconnect between PCB boards RG-174 has good performance for environmental variations, but is lower in overall ruggedness The connectors used on these cables are SMA connectors For the whole system implementation, over a hundred cables and connectors are used, which is bulky The SAMTEC (Samtec, Inc IN) use high-speed connectors, miniature ribbonised coaxial, and transitional PCBS to fabricate the high-speed cable (Figure 6.5) These
RAM cables have the advantages, such as lower crosstalk, lower EMI emission and susceptibility, lower voltage drop, and higher frequency compared to the RG174 coaxes
Figure 6.5 Assembly high-speed connector and cable from Samtec
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