Luận văn thạc sĩ Kỹ thuật điện: Áp dụng các kỹ thuật điều chế độ rộng xung để cải tiến chất lượng điện cho bộ nghịch lưu ba bậc NPC

Image 59 The duty cycle dap and dan in ONTVV...cccsccssscssssssecsecesassseecesesssseseceessssssesssecteseessen sOTwo PWM patterns resulting in Zero COMMON mode voltage...-.-.-...-.Ø 2Bl

ĐẠI HỌC QUỐC GIA TP HCM

TRƯỜNG ĐẠI HỌC BÁCH KHOA

PHAM ĐĂNG KHOA

AP DUNG CAC KY THUAT DIEU CHE DO RONGXUNG DE CAI TIEN CHAT LƯỢNG ĐIỆN NANG

CHO BO NGHICH LUU BA BAC NPC

Chuyên ngành : Kỹ Thuật ĐiệnMã sô: 60520202

LUẬN VĂN THẠC SĨ

TP HO CHI MINH, năm 2018

CÔNG TRÌNH ĐƯỢC HOÀN THÀNH TAITRƯỜNG ĐẠI HOC BACH KHOA —ÐHQG -HCMCán bộ hướng dẫn khoa học : PGS.TS Nguyễn Văn Nhờ

Thanh phân Hội đồng đánh giá luận văn thạc sĩ gồm:

(Ghi rõ họ, tên, học hàm, học vi của Hội đông châm bảo vệ luận vănthạc sĩ)

Xác nhận của Chủ tịch Hội đồng đánh giá LV và Trưởng Khoa quản lý

chuyên ngành sau khi luận văn đã được sửa chữa (nêu có)

CHỦ TỊCH HOI DONG TRƯỞNG KHOA ĐIỆN-ĐIỆN TỬ

ĐẠI HỌC QUỐC GIA TP.HCM CỘNG HÒA XÃ HỘI CHỦ NGHĨA VIỆT NAM

TRƯƠNG ĐẠI HỌC BÁCH KHOA Độc lập - Tự do - Hạnh phúc

NHIỆM VỤ LUẬN VĂN THẠC SĨ

Họ tên học viên : PHAM ĐĂNG KHOA MSHV:7140413Ngày, thang, nam sinh: 10/01/1990 Noi sinh: TP HO CHI MINHChuyên ngành: Kỹ Thuật Điện Mã số : 60520202

I TÊN DE TÀI: ÁP DỤNG CÁC KỸ THUẬT DIEU CHE ĐỘ RỘNG XUNG DECẢI TIEN CHAT LƯỢNG ĐIỆN NANG CHO BỘ NGHỊCH LƯU BA BAC NPCIl NHIEM VU VA NOI DUNG:

+ Khao sát và chon các kỹ thuật điều chế độ rộng xung cho nghịch lưu ba bậc NPC.+ Đề ra phương pháp để đánh giá và so sánh các kỹ thuật điều chế độ rộng xung đã

chọn

+ Xây dựng mô hình mô phỏng trên MATLAB cho tất cả các phương pháp đã chọndé tiến hành lây kết quả va so sánh kết qua của tat cả các phương pháp.

+ Xây dựng mô hình thực của bộ NPC ba bậc Các phương pháp đã chọn được lập

trình trên vi điều khiển TMS320F377D Kết quả lay từ thực nghiệm sẽ được so sánhvới nhau, đông thời kiểm chứng kết quả mô phỏng.

+ Áp dụng kỹ thuật điều chế độ rộng xung của năm bậc NPC và bảy bậc cascadenghịch lưu vào bộ nghịch lưu ba bậc NPC dé triệt tiêu điện ap common mode, đồngthời giảm độ méo dang dòng và giảm ton hao đóng cắt.

Ill NGÀY GIAO NHIỆM VU : 10/07/2017IV NGÀY HOÀN THÀNH NHIỆM VỤ: 03/12/2017V CAN BO HƯỚNG DAN: PGS.TS Nguyễn Văn Nhờ

Tp HCM, ngày 03 thang 12 năm 2017CÁN BỘ HƯỚNG DÂN CHỦ NHIỆM BỘ MÔN ĐÀO TẠO

(Họ tên và chữ ký) (Họ tên và chữ ký)

TRƯỞNG KHOA ĐIỆN-ĐIỆN TỬ

(Họ tên và chữ ký)

ACKNOWLEDGEMENTSThank you to Prof Nguyen Van Nho who have helped guide me through this exciting andchallenging journey, provide insightful feedback, and teach me how to conduct thoroughresearch His wisdom and expertise in this field of study is exceptional, and it was both apleasure and an honor to have him as an advisor and a professor.

| would like to thank Mr Nguyen Van Vui for his practical experience during the experiment

setup.

Finally, | sincerely thank my family for all of their support they have given to me over the years

Multilevel Inverters especially the three-level Neutral Point Clamped Inverters are widely used inmotor drive applications Compared to the conventional two-level inverters, the three-levelinverters offer better harmonic performance However, Common-mode Voltage and NeutralPoint Voltage Imbalance are the two technical challenges that need to be addressed in order tooptimize the performance of motor drive systems The Common-mode voltage causes bearingfailure and Electromagnetic Interference (EMI) These two problems reduce the life expectancyof motors and have other equipment working in close proximity not to function properly.Moreover, the Neutral Point Voltage Imbalance causes excessive stress on switching devices andlow-order harmonics at the output Therefore, both common-mode voltage and neutral pointvoltage imbalance must be mitigated by either hardware or software solutions In this thesis, thesoftware solutions, specifically Pulse-Width Modulation (PWM) strategies are the main focus.The thesis tackles the problem in the literature, which is the common-mode voltage and neutralpoint voltage imbalance are solved separately For example, a certain proposed PWM methodfor CMV reduction does not mention neutral point voltage imbalance, and vice versa Therefore,the thesis aims to select some prominent PWM strategies in the literature and make acomparison among them in terms of CMV mitigation, NP voltage balancing performance, andharmonic distortion The simulation of all the PWM methods are implemented from MATLAB2016b while the experiment is conducted at PERLAB The simulation results are compared againstone another The experimental results are also compared against one another validate thesimulation results

TOM TAT

Nghịch lưu đa bậc, đặc biệt là bộ nghịch lưu ba bậc NPC được sử dung rộng rãi trong các ứng

dụng điều khiển động cơ So với bộ nghịch lưu hai bậc thông thường, bộ nghịch lưu ba bậc chochất lượng đầu ra tốt hơn Tuy nhiên, điện áp common mode và lệch điện áp trung tính là hai vấnđề cần được giải quyết để tối ưu hóa các hệ thống điều khiển động cơ Điện áp common modegây ra nhiều hư hỏng cho động cơ và nhiễu điện từ trường Hai vấn đề này làm giảm tuổi thọ củađộng cơ và các thiết bị xung quanh Hơn nữa, lệch điện áp trung tính tụ gây ra hài bậc thấp ởdòng và áp ngõ ra Do đó, điện áp common mode và lệch điện áp trung tính tụ cần được giảiquyết bởi các phương pháp phan cứng hay phần mềm Trong luận văn này, phương pháp phanmềm đặc biệt là các phương pháp độ rộng xung là trọng tâm chính Luận văn giải quyết vấn đề làđiện áp common mode và lệch điện áp tụ trung tính thường giải quyết riêng lẽ Do đó, luận vănsẽ chọn một số phương pháp điều chế độ rộng xung tiêu biểu và so sánh giữa các phương phápvề mặc giảm common mode, khả năng cân bằng tụ, và độ méo dạng song hài ở ngõ ra Kết quảmô phỏng của phương pháp sẽ được thực hiện trên MATLAB và thực nghiệm sẽ được tiến hành

ở phòng thí nghiệm PERLAB Kết quả mô phỏng sẽ được so sánh đối chiếu với nhau Kết quả thực

nghiệm sẽ được so sánh đối chiếu với nhau và xác nhận kết quả mô phỏng.

DECLARATION| certify that the work is that of the author alone The work has not been submitted previously.The content of the thesis is the result of work which has been carried out since the officialcommencement date of the thesis.

Pham Dang Khoa

2 Literature Review of Common-Mode Voltage ProbleM cccccssssssecsscssesssssssceesseseseescaessesesneeees2.1 6901 9(0(ì 09-0 (000v 22-09200000 9ô

2.2 Causes Of COMMON-MoOde 0/000 0n

2.3 Common-Mode Voltage’s Effects on motor drive SYSTEMS cccecssssecseceecessesssecseseseeesees2.4 Solutions to Mitigate COMMON-MOde VOIltAaBEe cceccesseessecescessesseeceeseeaescseceesesatecseceeesaees2.4.1 Hardware Solutions to Mitigate ComMONn-Mode Voltage - s<<s<-2.4.2 Software Solutions to Mitigate Common-Mode Voltage - -c +53 Literature Review of Neutral Point Voltage Imbalance Problem - - sec +<c<csxssssss3.1 Neutral Point Voltage Imbalance Definition ccecesssesecescessesseecesseaeseseceesesaeseseceseeseaees3.2 Causes of Neutral Point Voltage Imbalarnce - c + + c1 1 1n HH ng ng g3.3 NP (0ìr 2-8009 -Ì s11 1 7

3.4 Solutions to Mitigate Neutral Point Voltage Imbalance - -c cccxsssssssseeerree“V097

5 Implementations of the Selected Pulse-Width Modulation (PWM) Methods in Three-LevelNeutral 2Ì0® Ƒ-019-o01) vi 177

.15161715

.19.20212121.22.26.26.333838383939A7

.49

5.1 Conventional Sinusoidal Pulse-Width Modulation (SPWM) 4Ø5.2 Sinusoidal Pulse-Width Modulation with the Proportional Controller (SPWM+P) 505.3 Sinusoidal Pulse-Width Modulation by Song (SPWM+Song) - cc+-c<-<cce Ð25.4 Centered Space Vector Pulse Width Modulation with the Proportional Controller

5.5 Optimized Nearest Three Virtual Vectors (ONTVV) cccccsscecsrcessrecesssecsetsceeesetscsterseteeteers DO5.6 Zero Common-Mode Voltage Pulse-Width Modulation with reduced switching loss(ZCMV PWM with reduced Switching lOSS) ccccsecsesessrecescesceceseesceeceserscessuscateesetsctersetecserse# Od5.7 Zero Common-Mode Voltage Pulse-Width Modulation with reduced current ripple(ZCMV PWM with reduced current ripple) cccccccscsesssscsecsssesssscsecsesesaeseseceesssasseeeceesssasesseseeses OO6 SiMUIATION ANA EXPELIMENt cscceesesssssseceecescesaescsececesaesesecoesesausseceeseseessecsesssasscseceesssassssecsssssesesOD

100000 19-117 .6.1.1The SPWM with Proportional Controller (SPWMI+P) cc.cccsecce c ,Õ6.1.2 The Centered Space Vector with Proportional Controller (CSVPWMI+P) 696.1.3 Sa 3 Ð6.1.4 The Optimized Nearest Three Virtual Vector (ONTVV) 16.1.5 The Zero Common Mode Voltage PWM with reduced switching loss (ZCMV PWM +FECUCE SWITCHING lOSS) cesecescesssecsscescseceseeecsecessaecesensceeeeseteceeesesecssatscsecesatscssatscstesstscserss TD6.1.6 The Zero Common Mode Voltage PWM with reduced current ripple (ZCMV PWM +FECUCEM 9014-0339 1-6.2 SIMULATION R€@SỤẨS -.- - - cc cọ nọ ng nọ ng ch cu su suy ng nh che sreeeeeseereereereee Z &6.2.1 The SPWM with Proportional Controller (SPWM+P) - <.-.- 46.2.2 The Centered Space Vector with Proportional Controller (CSVPWM+P) 306.2.4 The SPWM+SONGB c:ccsssccesssscstcesetececesesecssseseneceseusceeeeserscoeessstecseaeseaecesanscesauscaeeesateeeseessOD6.2.3 The Optimized Nearest Three Virtual Vector (ONTVV) Ũ6.2.5 The Zero Common Mode Voltage PWM with reduced switching loss (ZCMV PWM+ FECUCEC SWITCHING li _-6.2.6 The Zero Common Mode Voltage PWM with reduced current ripple (ZCMV PWM+ -90009-o0902-0i0ïi99 08 \02)

6.3 Comparison and Evaluation of Simulation Resulfs -. e-<c<-<<<e-s -e.-e LOG

6.4 EXPEriMent 800 ốồồỒồ

1249-0000 0 7

6.5.1 The SPWM with Proportional Controller (SPWM+P) - 24

6.5.2 The Centered Space Vector with Proportional Controller (CSVPWM+P) 129

6.5.3 The Optimized Nearest Three Virtual Vector (ONTVV) 1356.5.4 The SPW M+SONG cccsssecseceecessesseecoesesceseescsecnssesaescsecoesesassesecoesssasscsectsssatsssaesssseessetees LAO6.5.5 The Zero Common Mode Voltage PWM with reduced switching loss (ZCMV PWM

+ reduced SWITCHING lOSS) cecsccesessescseceecesaesesecoesesaeseseceesessesesscsecsssssasssseceesessssesessessesseets L4G

6.5.6 The Zero Common Mode Voltage PWM with reduced current ripple (ZCMV PWM+ -90009-o090 (0ï 000118 .Ẻ6.6 Comparison and Evaluation of Experimental Resulfs - +<<<<-<< -.- LOG7 CONCIUSION and FUTULE WOFKS ccccccsecsecescenceccecceeceeceeceeceeceecsecsecusanseassasssacenceececceecetctestecescesceees LOZ

Figure 1: Topology of Three-Level NPC lnV€F©F - c2 1 2 1T HH ng ngưng ng nưưyn

Figure 2:

Figure 3: A three-level NPC inverter with a diode front-end -. cccccc nh HH nre

Figure 4:Figure 5:

Figure 6: The shaft voltage and common-mode voltage in a driven-PWM inverter

Figure 7:Figure 8:Figure 9:Figure 10Figure 11:Figure 12:Figure 13:Figure 14:Figure 15:Figure 16:Figure 17:

Figure 18:Figure 19:Figure 20:Figure 21:Figure 22:Figure 23:Figure 24:Figure 25:

LIST OF FIGURES

Space Vector diagram of the NPC CONVESTtELS :cccsscecetcessrecercesstecsseesceecesetsceeeesereceeeeseneens

Electrical and physical models of parasitic capacitances in a motOr Electrical representation of parasitic capacitances in A motOr - -«< << <<<<2

-Bearing currents IN A iOẨOíF - «cv nh TH TH cà kh nh nh kh nh vàn

An isolation transformer for CMV mitigatiOn ác cà LH H HH ng ng rưệuMii/-s-i8F-I8aiiesi-809)) 08:19 1177 ăn Ú 9620009 0(( 09-000) 00: 901100

A three-level NPC inverter with an addition of a fourth-Ìeg - ‹ -<-<-sxs«2Two 2-level Inverters connected to an Induction Motor with Open-End Windings Two Cascaded H-bridge Inverter connected to an Induction Motor with Open-End

Integrated DC choke in the CSI for CMV elimination cccccsececesesseeceesseesseeeneeneesIntegrated AC choke in VSI for CMV elimination cccccseceecessessessseceecesassseeceeseeeeeeeenslix-2g-i-909.90 12.1177 Circular-shaped integrated 080i) 018

An auxiliary circuit for CMV eliminatiOn cà k2 n HH HH ngMa PÌ-Ä| 0s00i 5-0901 2ái 1i .Impact of Dead time on CM voltage generatÏOn ccccc HH Hy ngThe three-level NPC inverter with diode front-end - c sec hinh re

Effects of inverter operating modes on NP voltage and NP current Absolute NP Ripple Magnitude for 4200UF vs S40UF ceccessseceseescecesetecereesstecseetsees

Dynamic NP Performance for 4200UF vs 84OUF - SG SA SH ng reSpace Vector Diagram for Sector 1 Vrer is within the subsector 2 -«-

17192122222424272728

282929303131

323236363839404041

Obtained from 0i +.

Figure 40:Figure 41:Figure 42:Figure 43:Figure 44:Figure 45:Figure 46:Figure 47:Figure 48:

Region A, B, C for the approximation of the optimum value of amplitude K Image

59

The duty cycle dap and dan in ONTVV cccsccssscssssssecsecesassseecesesssseseceessssssesssecteseessen sOTwo PWM patterns resulting in Zero COMMON mode voltage -.-.- -.Ø 2Block diagram of current-based mapping PWM to optimize switching loss 64Flowchart of the ZCMV PWM with reduced switching loss - Ø5Algorithm of determining which phase is mapped to d sequence ÕThe mapping of s¡ and s¿ to other two phases when transitioning to a new zone 66The three-level NPC inverter implemented in MATLAB Simulink Ô 7The control block of the SPWM+P in MATLAB Simulink <<««<s<<« -„@ØThe control block of the Centered Space Vector PWM with Proportional

.70

The control block of the SPWM+Song 5c - cà eseisrersrrrreeeereerssereeccc DL

Figure 50:Figure 51:Figure 52:Figure 53:Figure 54:Figure 55:Figure 56:Figure 57:Figure 58:Figure 59:Figure 60:Figure 61:Figure 62:Figure 63:Figure 64:Figure 65:Figure 66:Figure 67:Figure 68:Figure 69:Figure 70:Figure 71:Figure 72:Figure 73:Figure 74:Figure 75:Figure 76:

The control block 600 19) 0021 .The control block of the ZCMV with reduced switching loss in MATLAB SimulinkThe control block of the ZCMV with reduced current ripple -s+ s<<<5I0) 19v 0/000 2-0 70/70/00 The Frequency Spectrum of A-Phase Voltage Vạn - -Ă Ăn SH HitThe LIN@-LINE /0 r0 .The Frequency Spectrum of Line-Line Voltage Vạo - SG S ng re.The three-phase Currents Ïa, ib, Íc - - c c2 2n SE 1n SH vn HH KH TH ng ng ve riccThe Frequency Spectrum of A-phase CUFF€TnẲ Ïa - S St ng ng.The DC-LINK 1/2)ì 0/70, The Frequency Spectrum of Neutral Point Voltage Vp (Vci-Vc2) Ÿc.c<c-S-IU-®%900u)9i0)// (02-0200 0/118 .The Frequency Spectrum of Common-Mode Voltage Vụo - 7 52-7255 c+<<52The 0142-190-000 20/70/70, 10 The Frequency Spectrum of A-Phase Voltage Vạn -.- c7 Sàn SH,M8 B02 The Frequency Spectrum Of À 0 The Three-Phase Current ia, ib, Íc - -¿- E 2E E C2 3E SE SE 3E xv E KH ư kEnnưy vHrưv re rưThe Frequency Spectrum of A-Phase Currenf Ïa .- SĂc S S2 si riệnThe DC-link Capacitor Voltage /500/ 117 .The Frequency Spectrum of Neutral Point Voltage Vn (V‹1 — Ve2).s cessecsreessreessesereeeesIWU-®%900u)9(0)// (02-0200 r0 1 The Frequency Spectrum of Common-Mode Voltage Vno Ặ S7 cc c2The Three-Phase Voltage Van, Vin, Vícn c0 TC SH HS HH HH ch KHg ng traThe Frequency Spectrum of A-Phase Voltage Van -. SÁS nheII: 8A0 .The Frequency Spectrum of Line-Line Voltage Vạp - 5 55c sec se

7576767777781819.30.30.308181828283.33

.34348585.3686

Figure 77:Figure 78:Figure 79:Figure 80:Figure 81:Figure 82:Figure 83:Figure 84:Figure 85:Figure 86:Figure 87:Figure 88:Figure 89:Figure 90:Figure 91:Figure 92:Figure 93:Figure 94:Figure 95:Figure 96:Figure 97:Figure 98:Figure 99:

Figure 100: The Frequency Spectrum of Neutral Point Voltage Vop cccccecessesssecsesessesseceeensFigure 101: The Common-Mode Voltage Voo cceccessesssssecescessessseceecesaesesecoecesseseaeseeeeesaeeceeseeeaeeeaesFigure 102: The Frequency Spectrum of Common-Mode Voltage Vụo - cà s2H20I-019c1006)-7.0xàr A0000 10777

The Three-Phase Currents ia, ib, Íc 2 - E2 E22 3E 2E SE 3 SE HH KH ưng reThe Frequency Spectrum of A-Phase Current Ïa - - <7 5c S22 s+x se reeseThe DC-LiINk Capacitor Voltages A/T0A/ 7 The Frequency Spectrum of Neutral Point Voltage Vn (V1 — Ve2) cessscscessrecerecetseseeensThe COMMON-MOde Voltage Vno sssccescesssssseceecesesssecesesaeseeeceeseeseseeseseseesesaeseseceeseesnseeaesThe Frequency Spectrum of Common-Mode Voltage Vno sccssecereessecsscesseecceeesseeesThe Three-Phase Voltages 0/78/72 ốẽ The Frequency Spectrum of A-Phase Voltage Vạn - Ă Sàn 2 ng seI0 800/2 7 The Frequency Spectrum of Line-Line Voltage Vạp óc ctyThe Three-Phase Current ia, ib, Íc - - - - c< 2E 1E SE 3E E1 SxY YEY ưk E KHY ư KEgy EH rư reraThe Frequency Spectrum of A-Phase Current Ïa - - c5 c2 sec se.The DC-Link Capacitor Voltages Voi, Vc¿ - 2 - c St 2n 1n TY HH TH kg ng HH nưệtThe Frequency Spectrum of Neutral Point Voltage Vn (Vcr — V‹2) -Ặ+-c <2IU-®9000)9(0)/ 0e -0/2)00r 0/10 The Frequency Spectrum of Common-Mode Voltage Vno -.«< << <5The xo A007 The Frequency Spectrum of A-Phase Voltage Vạn - -.-SSc cĂ n2 ng riecThe 5U 800/2 .The Frequency Spectrum of Line-Line Voltage Vạp - 5c SScSS 2+ sesseeeeeThe Three-Phase Currents ia, ib, Íc ¿c2 2c 3E 1E 3E ESEY vu Hy HưThe Frequency Spectrum of A-Phase Current Ïa 5< c5 S22 x + srsesesesrssrceThe DC-Link Capacitor Voltages Vc1, Vc¿ - n1 2n 1n TY HH ng HH ng

8787

88888989

9090919192929393

949495959696979798989999100

Figure 104:Figure 105:Figure 106:Figure 107:Figure 108:Figure 109:Figure 110:Figure 111:Figure 112:Figure 113:Figure 114:Figure 115:Figure 116:Figure 117:Figure 118:Figure 119:Figure 120:Figure 121:Figure 122:

The Frequency Spectrum of Common-Mode Voltage Vụo -.- - 2< <<c< 2555THD of Phase Voltage Van of 7 PWM strategies for 25.250 load angle

THD of Phase Voltage Vạn of 7 PWM strategies for 48.54° load angle

THD of Phase Voltage Vạn of 7 PWM strategies for 62° load

angle -THD of Phase Current ia of 7 PWM strategies for 25.25° load angle

THD of Phase Current ia of 7 PWM strategies for 48.542 load angle

THD of Phase Current ia of 7 PWM strategies for 62° load

angile WTHD of output voltage Van of 7 PWM strategies for 25.25° load angle

WTHD of output voltage Van of 7 PWM strategies for 48.54° load angle

WTHD of output voltage Van of 7 PWM strategies for 62° load angle

.100.101.101.102102.103103104105.105.105106107107108.108.109.109Absolute maximum magnitude of NP voltage imbalance under balanced condition, 110

Figure 123: Absolute maximum magnitude of NP voltage imbalance under balanced condition,“y0 0 do in

Figure 124: Absolute maximum magnitude of NP voltage imbalance under balanced condition,A700 UF, 62° load 2.0 .111

Figure 125: Dynamic Performance under balanced load condition, 25.25° load angle, C = 4700

112

Figure 126: Dynamic Performance under balanced load condition, 48.54° load angle, C = 4700

112

Figure 127: Dynamic Performance under balanced load condition, 48.54? load angle, C = 4700Figure 128: The THD of line-line output voltage Vap under unbalanced load condition for C =

4700 uF

Figure 129: The THD of output phase current ig under unbalanced condition for C = 4700.114Figure 130: The WTHD of output phase voltage Van under unbalanced condition for C = 4700Figure 131: Dynamic Performance under unbalanced condition for C = 4700 „F

Figure 132: Absolute maximum magnitude NP voltage imbalance under unbalanced conditionFOr C= 4700 UF ue

Figure 133Figure 134Figure 135:Figure 136:Figure 137:Figure 138:Figure 140:Figure 139:Figure 141:Figure 142:Figure 143:Figure 144:Figure 145:Figure 146:Figure 147:Figure 148:Figure 149:: The block diagram of the power and control CÏFCUIĂ -.- «55s s+<sx+ss2: The pole voltages Vao, Veo, Vco (top -> bottom)) - - -s- c5 ss< se se essesseresThe pole voltage Vao, Vbo, Veo With the resistor load - - «5< s55 << <<<<s2The two DC-Link Capacitor voltages V‹¡ and V.2 read by the ADC module

The phase current ia read by the ADC module - -<cccc se srseresThe phase current ip read by the ADC Module cee cesstecessesssecsecesesecesetsceeeeseeeesThe IGBT gate river =

I0 2-0) 9 0

The TMSF28377D microCOritFO ÏÏ@TF - +: S326 E1 3x 3k ng nh ng vn.The Voltage 8-1103 0077

The CUIreNt SENSING 033100077

I0 4009/2003

The 2 90 46-7 aiic 17

The balanced three-phase R-L load (R = 33.3 0, L= 2.71 mhH)

The three-phase voltages Van, Vpn, Ven (100V/div, 5.00 ms/div) The Frequency Spectrum of A-Phase Voltage Van ssscsccssrecsrcesssscescesereecesseessteenesThe line-line voltage Vab (100V/div, 5.OOMS/GIV) :cccecesccesesesssssrscsecsscteneeees

117118118119119120121121122123123123124124124

125125113

.113

115116

116

Figure 150: The Frequency Spectrum of Line-Line Voltage Vạp - <7 25c secexcce2Figure 151: The three-phase Current ia, ib, Ïc 7 2< 2 3 S1 2n 1n H1 HH HH ng ng ngưynFigure 152: The Frequency Spectrum of Phase Current Ïa - c5 cc + SSS secFigure 153: The Common-Mode Voltage (100V/div,5.00ms/diV) -.- c7 c2Figure 154: The Frequency Spectrum of Common-Mode Voltage Vno - -S+5 555Figure 155: The DC-link capacitor voltages V‹¡, Vc2 at the transient state (100V/div,

.126126127128129

129

Figure 156: The DC-link capacitor voltages V1, Vc2 at the steady state (100V/div, 5.00ms/div).Figure 157: The Frequency Spectrum of NP voltage Vn (Vc1 — Vc2) sssesccescessesssseseceesesatssseceeensFigure 158: The three-phase voltages Van, Vpn, Ven (100V/div, 5.00ms/div) Figure 159: The Frequency Spectrum of Phase Voltage Van c:sssssscsscesssesecsessessssesecseeesaesFigure 160: The Line-Line Voltage Vab (100V/div,

Figure 161: The Frequency Spectrum of Line-Line Voltage Vab ccsssssecscesssssseceesssesseneeesBH20I-01.Y⁄2015)-8014 19v 1-0-0 10 1010 Figure 163: The Frequency Spectrum of Phase Current Ïa - 5< St sesrssxeeFigure 164: The Common-Mode Voltage Vno (100V/div, 5.00ms/div) -. -Figure 165: The Frequency Spectrum of Common-Mode Voltage Vụo Ÿ S22Figure 166: The DC-link capacitor voltages V‹¡, Vc2 at the transient state (100V/div,

Figure 167: The DC-link capacitor voltages Vc1, Vc2 at the steady state (100V/div,

Figure 168: The Frequency Spectrum of NP voltage Vn (Vc1 — Vc2) sescsccsscessessrscseecsesessnscsecseeeeesFigure 169: The three-phase voltages Van (top), Vbn (middle), Ven (bottom) (100V/div,

Figure 170: The Frequency Spectrum of Phase Voltage Van cssssccscccesssssseceecsssssssesesssseseeeensFigure 171: The Line-Line Voltage Vab (100V/div, 5.OOMS/iV) c:cccccecesssssssssecseecsscseeseeesenensFigure 172: The Frequency Spectrum of Line-Line Voltage Vab :scsccssscscesssessecsessssssseseeeesFigure 173: The 0-00-0000 108 00 776

.130.130.131

131.132.132.132.133134

.135

135136

.136137137138138

Figure 174: The Frequency Spectrum of Phase Current Ïa - 2< cty,Figure 175: The Common-Mode Voltage Vno (100V/div, 5.00ms/div) c-<cc Figure 176: The Frequency Spectrum of Common-Mode Voltage Vno ssccececessecseesseesseneesFigure 177: The DC-link capacitor voltages Vc, Vc2 at the transient state (100V/div,

Figure 178: The DC-link capacitor voltages Vc1, Vc2 at the steady state (100V/div,

Figure 179: The Frequency Spectrum of NP voltage Vn (Vc1 — Vc2) sssssecercessessssesecesceseseseeeeseeseaesFigure 180: The three-phase voltages Van, Vpn, Ven (100V/div, 5.00ms/div) Figure 181: The Frequency Spectrum of Phase Voltage Van :scsccscsssessssseecsssessescsecseeseeseneensFigure 182: The Line-Line Voltage Vab (100V/div, 5.00ms/diV) c-cccc sec sceeeeeerreeFigure 183: The Frequency Spectrum of Line-Line Voltage Vạo -.- S2 sec eseeereeH20I4-01.1/28001-8014 19v -0o0 i00 101010 .Figure 185: The Frequency Spectrum of Phase Current Ïa -cScc SE secFigure 186: The Common-Mode Voltage Vno (50V/div, 5.00ms/diV) -. c -c-e-Figure 187: The Frequency Spectrum of Common-Mode Voltage Vụo -. 7 2c s+Figure 188: The DC-link capacitor voltages Vc, Vc2 at the transient state (100V/div,

Figure 189: The DC-link capacitor voltages Vc1, Vc2 at the steady state (100V/div,

Figure 190: The Frequency Spectrum of NP voltage Vn (Vc1 — Vc2) sssescceccesssesssesecescesaessseceesessaeesFigure 191: The three-phase voltages Van (top), Vbn (middle), Ven (bottom) (40V/div,

Figure 192: The Frequency Spectrum of Phase Voltage Van c:ccsssssccercesssssseceesessesssscecsssesenseaesFigure 193: The Line-Line Voltage Vạn (40V/div, 5.OOMS/GIV) c:cccceccesceeccssessesssssteceecsseeeneeeesFigure 194: The Frequency Spectrum of Line-Line Voltage Vạp - <7 2c c2 sec eeeeFigure 195: The three-phase Current ia, ib, icce.sssssscceccesssssseceecesseseseceesessesnecaeceeaesesecoesesauenseceeeaasensFigure 196: The Frequency Spectrum of Phase Current Ïa <5 chenFigure 197: The Common-Mode Voltage Vno (20V/div, 5.00ms/div) -c-cc-scccccecc-

139139139

139

140140141142143143143143144144

145

145146

146147147148148149

149

Figure 198: The Frequency Spectrum of Common-Mode Voltage Vụo LAGFigure 199: The DC-link capacitor voltages Vạ, V‹¿ at the steady state (40V/div,

Figure 200: The Frequency Spectrum of NP voltage Vn (Vc1 — Vc2) csccscscceesetseceestestsseeeeneenestteee bodFigure 201: The three-phase voltages Van, Vbn, Ven (100V/div, 5.00ms/div) LOLFigure 202: The Frequency Spectrum of Phase Voltage Van ccsccscsceccestsesseessecsecsessssssstseeeenes LODFigure 203: The Line-Line Voltage Vab (100V/div, 5.00ms/diV) - . -cceccecee 52Figure 204: The Frequency Spectrum of Line-Line Voltage Vab csssccsccscsesessesttesteseeenenes LOSFigure 205: The three-phase Current la, ib, iccssccessssssecessescsscesereceecessrecseetsceecssatscseetscstesstsctterseteesteeees LOOFigure 206: The Frequency Spectrum of Phase Current ia ccsccecececestssssssnessecnecsessetssssstteeeees LOAFigure 207: The Common-Mode Voltage Vno (100V/div, 5.00ms/div) 154Figure 208: The Frequency Spectrum of Common-Mode Voltage Vụo 155Figure 209: The DC-link capacitor voltages Vi, V‹¿ at the steady state (100V/div,

Figure 210: The Frequency Spectrum of NP voltage Vn (V‹+ — Vc2) à 2c sec LOOFigure 211: The THD of Phase Voltage Van under balanced condition for C = 4700

Figure 212: THD of Line-Line Voltage Vab under balanced condition for C = 4700 wF 158Figure 213: The WTHD of Line-Line Voltage Vab under balanced condition for C = 4700 uF 158Figure 214: The THD of the Phase Current ia under balanced load condition C = 4700 wF 159Figure 215: The dynamic NP voltage balancing performance under balanced load condition C =4700 LF at the transient State Figure 216: The Magnitude of DC Component of NP voltage at the steady state under loadCONITION C = 4700 LP uu n6 e6.H -‹:Figure 217: The Magnitude of the 3 component of NP voltage at steady state under loadCONITION C = 4700 LP uu n6 e6.H -‹:

LIST OF TABLES

Table 1: Phase leg output voltages and associated switching commaand - LOTable 2: Comparison of Design Data Between the Integrated Choke and Separate Reactors(@® 11 <<:Table 3: CMV magnitude corresponding to each Voltage VeCtOr . ccc<cccssecese-e.s 24Table 4: The effects of switching states ON NP CUITeNt ccccceessecesseecescesereceeeessrecssetscstessetscsrerser eATable 5: NTVV’s Virtual Vector Composition for SeCtOr Low ec ceeesseeseceeceseesseeeseceessasesseeesseesee sOTable 6: Mapping function in Zero Common Mode Voltage PWM < Ø4Table 7: The three-level NPC inverter ParaMetelS ccscceccessssssecsecessessseceeseseessaecssssssscsecssssstneeee sOTable 8: The operating condition of the three-level NPC inverter - -.<<<-.-.e- 117

LIST OF SYMBOLS

NPC: Neutral Point ClampedPWM: Pulse Width Modulationm: modulation index

R: load resistorL: load inductorSPWM: Sinusoidal Pulse-Width ModulationSPWM+P: Sinusoidal Pulse-Width ModulationCSVPWM+P: Centered Space Vector Pulse-Width ModulationSPWM+Song: Sinusoidal Pulse-Width Modulation by author SongONTVV: Optimized Nearest Three Virtual Vectors

ZCMV PWM + reduced switching loss: Zero Common-Mode Voltage Pulse-Width Modulationwith reduced switching loss

ZCMV PWM + reduced current ripple: Zero Common-Mode Voltage Pulse-Width Modulationwith reduced current ripple

Chapter 1: Introduction

1.1 BackgroundMultilevel inverters have gained a tremendous interest in motor drive applications, especially inmedium and high voltage range due to higher output voltage quality, higher voltage rating foreach phase leg, and more redundant states of voltage vectors than conventional 2-levelinverters The output voltage quality is superior thanks to having more voltage levels, i.e three,five, seven levels Hence, the output voltage waveform in multilevel inverters more closelyresembles the pure sinusoidal waveform than that of the conventional 2-level inverters Someprominent topologies of multilevel inverters include three-level Neutral Point Clamped (NPC)inverters, flying-capacitor inverters, H-bridge cascaded inverters In this thesis, the three-levelNPC inverter is investigated thoroughly

The topology of the 3-level NPC inverter is shown in Fig 1 It includes 2 DC-link capacitors at theinput, 12 power switching devices for 3 phase legs, and 2 clamping diodes for each phase leg.Two DC-link capacitors are connected through a neutral point (NP) Ideally speaking, the NP

voltage has to be half of the DC-link voltage However, in practice, the NP voltage can deviatefrom this level The load could be a three-phase RL load or a motor with a floating neutral point.

For each phase leg, S1x and S3x are complementary as well as S2x and S4x {x = a, b, c} Theswitching states of these switches determining the output voltage of each leg Vy {x = a, b, c} areshown in Table 1:

Six S2x S3x Sax Vx0 0 1 1 01 1 0 0 +Vpc0 1 1 0 +VNp

Table 1: Phase leg output voltages and associated switching commandsThe three phase legs of the converter produce 33 = 27 switching states and 19 space vectors (SV)as shown in the figure 2 The space vector diagram has six sectors Each sector has foursubsectors

12 211

022 & 200X 01 111 100

000112 212 Alpha012 120

concern in medium-high voltage motor drive applications since it dictates the efficiency of aconverter In fact, switching loss reduction has been a research topic of the field Numerouspapers [2][3][4][5] has focused on it by using Discontinuous PWM (DPWM) or not lettingswitches commutate when a phase current magnitude is maximum As far as the output qualityis concerned, current ripple reduction has been a major focus of the field since it leads to lowertorque pulsation in a motor.

In terms of the NP voltage balancing, the steady and transient state are investigatedthoroughly In steady state, the maximum NP ripple magnitude is measured for a particular

PWM method In transient state, the NP voltage performance, which is how long it takes for aparticular PWM method to reduce NP imbalance from an initial value to an acceptable level, ismeasured

In terms of CMV control, the magnitude of CMV, the step height of CMV, and the number ofCMV transitions in one carrier cycle will be observed for each PWM method Since these factorswill determine how effective a particular PWM is in CMV reduction/elimination

In terms of output quality, the total harmonic distortion and the weighted total harmonicdistortion of output voltage and current are calculated for each PWM method

All of these performance criteria above are used to address the following research questionsrelating to the NP voltage control, common-mode voltage, switching loss, and output quality ofthe three-level NPC inverter, which includes:

1/ What performance criteria does a particular PWM compromise in order to achieve a NPvoltage balancing?

2/ What performance criteria does a particular PWM compromise in order to achieve CMVreduction/elimination?

3/ What performance criteria does a particular PWM compromise in order to achieve superioroutput quality?

4/ Is there any PWM method that can achieve all performance criteria at the same time?In order to answer all the questions above, some prominent PWM methods in the literature areselected and then quantitatively compared with one another

1.3 Current Understanding of the Problem, Existing Solutions, and Barriers to these SolutionsThe problem of PWM strategies presented in the literature is that they are not analyzed in acomprehensive manner For example, most papers which develop PWM methods for NP voltagebalancing only pay attention to NP voltage imbalance and neglect CMV reduction/elimination.While PWM strategies developed for CMV control in other papers ignore the NP voltagebalancing All papers show the output quality in terms of harmonic distortion of current andvoltage However, the switching loss may or may not be included in the papers Therefore, in

order to evaluate the effectiveness of any PWM strategy, it must be investigated in acomprehensive manner.

Some papers in the literature do attempt to analyze the performance of PWM methods in termsof NP voltage balancing and CMV control However, they do not compare their performance withthat of the well-known PWM methods, such as convention Sinusoidal PWM (SPWM) or SpaceVector Modulation (SVPWM) Moreover, switching loss is not mentioned in these papers since itis a crucial factor in medium-high voltage applications Therefore, it fails to give a designer orbeginner a ‘big picture’ of the performance of PWM strategies

The barriers to give a ‘big picture’ of the performance of PWM methods available in the literatureis the number of the strategies There are a large number of PWM methods presented in theliterature Most of them can be categorized into 3 main groups, i.e carrier-based PWM (CPWM),Space Vector PWM (SVPWM), and Selected Harmonics Elimination (SHE) In fact, a huge numberof PWM strategies are only the variants of these 3 main types For example, in carrier-basedPWM, a new method can be developed by modifying the offset If the offset is zero, then itbecomes a Sinusoidal PWM In addition, the offset can be different from zero (either fixed orvariable) depending upon a specific control purpose, i.e NP voltage balancing, CMVreduction/elimination, and switching loss reduction Therefore, the number of PWM strategieswill be limited in order for the thesis to be manageable

1.4 Expected Results and Its SignificanceThe results of the thesis will pinpoint the strengths and weaknesses of some prominent PWMstrategies presented in the literature They are going to help the designers choose which PWMmethod is the suitable one for their own applications Moreover, PWM strategies which will bedeveloped in the future should be assessed in a comprehensive manner by considering all theperformance criteria

Chapter 2: Literature Review of Common Mode Voltage

Problem

2.1 Common Mode Voltage Definition in Three-Level Neutral Point Clamped Inverters

SÍA Ud st Cae} sic

ies bt D3 i =1 k+ $2B os f Cae} 4h & $2c°

Vo, total = Vc, rectifier + Vc, inverter

Vc, rectifier = VpgVM, inverter = VNpWhere: Vcw,tora = the total common-mode voltage generated by a rectifier and an inverterVem,rectifier = the common-mode voltage generated by a rectifier

VcM,inverer = the common-mode voltage generated by an inverterIn this thesis, however, it focuses on the common-mode voltage generated by an inverter(VcM,inverter) and the instantaneous Vemiinverter is calculated as:

Vap+Vpp+Vcp

3

Vw, inverter = (1)2.2 Causes of Common Mode Voltage in Three-Level Neutral Point Clamped Inverters

The switching modulation of an inverter produces a switched output voltage waveform, which,according to the formula (1), results in non-zero instantaneous common-mode voltage.

2.3 Common Mode Voltage’s Effects on Motor Drive SystemsShaft Voltage and Bearing Current

Shaft voltage and bearing current has been a well-known problem for motors since 1924 [6].There are three sources of shaft voltage, namely electromagnetic induction, electrostaticcoupled from internal sources and external sources The high level of common-mode voltagedv/dt is the external source that causes shaft voltage and bearing current due to parasiticcapacitances present in motors These types of parasitic capacitance are shown in the Fig 4

Stator Winding Bearing

Api )

mI TeaseMode oO shat

CỐVin, O | Rotor E:

as 2 L4

Figure 4: Electrical and physical models of parasitic capacitances in a motor [7]

1/ Stator to frame capacitance or Csr: This is the primary capacitance that is formed betweenthe stator winding and the grounded frame It is the largest single parasitic capacitance in themotor Most of the common mode current due to the high CM dv/dt flow through this path [7]

2/ Stator to Rotor capacitance or Csr: This capacitance is formed between the stator windingand the rotor frame The value of this capacitance is small but is important in determining themagnitude of the shaft voltage [7].

3/ Rotor to Frame capacitance or Cre: The rotor to frame capacitance completes the chargingpath that started from the stator winding to the rotor surface The value of this capacitance istypically about 10 times that of the stator winding to rotor surface capacitance (Csr) Since thevoltage across a capacitor is inversely proportional to its capacitance value, the most of theapplied common-mode voltage appears across Csr and only a small voltage is developed acrossCer This voltage is called shaft voltage Hence, the rotor to frame capacitance is also essential incalculating the shaft voltage [7]

4/ Shaft to Frame capacitance or Bearing capacitance Cg: When the motor is rotated at orabove a certain speed, the balls in a ball-bearing of the motor float up and occupy the space inbetween the inner and outer race of the bearing An insulating film is formed by the lubricantmedium in which the balls are floating The value of his capacitance depends on the shaftspeed, type of lubricant used, the surface area of the ball in the bearing, the temperature of thelubricant, and the mechanical load on the shaft This parasitic capacitance is formed only whenthe motor rotates The value of this capacitance is crucial in determining the bearing currentand dictates the life of the bearing [7]

The shaft voltage is formed as a result of the common-mode voltage and parasitic capacitances.Its value is calculated as:

_ CsrVs H Vo M

Where: Vo; is the shaft voltageVey is the total common-mode voltage generated by a rectifier and an inverterCsp is the stator to rotor frame capacitance

Cpr is the rotor to frame capacitanceCp is the bearing capacitance

The ratio of Vsu/Vcw is typically 1:10 since the value of Cạr is much larger than that of Csr Theexact ratio depends on the size of the motor The waveform of the shaft voltage and common-mode voltage are shown in the Figure 6 below

2/ Electric Discharge Machining (EDM) bearing current (iz)Due to the common-mode voltage, an electric charge is stored in the capacitance (Cpr) that isformed across the rotor body and the grounded stator frame The voltage across Cre ispractically the voltage across the shaft The voltage across this capacitor can keep building upand eventually reach such a level so as to cause the insulation of the lubricating film to break

down This dielectric breakdown results in the charge stored across Cer to discharge throughthe insulating film of the bearing and this phenomenon is called Electric Discharge Machining(EDM) Since the capacitance of Crr is relatively higher than Csr, the energy stored in Crr can besufficiently large to cause bearing damage EDM currents are not generated if the motor shaft isgrounded or the rotating speed is low enough for the ball bearing assembly to contact with thestator frame [7].

3/ Common-mode current flow through shaft due to poor grounding (is)lf the motor frame is poorly grounded and the motor shaft is connected to a mechanical loadthat has much lower ground impedance, the common mode current that flows at every edge ofthe common mode voltage through the capacitor CSR and charges up the rotor structure nowfinds a way to flow through the shaft into an external ground that has a lower impedance Thecurrent bypasses the bearing and makes its way safely into a lower impedance ground throughthe shaft or the load structure connected to the shaft [7]

4/ Circulating bearing currents (ia)The shaft voltage is due to asymmetry in the magnetic field from one end of the rotor to theother end of the rotor and is prevalent in long axial machines This asymmetry induces a shaftvoltage across the length of the rotor and is basically an electromagnetic induction

phenomenon opposed to the capacitive coupled phenomenon The induced voltage is of verylow frequency and depends on the fundamental excitation of the motor The circulating currentflows along the axis of the rotor, through the bearings and circulates through the stator frameand returns back from the other bearing end This current is generally not significant in smallpower AC machines less than 110 KW [7]

The bearing currents described above cause bearing damage, thereby shortening the lifeexpectancy of a motor Therefore, there are 4 main solutions to mitigate bearing currents.1/ Reduce or eliminate the common-mode voltage produced by Adjustable Speed Drive (ASD)[7]

2/ Reduce or eliminate the coupling action between the stator and rotor [7].3/ Provide a low impedance ground path to drain currents from the shaft [7].4/ Implement passive and/or active filtering to reduce CMV amplitude and CM dv/dt [7].The first method will be the main focus of the thesis, which involves in modifying PWMstrategies The second solution can be achieved by incorporating an electrostatic shield on thesurface of the stator Installing a shaft grounding brush, which is a hardware solution, can helpdrain shaft currents but adds additional cost and maintenance to the motor-drive system.Adding passive and/or active filters to the drive output or motor terminals is another hardwaresolution which will be explained in a subsequent section

Winding Voltage StressThe common-mode voltage causes premature insulation breakdown, leading to winding shortcircuits and inter-turn faults Most motors controlled with ASD have floating neutrals that areisolated from the ground [7] Hence, Vne is significant over the entire winding of motors ManyASDs now use IGBTs as the primary switching devices due to their high voltage/power rating, lowrise time and fast switching speeds This allows for a higher switching frequency in PWM VSIsthat produces a current waveform with lower harmonics and less audible noise in the motor [7].The trade-off of improved ASD efficiency due to low IGBT rise times comes from the interactionbetween the inverter, motor and cabling that can produce large overvoltages at the motorterminals reaching twice the DC bus voltage Moreover, pulses at the inverter outputs may occurprior to the decay of the reflected waves of previous pulses which can lead to overvoltagesexceeding twice the DC bus voltage Even more disastrous are polarity reversals of the line-to-line voltages resulting from two phase voltages simultaneously changing state Thesephenomena have been shown to lower the life of the motor insulation [7].

Electromagnetic Interference (EMI)Conducted EMI emissions caused by CMV/CMI are the major concern in ASD applications CMIscan flow through different ground paths, which may provoke unexpected behavior of nearbycontrol electronics, including the drive controller, encoders, ASD current sensors, etc [7] Theseeffects can be exacerbated if the power system impedance is high or if a high resistancegrounding scheme is employed [7] From a high frequency perspective, the CM dv/dt producedfrom the low switching times in ASDs contribute to EMI noise ranging from 535 kHz to 1.7 MHzin industrial applications [7] This waveform is ideal, whereas in realistic applications, the parasiticcapacitances in the cables and motors will cause high frequency ringing at each switchingtransition [7]

CMIs induced by CM dv/dt produced by ASDs can produce many unwanted effects in motor-drivesystems, including premature motor bearing failure, winding insulation breakdown, and EMI.CMIs are highest for motor-drive systems incorporating long cabling between the drive andmotor, high voltage/power motors with a high value of parasitic capacitance, and ASDs equippedwith low switch rise-times [7]

2.4 Solutions to Mitigate Common Mode Voltage in Three-Level Neutral Point Clamped

Inverters

In this section, methods of mitigating CMV including hardware and software solutions will bereviewed Although the focus of the thesis is on software solutions, specifically PWM strategies,it would be worthwhile to understand the strengths and weaknesses of the hardware solutionsand compare them with software solutions

2.4.1 Hardware Solutions to Mitigate Common-Mode Voltage

The first effective solution of mitigating the CMV is using an isolation transformer [8] A typicalconfiguration of a transformer is shown in Figure 8 with delta connection on the grid side andWYE connection on the other side The capacitive coupling of a motor and a transformer withrespect to the ground are Cmg and Cig, respectively The value of Cmg is approximately 150 timeslarger than Cig in medium voltage systems [8] Therefore, the CMV stress will be transferred fromthe motor to the secondary winding of the isolation transformer Although the CMV is mitigatedby this method, the shaft voltage and bearing current induced by CMV are not completelyaddressed [8] Moreover, an isolation transformer is bulky, costly, and also reduces the efficiencyof the system.

Utility Isolation ake ke

Supply Transformer | Motor

tk una

Harmonic Filter

Figure 8: An isolation transformer for CMV mitigation [8].The second method of reducing CMV is using CM choke The term choke in the phrase ‘CM choke’means to reduce or mitigate the common-mode voltage Before getting into the CM choke, let’sdiscuss types of noise in inverter-driven motors There are two kinds of noise, namely differentialmode noise (DM noise) and common-mode noise (CM noise) In the DM noise, the currentsflowing on the line and neutral have opposite direction, forms a closed loop and are shown asbelow:

Signal Strayki \ >> SS capacite

sả:

w

Reference ground surface

Figure 10: Common-mode (CM) noise [9].These 2 types of noise coexist in motor drive applications Therefore, mitigation methods areintroduced to reduce their effects In particular, in the DM noise, the LCL inductors are used,also known as DM chokes As far as the CM noise is concerned, the CM chokes are also utilized.In VSIs and CSIs, DM filters are present at DC-link of inverters as well as at motor side

Therefore, the CM chokes are usually integrated into DM chokes for the sake of convenienceand cost There are also 2 types of CM chokes One is DC CM choke and the other is AC CMchoke The term DC or AC refers to the position in which the chokes are placed in the topology.For example, DC CM choke is placed at the DC-link of an inverter, in particular the CSIs since theDM chokes are already present to smooth out the DC current As for VSIs, AC CM chokes areoften used and placed at the line side (AC side) Both DM and CM filtering features are usuallyintegrated into one choke (either DC or AC choke) The DC and AC choke are shown respectivelyin the figure below

Choke

Motor-Side EMIFilter (Optional)

achieve the desired differential and common-mode inductances With the configuration asshown in Figure 13, the common-mode inductance not only is produced by the common-modecoil C and D, but also is created by the differential coil A and B, thereby making the common-mode inductance substantially larger than differential inductance

Re —=R

Ned PC c2

Ae a ») Co he 2N DA Ne B\o—— D,o “a D B,—— >

Np D

D,o— 2

Figure 13: Integrated DC Choke [10].The working mechanism of an integrated AC choke is the same as the DC one, which is topresent an impedance to both differential current and common-mode current so as toeliminate them [11] The magnetic core of an integrated AC choke can be of circular, triangle, orhexagonal shape [11] The magnetic core having a circular shape is shown in Figure 14 The coreconsists of a periphery, three evenly distributed bridge legs, three-phase coils wounded on thedivided parts of the circumference in the same direction, and air gaps located in the center

Inductor Type

Comparable Index tae

Integrated Choke cactors

DM CMMax flux density (7) 0.8 (total): 0.1 (CM) 0.8 0.07Inductance (iH) 2.76 (DM): 101.4 (CM) 2.76 101.3

3.67 3.56Core weight (kg) 2.72

1/ an almost 40% drop in coil weight [11]2/ a 60% iron weight reduction [11]3/ a total weight decrease of 50% [11]The third method of reducing CMV is using a four-leg inverter, i.e adding an additional fourthleg (pole) in an inverter In a three-phase two-level inverter, it is impossible to produce a zerocommon-mode voltage unless a fourth leg is added to an inverter However, a three-level NPCinverter is capable of producing zero common-mode voltage without the addition of the fourthpole Therefore, a fourth pole is added into an inverter to balance the neutral point voltage[12] In a three-level NPC inverter, a fourth leg is connected to the neutral point through aninductor as shown in Figure 15.

¬ come ste’ ŒL k3 mae ĐöE0) Aes

line Âm ok the A CHỈ #

: ia : =} Hk Xsza : SE

" Di | hiền Sáo Riá kia EET ASUS IG Lá A8 EE BEGET Sons yaaa

thts ake : | VN — CN

yan risa} & SIA ; ou - A MT Mộ L, Che

CATH sa “AT Cec GE

Figure 15: A three-level NPC inverter with an addition of a fourth-leg [12].The fourth method of reducing/eliminating CMV is using dual-bridge inverters Dual-bridgeinverters consists of either 2 two-level inverters or 2 cascaded H-bridge inverters and aninduction motor connects to two inverters from its both ends as shown in Figure 16 and 17

a Tees AOR '|' vader Œ

s|IÐVOHCFẨ:: sỉ mà | S| tý Eš Ệ TH

Figure 16: Two 2-level Inverters connected to an Induction Motor with Open-End Windings [13].

Inverter A : i : : : Inverter B

CU ro age ge ag aeral Vdc/2 = ios ome , ,

} lín Ble CEs TÃ |i Bì tú đã tí ti tả BI mi li |5 Mã Eš fHh TÊM) Mi ane: qk eB rẻ cố he ee ec he

Titi : i |e : ¡ lý THỂ : | te : eI :

Figure 17: Two Cascaded H-bridge Inverter connected to an Induction Motor with Open-End

Windings [14].The common-mode voltage can be either eliminated (Vcm = 0) or reduced (usually to 1/6Vpc)depending upon the selection of the switching vectors [15][16][17][18] The CMV eliminationcomes at the expense of output quality and switching loss [8]

A fifth method of eliminating CMV is adding an auxiliary circuit The basic working of anauxiliary circuit is to add a compensatory voltage through a transformer in order to cancel outthe CMV, thereby resulting zero CMV [19] The typical topology of an auxiliary circuit is shown

output terminal of an inverter The complementary transistor Q: and Q2 operate in the linearregion Therefore, the emitter voltage of the transistors to the DC link mid-point (Veo) is equalto the detected CMV (Vno) and the CMV (Vao) The three secondary windings of the CMtransformer are connected in series between the inverter output and the load terminals.

Hence, the CMV of the induction motor drive system can be eliminated by addingcompensatory voltage for CMV to the primary winding of CMT [19]

For example, if the control purpose is to achieve superior output quality and high DC busutilization, the Space Vector Modulation (SVPWM) using Nearest Three Vector (NTV) is utilized.lf the control purpose is to minimize switching loss, the Discontinuous PWM is selected As forCMV mitigation, PWM strategies can be categorized into two groups, namely reduced CMV PWM(or partially eliminated CMV PWM) and eliminated CMV PWM In a three-level NPC inverter, areduced CMV PWM means the CMV is reduced to a certain voltage level with respect to DC-linkvoltage (Voc), i.e 1/6Vpc by avoiding some voltage vectors that cause high CMV In a two-levelinverter, a reduced CMV PWM means the CMV is reduced to 1/3Vpc by avoiding zero vectors Aneliminated CMV PWM in a three-level inverter means the CMV is zero by selecting voltage vectorsthat result in zero CMV However, there is a cost (or a penalty) in achieving either partiallyeliminated CMV or completely eliminated CMV The costs can be higher output current ripple,higher switching loss, and reduced DC-link utilization compared to a conventional SVPWMstrategy The high output current ripple is due to the fact that the partially and completelyeliminated CMV do not utilize the Nearest Three Vector (NTV) principle, which is known in theliterature as having superior output performance The high switching loss is caused by doublecommutation of two legs, i.e 2 phase legs of an inverter are switching simultaneously incompletely eliminated PWM methods The reduced DC-link utilization is the result of theexclusion of large vectors It is also worth noting that the dead-time effect should be taken intoaccount since some PWM methods for CMV mitigation without considering the dead-time(blanking-time) effect may not be working in real operating conditions

Both reduced and eliminated CMV PWM methods can be Carrier-based PWM or Space VectorPWM (SVPWM) By adding a proper offset, Carrier-based PWMs can reduce or eliminate the CMV[20] It has been well demonstrated in [23] [24] [25] [26] that the performance of Carrier-basedPWM is similar to that of SVPWM by adding a proper offset into original reference signals.Therefore, Carrier-based PWM is usually employed due to its simple implementation [26] Incarrier-based PWMs, a comparison is made among Phase Disposition PWM (PD-PWM), PhaseOpposition Disposition PWM (POD-PWM), and Alternate Phase Opposition Disposition (APOD-PWM) [21] The POD-PWM with offset has been shown to offer low CMV magnitude as well aslow CM dv/dt compared to other methods at the expense of higher THD in line-line voltage [21].In addition, a paper in [22] uses quad-carrier waves, which is the two additional waves are phase-shifted with respect to original ones by 180° It also shows that the CMV magnitude is reduced to1/6Vpc Therefore, in carrier-based PWMs, the CMV reduction/elimination usually involvesmodifying carrier arrangements and/or changing offset added into the reference signals As forSVPWM, it offers an intuitive insight into how the CMV magnitude is reduced or eliminated byobserving the voltage vector selection [18] This is due to the fact that the voltage vectors willdetermine the CMV magnitude Moreover, the transition from one voltage vector to the otherwill dictate the step height of CMV and the switching sequence in one sampling period will alsodetermine the number of CMV transitions In a three-level NPC inverter with diode front-end,the inverter-generated CMV, which is the voltage between the stator neutral of a motor (theneutral point of the load) and the neutral point of the inverter, is reduced to 1/6Vpc by avoidingcertain voltage vectors [18] Specifically, only 19 out of 27 voltage vectors are utilized to reduceCMV magnitude [18] The voltage vectors corresponding to the CMV magnitude (with respect toDC-link) are listed in the Table 3.

Voltage Vectors [Vom |Medium Voltage Vectors (1,0,-1) (0,1,-1) (-1,1,0) (-1,0,1) 0

(-1,0,1) (0,-1,1) (1,-1,0)Large Voltage Vectors (1,-1,-1) (1,1,-1) (-1,1,-1) Vpc/6

(-1,1,1) (-1,-1,1) (1,-1,1)Small Voltage Vectors (1,0,0) (0,1,0) (0,0,1) Vpc/6

(-1,0,0) (0,-1,0) (0,0,-1)(1,1,0) (1,0,1) (0,1,1) Vpc/3(-1,-1,0) (-1,0,-1) (0,-1,-1)

Zero Voltage Vectors (0,0,0) 0

(1,1,1) (-1,-1,-1) Vpc/2Table 3: CMV magnitude corresponding to each voltage vector [18].According to the Table 3, the reduced CMV PWM methods will avoid the voltage vectors, whichgenerate the CMV larger than Vpc/6 Similarly, the eliminated CMV PWM will only select voltagevectors that result in zero CMV

Most reduced/eliminated CMV PWMs in the literature do not take the NP voltage balancinginto account Although some papers attempt to reduce the CMV magnitude while balancing the

NP voltage [27] However, these two objectives, which are CMV reduction/elimination and NPvoltage balancing, are contradictory [27] This is due to the fact that some redundant states ofthe small vectors, which are helpful in balancing the NP voltage, have to be avoided in order tobring the CMV magnitude back into 1/6Voc This in turn offers less degree of freedom in

controlling the NP voltage imbalance The papers [27] [28] [22] in the literature try to eliminatethe CMV while taking the NP voltage balancing into account However, this is can be onlyachieved by adding an additional hardware to balancing the NP voltage Since there is nodegree of freedom left in order to balance the NP voltage in eliminated CMV PWMs In otherwords, all small vectors which are crucial in NP voltage balancing are avoided altogether.In this thesis, the CMI reduction is not the main focus However, the CMI flowing through thestray capacitance is directly affected by both the step height of a CMV pulse and the number ofCMV transitions over one carrier period [29][30] These two factors were already discussed inthe earlier section and will be used to evaluate the performance of each PWM strategy Byreducing these 2 factors, the CMI can be greatly decreased [29] The CMI is important becauseit causes conducted Electromagnetic Interference (EMI) The paper in [31] attempts to reducethe number of variations of CMV pulses in one switching period by combining the

Discontinuous PWM (PWM) and Double Commutations while taking the dead-time effect intoaccount Therefore, the number of variations of CMV pulse are 2 as opposed to 6 and 4 inSPWM and DPWM, respectively Since this is a reduced CMV PWM method, there are still somedegrees of freedom left in controlling the NP balancing However, the switching loss of thisstrategy is higher than that of SPWM or SVPWM because the double commutation is used Theeliminated CMV PWM methods theoretically have zero CMV magnitude as well as zero

variation of CMV pulse [32] [33] [34] Unfortunately, without the consideration of the time effect, unexpected CMV spikes appear in real applications [35]

dead-The term dead-time effect has been mentioned many times in the text and will be discussed indetail in this section In Power Electronics, the dead-time effect must be included for all

converters so as to avoid shoot-through (or short-circuit), which can damage the power devicesof the converters [35] The Figure 19 shows the transition from O state to P state in the PhaseLeg A of a three-level NPC Inverter The dead time is included in between two states

orange, lout < 0: blue) [35].

om alin nn Sig ee cee

compensation is not included, the CMV pulse will appear in eliminated CMV PWMs [35] Theprinciple of deadtime compensation proposed in the literature can be summarized as follows Ifthere are commutations between two legs having different current direction, there will be noCMV pulse Otherwise, the CMV pulse will appear if there are commutation between two legshaving same current direction Therefore, in dead-time compensation, commutations are onlyallowed in two legs having different current direction The impact of dead-time on CMV isshown in Figure 20 Some proposed eliminated CMV PWMs without dead-time compensationresult in zero CMV in Simulation However, in experimental results, unexpected CMV spikeoccurs due to the dead-time effect

Two problems related to both reduced CMV PWMs and eliminated CMV PWMs are high currentripple and switching loss compared to conventional SPWM and SVPWM [34][36] In recentyears, reducing the current ripple and switching loss are the topic of research when it comes toCMV control The papers in [34][37][2] attempt to achieve zero CMV magnitude with reducedcurrent ripple by selecting a proper switching sequence Other ones in [36][4] also try to reducethe switching loss by using DPWM, i.e clamping one leg into a certain voltage state (P, O, or N).