MEMORY, MICROPROCESSOR, and ASIC ppt

Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com MEMORY, MICROPROCESSOR, and ASIC Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com MEMORY, MICROPROCESSOR, and ASIC Editor-in-Chief Wai-Kai Chen CRC PRESS Boca Raton London New York Washington, D.C. Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com This edition published in the Taylor & Francis e-Library, 2005. To purchase your own copy of this or any of Taylor & Francis or Routledge’s collection of thousands of eBooks please go to www.eBookstore.tandf.co.uk. The material from this book was first published in The VLSI Handbook, CRC Press, 2000. Library of Congress Cataloging-in-Publication Data Memory, microprocessor, and ASIC / Wai-Kai Chen, editor-in-chief. p. cm. — (Principles and applications in engineering ; 7) Includes bibliographical references and index. ISBN 0-8493-1737-1 (alk. paper) 1. Semiconductor storage devices. 2. Microprocessors 3. Application specific integrated circuits. 4. Integrated circuits-Very large scale integration. I. Chen, Wai-Kai, 1936- II Series TK7895.M4V57 2003 621.38′5—dc21 2002042927 This book contains information obtained from authentic and highly regarded sources. Reprinted material is quoted with permission, and sources are indicated. A wide variety of references are listed. Reasonable efforts have been made to publish reliable data and information, but the authors and the publisher cannot assume responsibility for the validity of all materials or for the consequences of their use. Neither this book nor any part may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, microfilming, and recording, or by any information storage or retrieval system, without prior permission in writing from the publisher. All rights reserved. Authorization to photocopy items for internal or personal use, or the personal or internal use of specific clients, may be granted by CRC Press LLC, provided that $1.50 per page photocopied is paid directly to Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923 USA The fee code for users of the Transactional Reporting Service is ISBN 0-8493-1737-l/03/$0.00+$1.50. The fee is subject to change without notice. For organizations that have been granted a photocopy license by the CCC, a separate system of payment has been arranged. The consent of CRC Press LLC does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific permission must be obtained in writing from CRC Press LLC for such copying. Direct all inquiries to CRC Press LLC, 2000 N.W. Corporate Blvd., Boca Raton, Florida 33431. Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identification and explanation, without intent to infringe. Visit the CRC Press Web site at www.crcpress.com © 2003 by CRC Press LLC No claim to original U.S. Government works International Standard Book Number 0-8493-1737-1 Library of Congress Card Number 2002042927 ISBN 0-203-01023-X Master e-book ISBN Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com v Preface The purpose of Memory, Microprocessor, and ASIC is to provide in a single volume a comprehensive reference work covering the broad spectrum of memory, registers, system timing, microprocessor design, verification and architecture, ASIC design, and test and testability. The book is written and developed for practicing electrical engineers and computer scientists in industry, government, and academia. The goal is to provide the most up-to-date information in the field. Over the years, the fundamentals of the field have evolved to include a wide range of topics and a broad range of practice. To encompass such a wide range of knowledge, the book focuses on the key concepts, models, and equations that enable the design engineer to analyze, design, and predict the behavior of large-scale systems. While design formulas and tables are listed, emphasis is placed on the key concepts and theories underlying the processes. The book stresses the fundamental theory behind professional applications. In order to do so, it is reinforced with frequent examples. Extensive development of theory and details of proofs have been omitted. The reader is assumed to have a certain degree of sophistication and experience. However, brief reviews of theories, principles, and mathematics of some subject areas are given. These reviews have been done concisely, with perception. The compilation of this book would not have been possible without the dedication and efforts of Bing J.Sheu, Steve M.Kang and Nick Kanopoulos, and, above all, the contributing authors. I wish to thank them all. Wai-Kai Chen Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com vii Editor-in-Chief Wai-Kai Chen, Professor and Head Emeritus of the Department of Electrical Engineering and Computer Science at the University of Illinois at Chicago. He is now serving as Academic Vice President at International Technological University. He received his B.S. and M.S. in electrical engineering at Ohio University, where he was later recognized as a Distinguished Professor. He earned his Ph.D. in electrical engineering at University of Illinois at Urbana/Champaign. Professor Chen has extensive experience in education and industry and is very active professionally in the fields of circuits and systems. He has served as visiting professor at Purdue University, University of Hawaii at Manoa, and Chuo University in Tokyo, Japan. He was editor of the IEEE Transactions on Circuits and Systems, Series I and II, president of the IEEE Circuits and Systems Society and is the founding editor and editor-in-chief of the Journal of Circuits, Systems and Computers. He received the Lester R.Ford Award from the Mathematical Association of America, the Alexander von Humboldt Award from Germany, the JSPS Fellowship Award from Japan Society for the Promotion of Science, the Ohio University Alumni Medal of Merit for Distinguished Achievement in Engineering Education, the Senior University Scholar Award and the 2000 Faculty Research Award form the University of Illinois at Chicago, and the Distinguished Alumnus Award from the University of Illinois at Urbana/Champaign. He is the recipient of the Golden Jubilee Medal, the Education Award, and the Meritorious Service Award from IEEE Circuits and Systems Society, and the Third Millennium Medal from the IEEE. He has also received more than dozen honorary professorship awards from major institutions in China. A fellow of the Institute of Electrical and Electronics Engineers and the American Association for the Advancement of Science, Professor Chen is widely known in the profession for his Applied Graph Theory (North-Holland), Theory and Design of Broadband Matching Networks (Pergamon Press), Active Network and Feedback Amplifier Theory (McGraw-Hill), Linear Networks and Systems (Brooks/Cole), Passive and Active Filters: Theory and Implements (John Wiley & Sons), Theory of Nets: Flows in Networks (Wiley- Interscience), and The Circuits and Filters Handbook and The VLSI Handbook (CRC Press). Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com ix David Blaauw Motorola, Inc. Austin, Texas Kuo-Hsing Cheng Tamkang University Tamsui, Taipei Hsien, Taiwan Amy Hsiu-Fen Chou National Tsing-Hua University Hsinchu, Taiwan Daniel A.Connors University of Illinois Urbana, Illinois Abhijit Dharchoudhury Motorola, Inc. Austin, Texas Eby G.Friedman University of Rochester Rochester, New York Stantanu Ganguly Intel Corporation Austin, Texas Rajesh K.Gupta University of California Irvine, California Sumit Gupta University of California Irvine, California Contributors Charles Ching-Hsiang Hsu National Tsing-Hua University Hsinchu, Taiwan Jen-Sheng Hwang National Science Council Hsinchu, Taiwan Wen-mei W.Hwu University of Illinois Urbana, Illinois Vikram Iyengar University of Illinois Urbana, Illinois Dimitri Kagaris Southern Illinois University Carbondale, Illinois Nick Kanopoulos Atmel Multimedia and Communications Morrisville, North Carolina Tanay Karnik Intel Corporation Hillsboro, Oregon Ivan S.Kourtev University of Pittsburgh Pittsburgh, Pennsylvania Frank Ruei-Ling Lin National Tsing-Hua University Hsinchu, Taiwan Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com [...]... computational process in these systems to be spread over hundreds of thousands of functional logic elements and tens of thousands of registers Memory, Microprocessor, and ASIC 1-6 Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com For such synchronous digital systems to function properly, the many thousands of switching events require a strict temporal ordering This strict ordering... TCP and the delays of the clock FIGURE 1.13 Lead/lag relationships causing clock skew to be zero, negative, or positive * Note that these delays and are measured with respect to the same reference point Memory, Microprocessor, and ASIC 1-20 Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com FIGURE 1.14 A single-phase local data path signal Ci and Cf to the flip-flops Ri and Rf... Together, the combinational logic and registers constitute the computational * RISC=Reduced Instruction Set Computer ** Such quantities as the electical voltages and currents in the electronic devices 1-4 Memory, Microprocessor, and ASIC Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com FIGURE 1.2 A synchronous system portion of the synchronous system and are interconnected in a way... level-sensitive register 1-16 Memory, Microprocessor, and ASIC Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com Latch Setup Time The latch setup time =t6—t5, shown in Fig 1.9, is the minimum time between a change in the data signal and the trailing edge of the clock signal such that the new value of D would propagate to the output Q of the latch and be stored within the latch... defined as the minimum time between a change in the data signal and the latching edge of the clock signal such that the new value of D propagates to the output Q of the flip-flop and is successfully latched within the flip-flop FIGURE 1.11 Parameters of an edge-triggered register 1-18 Memory, Microprocessor, and ASIC Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com Flip-Flop... clock signal paths to the registers R5 and R9, respectively Note that the clock skew Tskew(i, f) between the sequentially adjusted pair of registers Ri Rf is equal to the difference between the accumulated buffer propagation delays between and that is, * Note that not all of the vertices correspond to registers Memory, Microprocessor, and ASIC 1-12 Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com... integrated circuits (ICs) were introduced in the 1960s 0–8493–1737–1/03/$0.00+$ 1.50 © 2003 by CRC Press LLC 1-1 1-2 Memory, Microprocessor, and ASIC Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com FIGURE 1.1 Moore’s law: exponential increase in circuit integration and clock frequency (From Rabaey, J.M., Digital Integrated Circuits: A Design Perspective, Prentice Hall, Inc., 1995.)... (or control) signal input FIGURE 1.7 A general view of a register 1-14 Memory, Microprocessor, and ASIC Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com The two major groups of storage elements (registers) are considered in the following sections based on the type of relationship that exists among the data and clock signals of these elements In latches, it is the specific value... Ci and Cj, respectively In Definition 1.3, the clock delays and are with respect to some reference point A commonly used reference point is the source of the clock distribution network on the chip Note that the clock skew Tskew (i,j) as defined in Definition 1.3 obeys the antisymmetric property (1.2) FIGURE 1.3 Graphs G and its underlying graph Gu of the graph N=5 registers Memory, Microprocessor, and. .. of buffers and interconnects Typically, a buffer in the network drives a combination of other buffers and registers in the VLSI circuit An *Equivalently, it is required that the clock signal arrive at each register at approximately the same time 1-10 Memory, Microprocessor, and ASIC Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com FIGURE 1.4 Tree structure of a clock distribution . Merge and Split Unregistered Version - http://www.simpopdf.com MEMORY, MICROPROCESSOR, and ASIC Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com Simpo PDF Merge and Split. design, verification and architecture, ASIC design, and test and testability. The book is written and developed for practicing electrical engineers and computer scientists in industry, government, and academia (Wiley- Interscience), and The Circuits and Filters Handbook and The VLSI Handbook (CRC Press). Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com Simpo PDF Merge and Split Unregistered