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Due to its powerful brainlike parallel computing and efficient data processing capabilities, memristors are considered to be the core components for building the next generation of artificial intelligence systems. In this study, the CeOxWOy heterojunction is employed as the functional layer, and various metal materials are utilized as the top electrode to fabricate the memristor. The results indicate that the memristive performance of the AgCeOxWOyITO device can be improved by using Ag as the top electrode. By studying the conductivity mechanism of the device, a conductivity model is established that regulates oxygen vacancies and Ag conductive filaments. Furthermore, using the asprepared memristor, it is constructed four basic digital logic circuits: OR, AND, XOR, and XNOR, as well as a half adder and a full adder that can be used for digital arithmetic operations. Specifically, an oddeven checker is developed based on XOR and XNOR logic circuits to verify the correctness of data transmission. Finally, it is also designed and implemented a cryptographic array based on a memristor, which can be applied to encrypt and decrypt a series of numbers and images. Therefore, this work extends the application of memristor toward digital circuits, information transmission, data processing and image security encryption.
RESEARCH ARTICLE www.afm-journal.de Logic Gate Circuits Based on CeOx/WOy Memristor for the Odd/Even Checker and Encryption/Decryption of Image Applications Jiangqiu Wang, Hongyan Wang,* Zelin Cao, Shouhui Zhu, Junmei Du, Chuan Yang, Chuan Ke, Yong Zhao, and Bai Sun* With the continuous development of artificial intelligence technology, the demand for computer processing energy efficiency is increasing.[1,2] Since the current computer based on the von Neumann architecture has independent storage and computing units, frequent data transmission between the central processing unit (CPU) and memory will lead to bottlenecks in information processing speed.[3,4] As a novel electronic device, the memristor is called the fourth basic circuit element whose internal conductive state depends on the history of electrons or ions.[5,6] These functions enable data to be processed in memory, making it a core component of brain-like computing architectures.[7–9] Generally, a memristor is a two-terminal device with a sandwich structure, in which an insulator or semiconductor is usually used as a functional layer, and a metal or conductive oxide is used as the top and bottom electrodes.[10–12] When a voltage is applied, the resistance state of the memristor can be switched between the high resistance state (HRS) and the low resistance state (LRS).[13] Up to now, many materials have been reported to be used as the functional layer of memristor, such as metal oxides, perovskite, ferroelectrics, 2D materials, organic materials, etc.[14–19] When different functional materials are used, the performance of the memristor varies greatly, which broadens the application range of memristors.[20] However, the diverse selection of materials also increases the difficulty of studying the mechanism of resistive J Wang, H Wang, S Zhu, J Du, C Yang, Y Zhao School of Physical Science and Technology Key Laboratory of Advanced Technology of Materials Southwest Jiaotong University Chengdu, Sichuan 610031, China E-mail: hongyanw@swjtu.edu.cn Z Cao, B Sun Frontier Institute of Science and Technology (FIST) Xi’an Jiaotong University Xi’an, Shaanxi 710049, China E-mail: baisun@xjtu.edu.cn Z Cao, B Sun Micro-and Nano-technology Research Center State Key Laboratory for Manufacturing Systems Engineering Xi’an Jiaotong University Xi’an, Shaanxi 710049, China C Ke, Y Zhao Key Laboratory of Magnetic Suspension Technology and Maglev Vehicle (Ministry of Education) School of Electrical Engineering Southwest Jiaotong University Chengdu 610031, China Due to its powerful brain-like parallel computing and efficient data processing capabilities, memristors are considered to be the core components for building the next generation of artificial intelligence systems In this study, the CeOx /WOy heterojunction is employed as the functional layer, and various metal materials are utilized as the top electrode to fabricate the memristor The results indicate that the memristive performance of the Ag/CeOx /WOy /ITO device can be improved by using Ag as the top electrode By studying the conductivity mechanism of the device, a conductivity model is established that regulates oxygen vacancies and Ag conductive filaments Furthermore, using the as-prepared memristor, it is constructed four basic digital logic circuits: OR, AND, XOR, and XNOR, as well as a half adder and a full adder that can be used for digital arithmetic operations Specifically, an odd/even checker is developed based on XOR and XNOR logic circuits to verify the correctness of data transmission Finally, it is also designed and implemented a cryptographic array based on a memristor, which can be applied to encrypt and decrypt a series of numbers and images Therefore, this work extends the application of memristor toward digital circuits, information transmission, data processing and image security encryption Introduction The ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/adfm.202313219 DOI: 10.1002/adfm.202313219 Adv Funct Mater 2024, 2313219 2313219 (1 of 13) © 2024 Wiley-VCH GmbH www.advancedsciencenews.com www.afm-journal.de switching (RS) characteristics RS characteristics are related to the functional layer material and its thickness, electrode material, and the environment of the device.[21–23] Among them, the most widely used functional layer material in the manufacture of memristors is binary metal oxides Many memristors based on binary metal oxides not only have excellent durability and retention advantages, but also are well compatible with current complementary metal oxide semiconductor (CMOS) devices, which can combine memristors with circuits and promote large-scale and high-density integration of memristors.[24,25] In recent years, the memristor based on the rare earth metal oxide cerium dioxide (CeO2 ) has attracted much attention due to its unique performance.[26–29] CeO2 is a typical n-type semiconductor, of whose main crystal defect is oxygen vacancy, and plays an important role in memristive devices CeO2 has a high dielectric constant (≈26), which has good application prospects in nonvolatile memory and neuromorphic computing.[30,31] However, the preparation of a memristor based on CeO2 still has some problems, such as it is difficulty in controlling the distribution of cerium cation and oxygen vacancy in CeO2 film, large formation voltage, small resistance window, and large operating current Yan et al used BaTiO3 /CeO2 thin films to prepare a silicon-based memristor with epitaxial vertically arranged nanostructures, which can achieve five state storage function and a durability of up to 109 cycles.[32] Further, the convolutional neural network was built based on the device to identify the CIFAR-10 dataset, and the recognition rates of online and offline learning reached 90.03% and 92.55% respectively Zhou et al prepared a photoelectric memristor with two terminal structures based on CeOx /ZnO heterostructure, and tested its recognition, storage, and processing under visible light of 405 nm, indicating that it has great potential applications in artificial vision systems.[33] In addition, Yang et al.[34] prepared a memristor device with Ag/TiOx /CeOy /FTO structure, in which it was found that the device shows volatile at low voltage, but it shows nonvolatile memory behavior at high voltage with typical memristive characteristics accompanied by negative differential resistance effect in the range of 3.5–4.0 V Therefore, in the above works, the performance of the memristive devices has been significantly improved by introducing a double-layer heterostructure due to the interface interaction formed by different material layers In this work, a memristor with a two-terminal structure was prepared based on the CeOx /WOy bilayer heterojunction as a functional layer by magnetron sputtering, which shows a digital RS behavior with outstanding durability and retention characteristics By fitting the I–V curves in a double logarithmic form, it can be proposed that the mechanism of RS characteristics of the Ag/CeOx /WOy /ITO device should be attributed to space-chargelimited current (SCLC) and Schottky emission In addition, four basic OR, AND, XOR, and XNOR digital logic circuits were constructed, as well as half-adders and full-adders that can be applied to digital arithmetic operations Further, we also developed an odd/even checker based on the XOR and XNOR logic circuits to verify the correctness of data transmission Finally, a memristorbased cryptographic array was constructed and implemented for encrypting/decrypting digital strings and images These results expand the applications of memristors in the fields of information transmission and data security encryption Adv Funct Mater 2024, 2313219 Results and Discussion In this work, a memristor with the Ag/CeOx /WOy /ITO structure was fabricated The photograph of the as-prepared memristive device is shown in Figure 1a, and the structural model of the device and the schematic diagram of the electrical testing process are shown in Figure S1a (Supporting Information) To further understand the thickness of the device, the cross-sectional scanning electron microscope (SEM) image confirms the thickness of the CeOx /WOy layer is ∼232 nm in Figure 1b, in which it can be seen that the functional film in the SEM image was deposited with CeOx and WOy bilayer films The surface of CeOx /WOy bilayer film was dense and crack-free as exhibited in Figure S1b (Supporting Information) Figure S2 (Supporting Information) shows the different elemental distributions in the CeOx /WOy film, and the energy dispersive spectroscopy (EDS) spectrum confirms the content of the O, W, and Ce elements is ≈71.16%, 10.69%, and 18.16% in Figure 1c Besides, the X-ray diffraction (XRD) analysis was performed to determine the structure and composition of the functional layer of the device The XRD spectrum featured in Figure 1d shows intensive peaks attributed to ITO and CeO2 , while the WO3 (200) crystal plane is represented by a peak at 33.6° The crystal structures of CeO2 and WO3 are shown in Figure S1c (Supporting Information), where the red balls represent O atoms, the yellow balls represent Ce atoms, and the green balls represent W atoms In particular, the X-ray photoelectron spectroscopy (XPS) was used to analyze the chemical composition and surface chemical states of bilayer films made of CeOx and WOy , and the survey spectrum of the CeOx film is depicted in Figure S1d (Supporting Information) The XPS spectrum displays the presence of C, Ce, and O elements, in which C elements can be classified as carbon-based contaminants Figure 1e displays the XPS spectra for the O 1s core level of thin films in CeOx At 530.29 eV, the fitted peak is assigned to lattice oxygen that is present in CeOx At the same time, the other peak at 531.55 eV is attributed to nonlattice oxygen, indicating the existence of oxygen vacancy defects in the CeOx layer As shown in Figure 1f, the XPS spectra of Ce 3d core level of thin films in CeOx According to the XPS spectra, it can be seen that the Ce element in the films is divided into two valence states of Ce4+ and Ce3+ ions The survey spectrum of the WOy film is illustrated in Figure S1e (Supporting Information), revealing the existence of C, W, and O elements within the XPS spectrum, in which C elements can be classified as carbon-based contaminants Figure 1g illustrates the XPS spectra of the O 1s core level in WOy films, in which the peak of 531.15 eV is associated with lattice oxygen, specifically in WOy The other peak with a binding energy of 531.91 eV is related to non-lattice oxygen and corresponds to oxygen vacancy defects in the WOy layer The XPS spectra of the W 4f core level in the WOy thin film are shown in Figure 1h According to the XPS spectra, three characteristic peaks at 36.02, 38.24, and 42.05 eV of the binding energy can be observed, which correspond to W 4f7/2 , W 4f5/2, and W 4f3/2 , respectively In addition, ultraviolet photoelectron spectroscopy (UPS) was used to measure the work function of CeOx and WOy The energy spectra of the measurements are shown in Figure 1i with an applied bias voltage of −10 V The fitting process produced the work functions of CeOx and WOy to be 4.295 and 3.33 eV, respectively 2313219 (2 of 13) © 2024 Wiley-VCH GmbH www.advancedsciencenews.com www.afm-journal.de Figure a) Photograph of the as-prepared memristive device b) The cross-section SEM image of the device c) EDS analysis of the CeOx /WOy film with the ITO electrode d) XRD pattern of CeOx /WOy /ITO film High-resolution XPS spectra and fitted spectra of e) O 1s and f) Ce 3d for the CeOx film High-resolution XPS spectra and fitted spectra of g) O 1s and h) W 3d for the WOy film i) The work functions of active layer CeOx and WOy measured using UPS In order to investigate the effect of different electrodes on the performance of the memristor, ITO was used as the bottom electrode, CeOx /WOy heterojunction as the functional layer of the memristor, and Ag, Ti, and TiN were selected as the top electrodes First of all, the semi-logarithmic I–V curves with 200 cycles of the Ag/CeOx /WOy /ITO memristor at ±2 V is shown in Figure 2a, in which it can be found that the memristive performance is stable To explore the durability of the device, the HRS and LRS resistance values of the device were tested at an applied voltage of −0.1 V, as shown in Figure 2b We can observe that the HRS and LRS resistance values of the memristor remain stable as the number of cycles increases, indicating that the device has excellent endurance characteristics The HRS/LRS resistance ratio of the device can achieve ≈16, which also remains stable with Adv Funct Mater 2024, 2313219 the increasing of cycle number Further, the retention characteristics of the device were investigated, as shown in Figure 2c, and the results show that the retention performance is satisfactory within 104 s Subsequently, the semi-logarithmic I–V curves of the Ti/CeOx /WOy /ITO memristor is plotted in Figure 2d The memristive performance of the device can be seen from the I–V curve that the first 60 cycles are stable and the last 20 cycles show a jumping phenomenon The HRS and LRS resistance value of the device were measured at −0.1 V to investigate the durability of the device in Figure 2e, in which the HRS and LRS resistance values of the device showed a simultaneous increase in the vicinity of 60 cycles and the stability decreased The HRS/LRS resistance ratio of the device is ∼1, and its value also shows small 2313219 (3 of 13) © 2024 Wiley-VCH GmbH www.advancedsciencenews.com www.afm-journal.de Figure a) Semi-logarithmic I–V characteristic curves of the device when Ag was used as the top electrode b) Corresponding resistance value of the device at the HRS and LRS and the HRS/LRS resistance ratio c) Retention characteristics of the corresponding device d) Semi-logarithmic I–V characteristic curves of the device when Ti was used as the top electrode e) Corresponding resistance value of the device at the HRS and LRS and the HRS/LRS resistance ratio f) Retention characteristics of the corresponding device g) Semi-logarithmic I–V characteristic curves of the device when TiN was used as the top electrode h) Corresponding resistance values of the device at the HRS and LRS and the HRS/LRS resistance ratio i) Retention characteristics of the corresponding device fluctuations in the later part of the cycle, which indicates the weak durability of the device The retention characteristics of the device were further explored, as shown in Figure 2f, which show that both the resistance values of the HRS and LRS increase with time within 103 s Finally, the semi-logarithmic I–V curve of the TiN/CeOx /WOy /ITO memristor is shown in Figure 2g It is evident that the I–V curves changed during the cycling process In order to assess the durability of the device, we conducted tests to measure the HRS and LRS resistance values at an applied voltage of −0.1 V, and the results are shown in Figure 2h The HRS resistance value of the device has a high dispersion in the first 50 cycles, and the LRS resistance value shows an abrupt decrease of resistance in the 10th cycle The HRS/LRS resistance ratio of the device is ≈2, and the resistance value shows small Adv Funct Mater 2024, 2313219 fluctuations, indicating that the device is relatively unstable The retention characteristics of the device were further explored, as shown in Figure 2i, and the results show that the device has a small fluctuation within 103 s Based on the experimental results presented above, the performance of memristor devices using Ag as the top electrode shows significant improvement compared to devices using Ti and TiN as the top electrode The memristor based on Ag electrode not only exhibits a high resistance ratio, but it also exhibits excellent durability and retention performance In order to test the RS performance of the as-prepared Ag/CeOx /WOy /ITO device in depth, the I–V curve with 100 cycles was obtained at the operating voltage sequence of → +2 V → → -2 V → 0, as shown in Figure 3a By testing the Ag/CeOx /WOy /ITO memristor, it can be observed that the de- 2313219 (4 of 13) © 2024 Wiley-VCH GmbH www.advancedsciencenews.com www.afm-journal.de Figure a) I–V curves of the Ag/CeOx /WOy /ITO device under applied voltage of ±2 V b) Corresponding semi-logarithmic I–V curves c) I–V curves of the device under different bias voltage scan rates d) Comparison of HRS and LRS of the device under different bias voltage scan rates and the HRS/LRS resistance ratio e) I–V curves of the device under different voltage amplitude f) Comparison of the HRS and LRS of the device under different voltage amplitude and the HRS/LRS resistance ratio vice has a typical bipolar RS behavior, and a typical I–V curve was taken to obtain a semi-logarithmic curve in Figure 3b, which clearly shows the SET and RESET process When a positive voltage scan (0 → +2.0 V) is applied to the device, the SET behavior will occur ≈+1.0 V, and the device can be switched from HRS to LRS When the scan voltage direction was changed (+2.0 V → 0), the device remained LRS until it entered the negative voltage region When a negative voltage sweep (0 → −2.0 V) was applied, the RESET behavior occurs ≈−1.6 V, which lend that the device can be switched from LRS to HRS, and then the sweep voltage direction changes (−2.0 V → 0), but the device can still remain at HRS until it enters the positive voltage region again To further explore the RS performance of the Ag/CeOx /WOy /ITO memristor, we investigated the effect of different bias voltage scan rates on the performance of the memristor The I–V curves are shown in Figure 3c when the bias voltage scan rate is 0.2 0.4, 0.6, 0.8, 1.0, and 1.2 V s−1 under an applied voltage of ±2 V In the process of increasing the bias voltage scan rate from 0.2 V s−1 to 1.2 V s−1 , the resistance value of LRS is almost unchanged, while the resistance value of HRS first decreased and then increased, and the HRS/LRS resistance ratio reached the maximum value of ≈16 when the bias voltage scan rate was 0.2 V s−1 , as shown in Figure 3d The RS characteristics can be attributed to the effect of electron trapping/de-trapping duo on the interface defects At a low bias voltage scan rate, the injected electrons have enough time to complete the trapping/de-trapping process.[35,36] However, at a high bias voltage scan rate, the injected electrons may be not have enough time to complete the trapping/de-trapping process, Adv Funct Mater 2024, 2313219 which causes the resistance value of the HRS to first decrease and then tend to increase It indicates that the bias voltage scan rate has a threshold value for the motion of the injected electrons, which affects the motion of the electrons when the bias voltage scan rate is greater than the threshold value Therefore, the HRS/LRS resistance ratio of the device also varies with the bias voltage scan rate Naturally, the different voltage amplitude was applied to the memristor, which were ±0.5, ±1.0, ±1.5, ±2.0, ±2.5, and ±3.0 V, as shown in Figure 3e The I–V curves under different voltage amplitude show that the SET and RESET voltages of the device gradually increase with the increases of applied voltage amplitude, indicating that the threshold voltage of the memristor depends on the applied voltage amplitude As shown in Figure 3f, the HRS/LRS resistance ratio of the Ag/CeOx /WOy /ITO memristor also varies under different voltage amplitude, and the HRS/LRS resistance ratio of the device increases continuously with the increase of applied voltage amplitude When a voltage amplitude of ±3 V was applied to the device, the HRS/LRS resistance ratio reached a maximum value of 20 Furthermore, the resistance value of the HRS increased with the increase of voltage amplitude, while the resistance of the LRS decreased and then stabilized This indicates that the voltage amplitude affects both the resistance values of HRS and LRS In conclusion, the RS performance of the device was found to be influenced by variations in voltage amplitude and voltage scan rates This suggests that both the bias voltage scan rate and the applied voltage amplitude can have an impact on the RS performance of the device 2313219 (5 of 13) © 2024 Wiley-VCH GmbH www.advancedsciencenews.com www.afm-journal.de Figure a) The semi-logarithmic I–V curve of the device b,c) The I–V curve on log(I)–log(V) scale in the positive voltage region d) The I–V curves on a log(I)–log(V) scale in the negative voltage region e) The Schottky emission is fitted to the I–V curve in the negative voltage region f) Schematic energy band diagram of Schottky emission Eventually, to determine whether the device can maintain its ability to operate effectively under various temperature conditions, the RS performance was evaluated at different temperatures As shown in Figure S3a (Supporting Information), the I– V curves of the device were tested at a voltage amplitude of V with the temperature range from 300 to 380 K The results show that the RS performance remains stable at 300, 320, and 340 K When the temperature reaches 360 K, the RS performance of the device begins to degrade In particular, the RESET characteristic of the device disappears at 380 K As shown in Figure S3b (Supporting Information), the resistance values of HRS and LRS of the device increase to varying extents as the temperature continues to increase The HRS/LRS resistance ratio exhibits a pattern of initially increasing and then decreasing, and the HRS/LRS resistance ratio reaches a peak of 34 at 340 K This phenomenon can be attributed to the influence of electron trapping and detrapping on interfacial defects As the temperature increases, the injected electrons are accelerated to complete the trapping/detrapping process When the temperature exceeds the threshold of 360 K, it damages the internal structure of the device, leading to a decline in RS performance To further analyze the charge transport mechanism of the Ag/CeOx /WOy /ITO memristor, a typical semi-logarithmic I–V curve is selected, as shown in Figure 4a, in which the one-cycle I–V curve was divided into four parts and used different conduction models to fit the I–V curves under different voltage ranges At first, a double logarithmic linear fitting of the I–V curve in the positive region of V → +2 V, as shown in Figure 4b The slopes of the linear fitting in the V → +2 V region are ≈1.04,≈1.63, Adv Funct Mater 2024, 2313219 ≈11.9, and ≈1.3, respectively, indicating that the SCLC mechanism dominates the fitting results in this region In addition, a double logarithmic linear fitting of the I–V curve in the positive region of +2 V → V, as shown in Figure 4c The slopes of the linear fitting in the +2 V → V region is ≈1.03, which shows the Ohmic conduction mechanism is consistent with that in this range The above results show that the charge transfer characteristics of the device in the positive voltage region are dominated by the SCLC mechanism The SCLC mechanism is induced by electron injection from ohmic contacts, which is associated with the trapping and separation of carriers in the functional layer.[37,38] The SCLC mechanism can be described as follows:[39,40] JSCLC = V2 𝜀 𝜇𝜃 i d3 (1) where ℇi is the permittivity, μ is the carrier mobility, 𝜃 is the free and shallow trapped charges ratio, and d is the thickness of the dielectric layer After that, the I–V curve was fitted with a double logarithm in the negative voltage region, as shown in Figure 4d, and the slopes are 1.06 and 0.96 in the voltage regions of V → -1 V and -2 V → V, respectively, which is conformed to Ohmic conductance As shown in Figure 4e, in the high voltage region of -1 V → -2 V, there is a RESET process of the resistance state from LRS to HRS, which is fitted with the Schottky emission model and the result shows a slope of 3.04 in this region The fitting results indicate that the conduction behavior is consistent with Schottky emis- 2313219 (6 of 13) © 2024 Wiley-VCH GmbH www.advancedsciencenews.com www.afm-journal.de Figure a) Band schematic diagram of the Ag/CeOx /WOy /ITO structure b) Energy band diagram of the CeOx /WOy heterojunction c) Conductive filament model of the device sion, suggesting that some electrons are trapped by oxygen vacancies during conduction This can be described as follows:[41,42] ⎡ ⎢ −q J = A∗ T exp ⎢ ⎢ ⎣ A∗ = ( B − ) ⎤ qV∕4𝜋𝜀r 𝜀0 d ⎥ ⎥ KT ⎥ ⎦ √ 4𝜋qk2 m∗ 120m∗ = m0 h (2) (3) where J is the current density, A* is the effective Richardson constant, m0 is the free electron mass, m* is the effective electron mass in the dielectric layer, T is the absolute temperature, q is the electronic charge, ΦB is the Schottky barrier height, k is the Boltzmann’s constant, h is the Planck’s constant, ℇ0 is the permittivity in a vacuum, and ℇr is the optical dielectric constant, V is applied voltage, and d is the Schottky conduction distance After excluding the constant parameter in Equation (2), the equation can be regarded as ln(J) is linear to V½ , so the Schottky barrier plays an important role in the metal-semiconductor contact Figure 4f shows a band schematic diagram of Schottky emission In summary, the fitting analysis results of the I–V curve show that the charge transport mechanism of the device can be explained by the SCLC mechanism and Schottky emission The energy band structure of the Ag/CeOx /WOy /ITO memristor is depicted in Figure 5a, illustrating that the work functions of ITO and Ag electrodes are 4.8 and 4.26 eV, respectively The en- Adv Funct Mater 2024, 2313219 ergy bands of CeO2 and WO3 are 3.2 and 2.7 eV, respectively.[43–46] As a result of the UPS data in Figure 1i, the work functions of CeOx and WOy are 3.33 and 4.295 eV, respectively When two functional materials contact between CeO2 and WO3 , electrons flow from CeO2 with a higher Fermi energy level to WO3 with a lower energy level, which bends the energy band at the interface between the two materials until the Fermi energy level can reach equilibrium Finally, an electron depletion layer is formed on the contact surface of CeO2 , and an electron accumulation layer is formed on the contact surface of WO3 The interface is modulated by an applied electric field, which in turn affects the conductivity of this heterojunction, so that the devices can realize mutual transitions between HRS and LRS The n–n heterojunction is formed on the contact surface, as shown in Figure 5b, which leads to the change of the conductivity In the initial state, due to the formation of a heterojunction barrier to electronic transport having obvious blocking effect, this memristor exhibits HRS When the positive voltage applied to the device is gradually increased to the threshold voltage, oxygen vacancies are accumulated at the heterojunction interface, causing the heterojunction conductivity to increase dramatically, so that the resistance state of the memristor is switched from HRS to LRS When a negative voltage is applied to the device, the oxygen vacancies gradually migrate back to the initial state under the action of the electric field, causing the heterojunction also to gradually return to the initial state, and the resistance state of the device is switched from LRS to HRS again Therefore, by modulating the band structure of the heterojunction, the HRS and LRS 2313219 (7 of 13) © 2024 Wiley-VCH GmbH www.advancedsciencenews.com www.afm-journal.de of the memristor can be switched, which makes the device shows an excellent RS effect To further elaborate on the above explanation, a co-modulated conducting filament model by Ag and oxygen vacancies is developed to explain the RS performance of the Ag/CeOx /WOy /ITO memristor, as depicted in Figure 5c A representative I–V curve is chosen, which can be divided into four parts When no voltage is initially applied to the device, the resistance state is HRS When a positive voltage is applied to the top electrode of the device, the Ag atoms are first ionized to produce Ag+ ions Due to the low mobility of Ag+ ions in metal oxides, the electron gain reaction occurs near the anode, producing Ag atoms that aggregate at the anode to form Ag conductive filament, so that the Ag conductive filament grows from the anode to the cathode The reaction process is as follows:[47,48] Ag → Ag+ + e− (4) Ag+ + e− → Ag (5) At the same time, under the action of an electric field, reduction reactions occur in the oxygen atoms within the functional layer, leading to the generation of a large number of oxygen vacancies The oxygen vacancies generated will carry a positive charge due to the loss of electrons and will dynamically migrate to the cathode The cathode will continue to accumulate a large number of oxygen vacancies and form oxygen vacancy conductive filaments As a result, the oxygen vacancy conductive filaments grow from the cathode to the anode The process of oxygen vacancy generation is as follows:[49] O + 2e− → V2+ + O2− o (6) From the I–V curve, it can be inferred that the cathodic oxygen vacancy (Vo 2+ ) conducting filament and the anodic Ag conducting filament may be connected at the interface, forming a conducting channel between the top and bottom electrodes, making the resistance state can be switched from HRS to LRS When the direction of the applied electric field is reversed, the oxygen vacancy will combine with O2− ions, causing the conductive filament formed by the oxygen vacancies to break The reaction is as follows: → O + 2e− O2− + V2+ o (7) At the same time, the Ag conductive filament in the top electrode region loses electrons to form Ag+ ions These reactions lead to the rupture and dissolution of the oxygen vacancy and Ag conductive filament inside the CeOx /WOy functional layer, resulting in the resistance state of the device can be switched from LRS to HRS Therefore, we use the model of oxygen vacancy and Ag conducting filament to describe how the resistance state of the device can be switched between HRS and LRS This model provides a reasonable explanation for the RS behavior of the device The memristor with an Ag/CeOx /WOy /ITO structure exhibits excellent digital RS characteristics, allowing the resistance states of the device to transition between HRS and LRS under the applied electric field The variable conductivity of a memristor al- Adv Funct Mater 2024, 2313219 lows for its combination with other electronic devices in logic computation, information security transmission, and information encryption/decryption processing First of all, by connecting two memristors in forward parallel with terminals A and B as inputs and terminal Y as output, as shown in Figure 6a, thus an OR logic gate circuit is designed.[50] The OR logic gate circuit is constructed and simulated using the Simulink module of MATLAB The memristor parameters are configured to match those obtained from the Ag/CeOx /WOy /ITO memristor experiment, with the LRS set to 30 Ω and the HRS set to 480 Ω During the simulation, the input has a high level of 10 V and a low level of 0.1 V The output voltage is considered low if it is smaller than V and high if it is higher than V The simulation results of the OR gate circuit are depicted in Figure S4a (Supporting Information) The results indicate that the output low level is 0.1 V when both inputs are 0.1 V In all other cases, the output is at a high level The simulation results align with the truth table of the OR logic circuit The histogram generated from the simulation results is depicted in Figure 6b, illustrating that the OR logic can be achieved by connecting two memristors in parallel in the forward direction Then, an AND logic gate circuit was constructed using two memristors connected in reverse parallel, as illustrated in Figure 6c The AND logic gate circuit was simulated, and the simulation results are depicted in Figure S4b (Supporting Information) The output is 10 V when both inputs are 10 V; otherwise, the output is less than V A comparison of the simulation results with the truth table of the AND gate reveals that they exhibit the same logical relationship The histogram generated from the simulation results is depicted in Figure 6d, indicating that the circuit constructed by reversing the parallel connection of two memristors is capable of implementing an AND logic gate In addition, XOR and XNOR logic gate circuits can be designed by integrating the memristor with CMOS inverters.[51] As depicted in Figure 6e, the XOR logic gate circuit was created using a combination of four memristors and two CMOS inverters I1 and I2 are CMOS inverters The input of I1 and I2 is the output of an AND logic circuit The top terminal of I1 is connected to the output of an OR logic circuit, and the bottom terminal of I2 is connected to a low level The output is an XOR logic The XOR logic gate circuit can be simulated, and the simulated output can be seen in Figure S4c (Supporting Information) The output is 9.41 V when the two input voltages are different, but it is below V in other cases The comparison of the simulation results with the XOR truth table demonstrates that the logical relationship is consistent The histogram image from the simulation results is depicted in Figure 6f, indicating that the circuit, constructed using a combination of memristor and CMOS inverter, is capable of implementing the XOR logic gate Finally, the XNOR logic gate circuit was designed using a combination of four memristors and two CMOS inverters, as shown in Figure 6g When Vcc is set to 10 V, the inputs of I1 and I2 are connected to the outputs of the OR logic circuit The top terminal of I1 is linked to Vcc , and the bottom terminal of I2 is connected to the output of the AND logic circuit As a result, the circuit produces the output of an XNOR logic gate The XNOR logic gate circuit was simulated, and the results are depicted in Figure S4d (Supporting Information) The simulation indicates that the output is 10 V when the two input voltages are the same, and in all other cases, the output is below V A comparison of the simulation results with 2313219 (8 of 13) © 2024 Wiley-VCH GmbH www.advancedsciencenews.com www.afm-journal.de Figure Logic gate circuits based on memristor a) Schematic diagram of OR gate circuit b) Histogram of the simulation results of the OR gate circuits c) Schematic diagram of AND gate circuit d) Histogram of the simulation results of the AND gate circuit e) Schematic diagram of XOR gate circuit f) Histogram of the simulation results of the XOR gate circuit g) Schematic diagram of XNOR gate circuit h) Histogram of the simulation results of the XNOR gate circuit i) Schematic diagram of half adder circuit j) Histogram of the simulation results of the half-adder circuit k) Schematic diagram of full adder circuit l) Histogram of the simulation results of the full adder circuit the XNOR truth table confirms the consistency of the logic relationship The histogram image from the simulation results is presented in Figure 6h, demonstrating that the circuit, created by combining memristors and CMOS inverters, is capable of implementing the XNOR logic gate In addition to the construction of logic operation circuits, memristors can also be used in digital circuits for the construction of arithmetic operation circuits On the basis of the implementation of the four basic logic gates OR, AND, XOR, and XNOR, the adder can be further built.[52] When two one-bit binary numbers are added together without taking into account the input of the lower bit, it is believed to be a half-add operation A circuit that implements the half-add operation becomes a half-add circuit A half-add circuit is formed by parallel AND and XOR logic circuits, as shown in Figure 6i, in which S is the summation of the sums and C is the supply to the higher bit The circuit was built and simulated in MATLAB, as shown in the table of Figure S5a (Supporting Information) Comparing the results with the half-adder truth table, it shows that the device can perform half-adder operations The histogram obtained from the simulation results is shown in Figure 6j, which indicates that the circuit built by paralleling two AND and XOR memristor-based logic circuits can perform semi-additive logic operations Binary summation involves adding two corresponding addends and the three input digits in the lower order This operation Adv Funct Mater 2024, 2313219 is known as full addition, and the circuit is referred to as a full adder Figure 6k depicts the schematic of the full adder circuit The device comprises two half-adders and an OR logic circuit Here, CI represents the input from the lower bit, S represents the sum of the sums, and CO represents the input to the higher bit The full adder circuit was simulated, and the simulation results are presented in the table in Figure S5b (Supporting Information) A comparison of the results with the full adder truth table demonstrates that the device is capable of performing full adder operations The histogram image of the simulation results is displayed in Figure 6l, indicating that the circuit, constructed with two half adders and two OR logic circuits, is capable of performing full additive logic operations The accuracy of the simulated digital circuits was confirmed by comparing the logic results of the simulation with the truth table of the corresponding circuits The results of the comparison show that the constructed circuits are fully capable of implementing digital logic operations and digital arithmetic operations In addition, the memristor-based logic circuit can significantly reduce the number of components and power consumption compared to traditional digital logic circuits It also offers improved circuit versatility and cascading characteristics In digital electronic devices, a large number of binary digits, consisting of “0” and “1” are used to transmit information At the same time, in data transmission or digital communication, errors 2313219 (9 of 13) © 2024 Wiley-VCH GmbH www.advancedsciencenews.com www.afm-journal.de Figure a) Schematic diagram of odd checker circuit b) Schematic diagram of even checker circuit c) Histogram of the simulation results of the odd checker circuits d) Histogram of the simulation results of the even checker circuits may occur in the transmission of binary information due to the presence of noise and interference An odd/even checker can verify whether errors occur in the transmission of information.[53] The parity of “1” in a set of binary codes is determined by using odd numbers, known as an odd checker, and similarly using even numbers, known as an even checker In this study, an odd/even checker was constructed using memristors to verify the parity of the data Additionally, four-bit odd and even checkers were created using the constructed logic gate circuit First, a four-bit odd check device was constructed using three XOR logic gates The circuit diagram of the device is illustrated in Figure 7a, with A, B, C, and D representing the input terminals and Y representing the output terminal If the four input ports contain an odd number of 10 V inputs, the Y output will be at a high level; otherwise, it will be at a low level A simulation of the odd-checker circuit was conducted, and the simulation results are depicted in Figure S6b (Supporting Information) A comparison of the simulated results with the truth table for odd-check in Figure S6a (Supporting Information) shows that the two logic results are identical As depicted in Figure 7c, the simulation results are presented in a histogram The histogram illustrates that the odd number checker, constructed using memristors, can successfully perform the odd number check on the four input digits Then, three XNOR logic gates were used to construct a fourdigit even number checker that verifies whether the number of “1” in the input code is even Figure 7b illustrates the circuit principle of the even number checker If the number of “1” in the input code is even, the Y terminal input will be high when the num- Adv Funct Mater 2024, 2313219 ber of “1” for A, B, C, and D is even, and the output will be low in other cases The four-bit even checker circuit was simulated, and the results of the simulation are depicted in Figure S6b (Supporting Information) A comparison of the simulated results with the truth table in Figure S6a (Supporting Information) reveals that their logical outcomes are identical The simulation results were presented in a histogram in Figure 7d, demonstrating that the memristor-based even checker is capable of verifying four-bit even numbers Therefore, this memristor-based parity check circuit is useful for design purposes, and it can effectively ensure the accuracy of data during information transmission Nowadays, it is very important to ensure the security of information during the process of transmission Therefore, there is a high demand for information encryption in various security fields, including high-end technology, confidential correspondence, military, and national defense Software-based data encryption methods are vulnerable to external attacks that can lead to data leakage Therefore, the development of data encryption methods using physical hardware is essential for ensuring the security of information transmission.[54] In this study, a physical hardware-based encryption matrix system utilizing full adders is designed First, a full adder circuit based on a memristor is designed and implemented to create a cryptographic unit As shown in Figure 8a, where V represents the original image input, K and J are the inputs for key and key 2, respectively, and S is the output of the encrypted image Then, using the constructed encryption unit as a basis, an m × n array of encryption units is designed, in which this array can encrypt 2313219 (10 of 13) © 2024 Wiley-VCH GmbH www.advancedsciencenews.com www.afm-journal.de Figure a) Schematic diagram of the encryption cell matrix b) Encryption and decryption process of digital strings c) Encryption and decryption of images and decrypt both numbers and images As shown in Figure 8b, the encryption matrix is used to encrypt and decrypt a string of numbers “965841” First, a × 10 binary matrix and two × key matrices are constructed In this construction, the dark matrix represents a high level, while the light matrix represents a low level During the encryption process, the encrypted image is generated by adding the original digital matrix to the encryption key “0” corresponds to the low level in the matrix, while “1” corresponds to the high level in the matrix The encrypted output is depicted in Figure S7 (Supporting Information), which completes the encryption of the digital string In the encryption matrix, each digit in the digit string represents an encryption key input The encrypted image matrix is obtained by adding each element of the encrypted image matrix to the corresponding elements of the two key matrices When the information is trans- Adv Funct Mater 2024, 2313219 mitted, the decrypted image matrix can be obtained by adding the encrypted image matrix to the elements corresponding to the two key matrices Upon comparing the decrypted image matrix with the original image matrix, it is evident that the decrypted image matrix is identical to the original image matrix This effectively ensures the integrity of the data throughout the encryption and decryption process In order to enhance the effectiveness of the encryption matrix, the encryption and decryption processes are validated using a 512 × 512 grayscale landscape image The color landscape image is converted to a binary image to obtain the original binary image Then, two random key matrices of the same size as the original image are generated, as shown in Figure 8c Each pixel of the original image is added to the corresponding pixel of the two keys to obtain the encrypted image The decrypted image can 2313219 (11 of 13) © 2024 Wiley-VCH GmbH www.advancedsciencenews.com www.afm-journal.de be obtained by adding the encrypted image to the two keys Comparing the original image with the decrypted image, it is evident that they are identical The encryption circuit proposed in this study can both encrypt and decrypt information data, and the result is consistent with the original image In addition, encryption circuits based on physical hardware levels are more secure, making it difficult for information to be leaked Supporting Information Supporting Information is available from the Wiley Online Library or from the author Conclusion In summary, a bilayer CeOx /WOy film-based memristor was fabricated using magnetron sputtering By comparing three different top electrodes—Ag, Ti, and TiN, it was found that the Ag/CeOx /WOy /ITO device exhibits superior performance in terms of durability and the HRS/LRS resistance ratio The morphology, crystallization, and composition of the CeOx /WOy bilayer film were analyzed through material characterization tests such as SEM, XRD, XPS, etc Furthermore, by comparing the effect of the voltage window on memristive performance, it was found that the HRS/LRS resistance ratio increases with the increase of the voltage window Moreover, it is observed that the HRS/LRS resistance ratio initially increases and then decreases with the increase of the bias voltage scan rate when comparing the influence of different bias voltage scan rates on the device By analyzing and fitting the logarithm of the I–V curve, the memristive behavior of the device can be theoretically explained using the SCLC mechanism and Schottky emission Finally, four fundamental digital logic circuits (OR, AND, XOR, and XNOR) were constructed using memristors, along with half-adders and fulladders that can be utilized for digital arithmetic operations We have also developed a parity checker based on XOR and XNOR logic circuits to verify the accuracy of data transmission In particular, a memory-based cryptographic array was constructed and implemented for encrypting and decrypting digital strings and images These results contribute to expanding the application of memristors in the fields of information transmission and data security encryption Experimental Section Material Synthesis and Device Fabrication: In this experiment, CeOx and WOy films were successively prepared on an ITO substrate by magnetron sputtering First, the ITO substrate with an area of 1.5 × 1.5 square centimeters was ultrasonically cleaned with deionized water, absolute ethanol, and deionized water for 15 to remove residual organic matter from the surface The memristor was prepared using a multifunctional sputtering apparatus (FJL450) When the high-purity argon gas with a flow rate of 20 sccm was introduced at a sputtering pressure of 2.0 Pa, the CeOx and WOy films were deposited on ITO using radio frequency magnetron sputtering as the functional layer of the memristor Finally, the Ag as the top electrode was sputtered onto the surface of the functional layer using direct current magnetron sputtering Characterizations and Electrical Measurements: The morphologies and cross-sectional images of the device were analyzed using a scanning electron microscope (SEM, FEI inspect F) under a vacuum level of less than 5.1 × 10−5 Pa EDS was used to analyze the elemental composition and content of functional layer materials in devices XRD analysis was conducted to ascertain the structure and composition of the functional layers of the device The chemical valence states of the CeOx and WOy films were analyzed using monochromatic X-ray photoelectron spectroscopy (XPS, Adv Funct Mater 2024, 2313219 Thermo Scientific Nexsa) with energy of 1486.6 eV (Al K𝛼 X-ray source) under a vacuum level of less than × 10−10 Pa The electrochemical properties of the memristor were analyzed using a CHI-660E electrochemical workstation The memristor-based circuit simulation was conducted using the Simulink module of MATLAB Conflict of Interest The authors declare no conflict of interest Acknowledgements The authors gratefully acknowledge financial support from the National Natural Science Foundation of China (52375575), and B Sun is grateful to the Xi’an Jiaotong University for the financial support of the top young talent project (71211223010708) Data Availability Statement The data that support the findings of this study are available from the corresponding author upon reasonable request Keywords artificial intelligence, image recognition, logic gate, memristor, odd/even checker Received: October 24, 2023 Revised: December 25, 2023 Published online: [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] K Sun, J Chen, X Yan, Adv Funct Mater 2021, 31, 2006773 Z Lv, Y Zhou, S.-T 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