Introduction to semiconductor manufacturing technology

INTRODUCTION TO Semiconductor Manufacturing Technology Tai Lieu Chat Luong SECOND EDITION HOne Xiao SPIE PRESS Bellingham, Washington USA Library of Congress Cataloging-in-Publication Data Xiao, Hong Introduction to semiconductor technology / Hong Xiao – 2nd ed p cm Includes bibliographical references and index ISBN 978-0-8194-9092-6 Semiconductors–Design and construction Semiconductor industry I Title TK7871.85.X53 2012 621.381502–dc23 2012013231 Published by SPIE P.O Box 10 Bellingham, Washington 98227-0010 USA Phone: +1 360.676.3290 Fax: +1 360.647.1445 Email: Books@spie.org Web: http://spie.org c 2012 Society of Photo-Optical Instrumentation Engineers (SPIE) Copyright All rights reserved No part of this publication may be reproduced or distributed in any form or by any means without written permission of the publisher The content of this book reflects the work and thought of the author(s) Every effort has been made to publish reliable and accurate information herein, but the publisher is not responsible for the validity of the information or for any outcomes resulting from reliance thereon Printed in the United States of America First printing Preface to the First Edition The semiconductor industry is developing rapidly with new technology introduced almost on a daily basis The device feature size is shrinking continuously and the number of transistors on an integrated circuit (IC) chip is increasing rapidly, as predicted by Moore’s law Compared with only a decade ago, IC fabrication processing technology has become more complicated This book thoroughly describes the complicated IC chip manufacturing processes in a semiconductor fab, using minimum mathematics, chemistry, and physics It covers the advanced technologies while keeping the contents simple and easy to understand for readers without science and engineering degrees It focuses on the newest IC fabrication technologies and describes the older technologies to provide better understanding of the historical development The processes chosen for the book are very close to those used in real fabs, especially process troubleshooting and process and hardware relations This book is intended for technical and college students who need an in-depth understanding of the technology as they prepare to find a job in the field It is also intended as a reference book for engineering students and to provide a more realistic picture of the semiconductor industry Industry operators, technicians, engineers, and personnel in sales, marketing, administration, and management can also benefit This book can help them to learn more about their jobs, improve their troubleshooting and problem-solving skills, and raise their career development potential Chapter briefly reviews the history of the semiconductor industry and describes semiconductor manufacturing processes Chapter introduces basic semiconductor fabrication including yield, cleanroom, semiconductor fab, and IC chip test and packaging Chapter gives a brief review of fabrication semiconductor devices, IC chips, and early technologies in semiconductor processing Crystal structure, single-crystal silicon wafer manufacturing, and epitaxial silicon growth are described in Chapter Chapter lists and discusses thermal processes, including oxidation, diffusion, annealing, alloying, and reflow processes Rapid thermal processes (RTPs) and conventional furnace thermal processes are discussed Chapter details the photolithography process Fundamentals of plasmas used in semiconductor processing are covered in Chapter 7, which introduces plasma applications, DC bias, and plasma-process relations Chapter discusses the ion implantation process Chapter gives a detailed description of etch processes including wet and dry etches; chemical, reactive ion etch (RIE), and xxi xxii Preface to the First Edition physical etches; and patterned and blanket etch processes Basic chemical vapor deposition (CVD) and dielectric thin-film deposition processes, including dielectric CVD processes, process trends, troubleshooting, and future trends are discussed in detail in Chapter 10 Chapter 11 covers metallization, metal CVD, and physical vapor deposition (PVD) processes It also describes the copper metallization process Planarization processes including chemical mechanical polishing (CMP) are discussed in Chapter 12 Chapter 13 discusses process integration Chapter 14 diagrams CMOS process flows including an advanced CMOS process flow with copper and low-κ interconnection Chapter 15 predicts the future development of the semiconductor industry Many people helped me to write this book I especially appreciate the useful information provided by my current and former colleagues: Lou Frenzel, Thomas E Thompson, Ole Krogh, Tony Shi, Alberto Quiñonez, Lance Kinney, Scott Bolton, and Steve Reedy Many of my students helped me by proofreading and improving the book I especially express my thanks to Wayne Parent, Jeffrey Carroll, Boyd Woods, and Ronald Tabery I would also like to thank the following reviewers for their valuable suggestions: Professor Dave Hata, Portland Community College; Professor Fred Lavender, Albuquerque Technical Institute; Professor Gene Stouder, Southwest Texas State University; Professor Bassam Matar, Glendale Community College; Professor Carlo Sapijaszko, DeVry Institute of Technology; Professor George Shaiffer, Pikes Peak Community College; Professor Val Shires, Gwinnett Technical Institute; and Professor Devinder Sud, DeVry Institute Hong Xiao 2001 Contents Preface to the First Edition xxi Preface to the Second Edition xxiii List of Acroynms xxv Chapter 1.1 1.2 1.3 1.4 1.5 Chapter 2.1 2.2 2.3 Introduction Brief History of Integrated Circuits 1.1.1 First transistor 1.1.2 First integrated circuit 1.1.3 Moore’s law 1.1.4 Feature and wafer size 1.1.5 Definition of the integrated circuit technology node 1.1.6 Moore’s law or the law of more Brief Overview of Integrated Circuits 1.2.1 Manufacturing materials 1.2.2 Processing equipment 1.2.3 Metrology tools 1.2.4 Wafer manufacturing 1.2.5 Circuit design 1.2.6 Mask formation 1.2.7 Wafer processing Summary Bibliography Review Questions 2 5 10 11 12 12 12 13 13 14 16 19 19 20 21 Introduction to Integrated Circuit Fabrication 23 Introduction Yield 2.2.1 Definition of yield 2.2.2 Yield and profit margin 2.2.3 Defects and yield Cleanroom Basics 2.3.1 Definition of a cleanroom vii 23 25 25 26 27 28 29 viii Contents 2.4 2.5 2.6 2.7 2.8 2.9 Chapter 3.1 3.2 3.3 2.3.2 Contamination control and yield 2.3.3 Basic cleanroom structure 2.3.4 Basic cleanroom gowning procedures 2.3.5 Basic cleanroom protocols Basic Structure of an Integrated Circuit Fabrication Facility 2.4.1 Wafer processing area 2.4.1.1 Wet bay 2.4.1.2 Diffusion bay 2.4.1.3 Photo bay 2.4.1.4 Etch bay 2.4.1.5 Implant bay 2.4.1.6 Thin-film bay 2.4.1.7 Chemical mechanical polishing bay 2.4.2 Equipment area 2.4.3 Facility area Testing and Packaging 2.5.1 Die testing 2.5.2 Chip packaging 2.5.3 Final test 2.5.4 3D packaging Future Trends Summary Bibliography Review Questions 30 32 33 35 36 37 37 38 40 40 42 42 44 45 45 46 47 47 52 53 53 55 56 56 Semiconductor Basics 59 What Is a Semiconductor? 3.1.1 Bandgap 3.1.2 Crystal structure 3.1.3 Doping semiconductor 3.1.4 Dopant concentration and conductivity 3.1.5 Summary of semiconductors Basic Devices 3.2.1 Resistor 3.2.2 Capacitor 3.2.3 Diode 3.2.4 Bipolar transistor 3.2.5 Metal-oxide-semiconductor field effect transistor Integrated Circuit Chips 3.3.1 Memory 3.3.1.1 Dynamic random access memory 3.3.1.2 Static random access memory 3.3.1.3 Erasable programmable read-only memory, electric erasable programmable read-only memory, and flash 59 59 61 61 63 64 64 64 66 69 70 72 74 75 75 75 76 ix Contents 3.4 3.5 3.6 3.7 3.8 3.9 Chapter 4.1 4.2 4.3 4.4 4.5 4.6 3.3.2 Microprocessor 3.3.3 Application-specific integrated circuits Basis Integrated Circuit Processes 3.4.1 Conventional bipolar transistor process 3.4.2 p-Channel metal-oxide-semiconductor process (1960s technology) 3.4.3 n-Channel metal-oxide-semiconductor process (1970s technology) Complementary Metal-Oxide Semiconductor 3.5.1 Complementary metal-oxide-semiconductor circuit 3.5.2 Complementary metal-oxide-semiconductor circuit process (1980s technology) 3.5.3 Complementary metal-oxide-semiconductor process (1990s technology) Technology Trends after 2000 Summary Bibliography Review Questions 78 79 79 80 81 82 82 85 87 89 89 90 92 93 Wafer Manufacturing, Epitaxy, and Substrate Engineering 95 Introduction Why Silicon? Crystal Structures and Defects 4.3.1 Crystal orientation 4.3.2 Crystal defects Sand to Wafer 4.4.1 Crude silicon 4.4.2 Silicon purification 4.4.3 Crystal pulling 4.4.3.1 Czochralski method 4.4.3.2 Floating zone method 4.4.4 Wafering 4.4.5 Wafer finishing Epitaxial Silicon Deposition 4.5.1 Gas phase epitaxy 4.5.2 Epitaxial growth process 4.5.3 Epitaxy hardware 4.5.4 Epitaxy process 4.5.5 Future trends of epitaxy 4.5.6 Selective epitaxy Substrate Engineering 4.6.1 Silicon-on-insulator wafer 4.6.2 Hybrid orientation technology 4.6.3 Strained silicon wafer 95 96 97 97 99 100 100 101 102 102 104 105 107 108 110 111 112 114 115 116 116 116 118 119 x Contents 4.7 4.8 4.9 Chapter 5.1 5.2 4.6.4 Strained silicon-on-insulator wafer 4.6.5 Strained silicon in integrated circuit manufacturing Summary Bibliography Review Questions 119 120 120 122 122 Thermal Processes 125 Introduction Thermal Process Hardware 5.2.1 Introduction 5.2.2 Control system 5.2.3 Gas delivery system 5.2.4 Loading system 5.2.5 Exhaust system 5.2.6 Processing tube 5.3 Oxidation 5.3.1 Applications 5.3.2 Preoxidation cleaning 5.3.3 Oxidation rate 5.3.4 Dry oxidation 5.3.5 Wet oxidation 5.3.6 High-pressure oxidation 5.3.7 Oxide measurement 5.3.8 Recent oxidation trends 5.4 Diffusion 5.4.1 Deposition and drive-in 5.4.2 Doping measurement 5.5 Annealing 5.5.1 Postimplantation annealing 5.5.2 Alloy annealing 5.5.3 Reflow 5.6 High-Temperature Chemical Vapor Deposition 5.6.1 Epitaxial silicon deposition 5.6.2 Selective epitaxial growth processes 5.6.3 Polycrystalline silicon deposition 5.6.4 Silicon nitride deposition 5.7 Rapid Thermal Processing 5.7.1 Rapid thermal annealing 5.7.2 Rapid thermal oxidation 5.7.3 Rapid thermal chemical vapor deposition 5.8 Recent Developments 5.9 Summary 5.10 Bibliography 5.11 Review Questions 125 126 126 127 128 128 129 129 129 131 135 137 139 142 145 146 149 150 152 154 156 156 157 158 159 159 160 160 164 167 168 171 173 174 176 177 177 xi Contents Chapter 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Chapter 7.1 7.2 Photolithography 179 Introduction Photoresist Photolithography Process 6.3.1 Wafer cleaning 6.3.2 Preparation 6.3.3 Photoresist coating 6.3.4 Soft bake 6.3.5 Alignment and exposure 6.3.5.1 Contact and proximity printers 6.3.5.2 Projection printer 6.3.5.3 Stepper/scanner 6.3.5.4 Exposure light sources 6.3.5.5 Exposure control 6.3.6 Postexposure bake 6.3.7 Development 6.3.8 Hard bake 6.3.9 Metrology and defect inspection 6.3.10 Track-stepper integration system Lithographic Technology Trends 6.4.1 Resolution and depth of focus 6.4.2 Mercury lamps and excimer lasers 6.4.3 Resolution enhancement techniques 6.4.3.1 Phase shift mask 6.4.3.2 Optical proximity correction 6.4.3.3 Off-axis illumination 6.4.4 Immersion lithography 6.4.5 Double, triple, and multiple patterning 6.4.6 Extreme-ultraviolet lithography 6.4.7 Nanoimprint lithography 6.4.8 X-ray lithography 6.4.9 Electron beam lithography 6.4.10 Ion beam lithography Safety Summary Bibliography Review questions 179 181 184 185 187 188 193 194 194 195 196 199 199 201 203 205 206 211 212 212 215 216 217 218 219 221 222 226 228 229 230 231 232 233 234 235 Plasma Basics 237 Introduction Definition of Plasma 7.2.1 Components of plasma 7.2.2 Generation of plasma 237 237 238 238 xii Contents 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 Chapter 8.1 Collisions in Plasma 7.3.1 Ionization 7.3.2 Excitation-relaxation 7.3.3 Dissociation 7.3.4 Other collisions Plasma Parameters 7.4.1 Mean free path 7.4.2 Thermal velocity 7.4.3 Magnetic field 7.4.4 Boltzmann distribution Ion Bombardment Direct-Current Bias Advantage of Plasma Processes 7.7.1 Chemical vapor deposition 7.7.1.1 Plasma-enhanced chemical vapor deposition 7.7.1.2 Stress control 7.7.1.3 Chamber cleaning 7.7.1.4 Gap fill 7.7.2 Plasma etch 7.7.2.1 Etch profile control 7.7.2.2 Etch rate and selectivity 7.7.2.3 Endpoint 7.7.2.4 Chemical use 7.7.3 Sputtering deposition Plasma-Enhanced Chemical Vapor Deposition and Plasma Etch Chambers 7.8.1 Processing differences 7.8.2 Chemical vapor deposition chamber design 7.8.3 Etch chamber design Remote Plasma Processes 7.9.1 Photoresist strip 7.9.2 Remote plasma etch 7.9.3 Remote plasma cleaning 7.9.4 Remote plasma chemical vapor deposition High-Density Plasma 7.10.1 Inductively coupled plasma 7.10.2 Electron cyclotron resonance Summary Bibliography Review Questions 239 239 240 241 243 243 244 245 247 248 248 250 253 254 254 255 255 256 256 256 257 257 257 257 257 257 258 258 260 260 260 261 262 262 263 264 264 265 265 Ion Implantation 267 Introduction 267 8.1.1 Brief history 267 Index Terms Links etch 315 dielectric 342 dry (plasma) 330 main 322 mechanisms 333 metal 329 oxide 344 polysilicon gate 353 profile 320 rate 317 reactive ion (RIE) 320 332 single-crystal silicon 349 351 wet 325 340 etch bay 40 etch pits 97 etch process 42 etching 40 340 357 evaporation electron beam 486 excitation-relaxation 240 exhaust system 129 exposure control 199 F facility area 45 Fairchild Semiconductor feature size 11 31 53 78 89 199 201 218 field effect transistor (FET) 72 73 This page has been reformatted by Knovel to provide easier navigation Index Terms Links film thickness flip-chip technology floating zone (FZ) method 539 49 102 foundry company 16 four-point probe 305 474 free radicals 241 242 260 333 Frenkel defect fumed silica furnace 257 99 524 39 126 167 282 horizontal 129 vertical 129 G gap fill 256 gas delivery system 128 gas system 284 380 gases processing gate 128 10 capacitance 72 76 62 73 445 germanium bar single-crystal 96 glass transition 202 gowning 33 graphics processing unit (GPU) 78 gyrofrequency 248 gyromotion 247 35 286 This page has been reformatted by Knovel to provide easier navigation Index Terms Links gyroradius 248 288 H hard bake 205 heating process Horni, Jean hot electron effect hydrofluoric acid (HF) 80 187 297 35 37 107 114 144 67 89 325 hydrogen 39 I I-V curve 70 implant bay 42 implantation 564 in-situ process 173 insulator 59 integrated circuit (IC) application-specific (ASIC) 79 design 16 first processing 53 technology Intel Corporation interconnection 42 570 copper 574 early 572 local 570 interlayer dielectric (ILD) film intermetal dielectric (IMD) 347 88 370 This page has been reformatted by Knovel to provide easier navigation Index Terms Links interstitial defect 99 ion bombardment 248 249 255 257–259 330 331 42 79 82 151 206 267 270 279 291 294 299 305 333 ion implantation advantages 270 applications 271 ion implanter 247 ionization 238 240 junction depth 150 174 junction spiking 456 J K Kilby, Jack killer defect density 27 L laminar flow 33 light sources 199 215 lightly doped drain (LDD) 297 561 line resistance 452 lithography electron-beam (e-beam) extreme ultraviolet (EUV) nanoimprint (NIL) 231 80 226 228 This page has been reformatted by Knovel to provide easier navigation Index Terms Links lithography (Cont.) next-generation (NGL) 216 x-ray 229 loading effect 16 loading system 128 local oxidation of silicon (LOCOS) logic design 321 87 89 552 554 133 14 low-pressure chemical vapor deposition (LPCVD) 38 M magnetic field 247 288 294 16 18 23 194 196 223 227 230 111 389 489 mask mass-transport-limited regime material structure 95 amorphous 95 polycrystalline 95 single-crystal 95 mean free path (MFP) 244 330 memory 75 76 chip 75 625 flash 77 78 636 42 72 73 81 85 120 metal-insulator-semiconductor (MIS) metal-oxide semiconductor (MOS) 96 269 metal-oxide-semiconductor field effect transistor (MOSFET) 564 This page has been reformatted by Knovel to provide easier navigation Index Terms Links metallization 345 451 copper 497 498 metrology tools 40 42 microprocessor 78 43 microscope scanning electron (SEM) 40 Moore’s law Moore, Gordon N n-channel metal-oxide semiconductor (nMOS) n-type region nickel 72 296 69 465 nitric acid (HNO3) 37 107 nitrogen 39 46 Noyce, Robert nucleation step 478 O orientation crystal 97 overhangs 378 oxidation 129–131 137 dry 139 140 high-pressure 145 rapid thermal (RTO) 171 trends 149 wet 138 142 This page has been reformatted by Knovel to provide easier navigation 114 Index Terms Links oxide blanket-field 82 88 132 81 296 551 gate 134 growth rate 137 oxygen 39 ozonator 422 ozone 421 concentration 422 P p-channel metal-oxide semiconductor (pMOS) 72 p–n junction 69 p-type region 69 p-well implantation packaging 288 46 ceramic 51 plastic 51 yield 25 particle 53 26 30 killer 31 passivation 413 577 614 80 179 patterning process 301 pellicle 17 phase shift mask (PSM) 217 phosphine 39 phosphorus silicate glass (PSG) 82 photo bay 40 This page has been reformatted by Knovel to provide easier navigation Index Terms photolithography Links 80 82 179 199 215 optical 89 process 19 31 40 181 183 184 photomask 230 photoresist 23 coating 188 negative 31 positive 31 strip 260 photoresist etchback 514 photoresist strip 41 photoresist stripping 80 physical vapor deposition (PVD) 43 aluminum–copper 495 titanium 493 titanium nitride 494 physisorption planar technology 358 374 483 239 248 262 331 383 planarization 511 plasma 237 330 definition of 237 high-density 238 340 inductively coupled (ICP) 263 potential 250 radio frequency (rf) 238 plasma etch remote 256 261 This page has been reformatted by Knovel to provide easier navigation Index Terms Links plasma-enhanced chemical vapor deposition (PECVD) 42 polishing head 521 polishing pad 519 polymer 182 polysilicon 65 66 82 101 296 297 320 454 603 postacceleration 289 postexposure bake (PEB) 202 Pourbaix diagram 526 preclean 492 predeposition 152 premetal dielectric (PMD) 370 Preston equation 528 prism coupler 401 process gases 45 processing tools 45 profilometer 467 profit margin 26 projection exposure system 30 195 Q quartz sand 96 100 R rapid thermal annealing (RTA) 168 rapid thermal annealing (RTA) systems rapid thermal processing (RTP) 42 80 157 167 169 174 283 This page has been reformatted by Knovel to provide easier navigation Index Terms RC time delay Links 67 reflectivity 472 reflow 159 refractive index 146 remote plasma CVD (RPCVD) 262 removal process 44 79 65 70 154 155 305 472 resistivity 60 63 resistor 64 removal rate resistance sheet resolution reticle rf power 40 398 528 180 199 213 215 221 18 197 201 503 433 S safety 232 308 scanning electron microscope (SEM) 209 467 Schottky defect 99 selective epitaxial growth (SEG) 116 selectivity 320 self-aligned contact (SAC) 345 SEMATECH semiconductor 59 manufacturing 12 materials 59 processing 12 sensitizer 183 shadowing effect 279 322 529 36 80 This page has been reformatted by Knovel to provide easier navigation Index Terms shallow trench isolation (STI) self-aligned (SA-STI) sheath potential Shockley, William Links 41 89 349 391 554 617 557 639 249 269 shrinkage 407 sidewall spacer 164 391 39 111 411 435 silane silicide 570 silicon 24 crude 383 96 137 96 100 125 130 132 135 101 dioxide 140 epitaxial etch process 159 41 metallurgical-grade (MGS) 100 nitride 166 on isolator (SOI) 600 oxide 255 polycrystalline 104 single-crystal 390 13 62 95 97 102 103 267 327 substrate 125 300 silicon oxide 55 silicon-oxide surface 72 single-crystal semiconductor materials 61 structure 61 single-crystal structure 281 This page has been reformatted by Knovel to provide easier navigation Index Terms Links single-wafer implantation 293 slurry 107 aluminum 527 copper 527 metal polishing 525 oxide 523 soft bake 193 solvent 183 spectroreflectometry 404 spin 204 disk 522 293 spin-on glass (SOG) 396 424 sputtering 418 487 reactive sputtering etch process 460 43 standing wave effect 201 static dispense 189 static random access memory (SRAM) step coverage step-and-repeat 75 377 18 step-and-repeat system 196 stepper 197 sticking coefficient 386 stopping mechanisms 272 electronic stopping 272 nuclear stopping 272 stress 408 470 surface mobility 374 379 surface-reaction-limited regime 111 388 system ground potential 288 This page has been reformatted by Knovel to provide easier navigation 524 Index Terms Links T tantalum 464 test 52 tetraethyl-orthosilicate (TEOS) 43 plasma-enhanced (PE-TEOS) 386 434 tetraethylorthosilicate (TEOS) 347 tetramethyl ammonium hydroxide 203 Texas Instruments 384 thermal evaporation 485 thermal budget 151 thermal expansion 409 thermal processing 125 thermal stress 281 53 thermal velocity 245 thermal wave 306 thickness 402 thin films metal 465 thin-film bay 42 threshold adjustment 563 titanium 458 481 nitride 459 481 silicide 454 458 track system 211 transistor bipolar first 70 71 70 level design 14 npn 71 point-contact bipolar 96 This page has been reformatted by Knovel to provide easier navigation 81 Index Terms transition region Links 69 trench fill 132 trichlorosilane (TCS) 101 troubleshooting 437 tungsten 461 477 479 40 76 232 407 469 529 114 193 silicide 480 slurry 526 U ultraviolet (UV) light uniformity V vacancy 99 valence shell 59 void formation 441 W wafer 97 204 charging 302 cleaning 185 finishing 108 handler 292 manufacturing 13 preparation 550 processing 36 47 107 116 118 272 silicon-on-insulator (SOI) size This page has been reformatted by Knovel to provide easier navigation Index Terms Links wafer (Cont.) surface temperature yield 40 294 339 25 26 wafer preparation 88 wafer processing 19 28 wafer-to-wafer (WTW) nonuniformity wafer-to-wafer (WTW) uniformity well formation 156 112 318 88 557 self-aligned twin well 88 single well 88 wet bay 37 wet clean processing 136 wet etch 536 process 107 rate 406 wet processes 37 wire bonding 49 50 X xylene 232 Y yield 25–28 30 This page has been reformatted by Knovel to provide easier navigation