Bsi bs en 62228 2 2017

BS EN 62228-2:2017 BSI Standards Publication Integrated circuits — EMC evaluation of transceivers Part 2: LIN transceivers BRITISH STANDARD BS EN 62228-2:2017 National foreword This British Standard is the UK implementation of EN 62228-2:2017 It is identical to IEC 62228-2:2016 The UK participation in its preparation was entrusted to Technical Committee EPL/47, Semiconductors A list of organizations represented on this committee can be obtained on request to its secretary This publication does not purport to include all the necessary provisions of a contract Users are responsible for its correct application © The British Standards Institution 2017 Published by BSI Standards Limited 2017 ISBN 978 580 87526 ICS 31.200 Compliance with a British Standard cannot confer immunity from legal obligations This British Standard was published under the authority of the Standards Policy and Strategy Committee on 28 February 2017 Amendments/corrigenda issued since publication Date Text affected BS EN 62228-2:2017 EUROPEAN STANDARD EN 62228-2 NORME EUROPÉENNE EUROPÄISCHE NORM February 2017 ICS 31.200 English Version Integrated circuits - EMC evaluation of transceivers Part 2: LIN transceivers (IEC 62228-2:2016) Circuits intégrés - Évaluation de la CEM des émetteursrécepteurs - Partie 2: Émetteurs-récepteurs LIN (IEC 62228-2:2016) Integrierte Schaltungen - Bewertung der elektromagnetischen Verträglichkeit von SendeEmpfangsgeräten - Teil 2: LIN-Sende-Empfangsgeräte (IEC 62228-2:2016) This European Standard was approved by CENELEC on 2016-12-23 CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC Management Centre or to any CENELEC member This European Standard exists in three official versions (English, French, German) A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the same status as the official versions CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Serbia, Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and the United Kingdom European Committee for Electrotechnical Standardization Comité Européen de Normalisation Electrotechnique Europäisches Komitee für Elektrotechnische Normung CEN-CENELEC Management Centre: Avenue Marnix 17, B-1000 Brussels © 2017 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC Members Ref No EN 62228-2:2017 E BS EN 62228-2:2017 EN 62228-2:2017 European foreword The text of document 47A/994/FDIS, future edition of IEC 62228-2, prepared by SC 47A "Integrated circuits" of IEC/TC 47 "Semiconductor devices" was submitted to the IEC-CENELEC parallel vote and approved by CENELEC as EN 62228-2:2017 The following dates are fixed: • latest date by which the document has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2017-09-23 • latest date by which the national standards conflicting with the document have to be withdrawn (dow) 2019-12-23 Attention is drawn to the possibility that some of the elements of this document may be the subject of patent rights CENELEC [and/or CEN] shall not be held responsible for identifying any or all such patent rights Endorsement notice The text of the International Standard IEC 62228-2:2016 was approved by CENELEC as a European Standard without any modification BS EN 62228-2:2017 EN 62228-2:2017 Annex ZA (normative) Normative references to international publications with their corresponding European publications The following documents, in whole or in part, are normatively referenced in this document and are indispensable for its application For dated references, only the edition cited applies For undated references, the latest edition of the referenced document (including any amendments) applies NOTE When an International Publication has been modified by common modifications, indicated by (mod), the relevant EN/HD applies NOTE Up-to-date information on the latest versions of the European Standards listed in this annex is available here: www.cenelec.eu Publication Year Title EN/HD IEC 61967-1 - Integrated circuits - Measurement of EN 61967-1 electromagnetic emissions, 150 kHz to GHz Part 1: General conditions and definitions - IEC 61967-4 - Integrated circuits - Measurement of EN 61967-4 electromagnetic emissions, 150 kHz to GHz Part 4: Measurement of conducted emissions - ohm/150 ohm direct coupling method - IEC 62132-1 - Integrated circuits - Measurement of EN 62132-1 electromagnetic immunity Part 1: General conditions and definitions - IEC 62132-4 - Integrated circuits - Measurement of electromagnetic immunity, 150 kHz to GHz Part 4: Direct RF power injection method EN 62132-4 - IEC 62215-3 - Integrated circuits - Measurement of impulse immunity - Part 3: Nonsynchronous transient injection method EN 62215-3 - ISO 7637-2 - Road vehicles - Electrical disturbances from conduction and coupling Part-2: Electrical transient conduction along supply lines only - - ISO 10605 - Road vehicles - Test methods for electrical disturbances from electrostatic discharge - ISO 17987-6 - Road vehicles - Local Interconnect Network (LIN) Part 6: Protocol conformance test specification - - Year –2– BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 CONTENTS FOREWORD Scope Normative references Terms, definitions and abbreviations 3.1 Terms and definitions 3.2 Abbreviations General Test and operating conditions 5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.4 5.4.1 5.4.2 5.4.3 5.5 5.5.1 5.5.2 Supply and ambient conditions Test operation modes 10 Test configuration 10 General test configuration for functional test 10 General test configuration for unpowered ESD test 11 Coupling ports and coupling networks for functional tests 11 Coupling ports and coupling networks for unpowered ESD tests 12 Test signals 13 General 13 Test signals for normal operation mode 13 Test signal for wake-up from sleep mode 14 Evaluation criteria 14 General 14 Evaluation criteria in functional operation modes during exposure to disturbances 15 5.5.3 Evaluation criteria in unpowered condition after exposure to disturbances 16 5.5.4 Status classes 17 Test and measurement 17 6.1 Emission of RF disturbances 17 6.1.1 Test method 17 6.1.2 Test setup 17 6.1.3 Test procedure and parameters 18 6.2 Immunity to RF disturbances 19 6.2.1 Test method 19 6.2.2 Test setup 19 6.2.3 Test procedure and parameters 20 6.3 Immunity to impulses 22 6.3.1 Test method 22 6.3.2 Test setup 23 6.3.3 Test procedure and parameters 23 6.4 Electrostatic Discharge (ESD) 26 6.4.1 Test method 26 6.4.2 Test setup 26 6.4.3 Test procedure and parameters 28 Test report 28 Annex A (normative) LIN test circuits 29 A.1 General 29 BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 A.2 A.3 A.4 Annex B –3– LIN test circuit for standard LIN transceiver ICs for functional tests 29 LIN test circuit for IC with embedded LIN transceiver for functional tests 31 LIN test circuit for LIN transceiver ICs for unpowered ESD test 32 (normative) Test circuit boards 33 B.1 Test circuit board for functional tests 33 B.2 ESD test 33 Annex C (informative) Examples for test limits for LIN transceiver in automotive application 35 C.1 C.2 C.3 C.4 C.5 Annex D General 35 Emission of RF disturbances 35 Immunity to RF disturbances 36 Immunity to impulses 37 Electrostatic Discharge (ESD) 37 (informative) Test of indirect ESD discharge 38 D.1 D.2 D.3 D.4 General 38 Test setup 38 Typical current wave form for indirect ESD test 39 Test procedure and parameters 39 Figure – General test configuration for tests in functional operation modes 10 Figure – General test configuration for unpowered ESD test 11 Figure – Coupling ports and networks for functional tests 11 Figure – Coupling ports and networks for unpowered ESD tests 12 Figure – Principal drawing of the maximum deviation on an I-V characteristic 16 Figure – Test setup for measurement of RF disturbances 18 Figure – Test setup for DPI tests 19 Figure – Test setup for impulse immunity tests 23 Figure – Test setup for direct ESD tests 27 Figure A.1 – General drawing of the circuit diagram of test network for standard LIN transceiver ICs for functional test 30 Figure A.2 – General drawing of the circuit diagram of the test network for ICs with embedded LIN transceiver for functional test 32 Figure A.3 – General drawing of the circuit diagram for direct ESD tests of LIN transceiver ICs in unpowered mode 32 Figure B.1 – Example of IC interconnections of LIN signal 33 Figure B.2 – Example of ESD test board for LIN transceiver ICs 34 Figure C.1 – Example of limits for RF emission 36 Figure C.2 – Example of limits for RF immunity for functional status class A IC 36 Figure C.3 – Example of limits for RF immunity for functional status class C IC or D IC 37 Figure D.1 – Test setup for indirect ESD tests 38 Figure D.2 – Example of ESD current wave form for indirect ESD test at V ESD = -8 kV 39 Table – Overview of required measurements and tests Table – Supply and ambient conditions for functional operation 10 Table – Definition of coupling ports and coupling network component values for functional tests 12 –4– BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 Table – Definitions of coupling ports for unpowered ESD tests 13 Table – Communication test signal TX1 13 Table – Communication test signal TX2 14 Table – Wake-up test signal TX3 14 Table – Evaluation criteria for Standard LIN transceiver IC in functional operation modes 15 Table – Evaluation criteria for ICs with embedded LIN transceiver in functional operation modes 16 Table 10 – Definition of functional status classes 17 Table 11 – Parameters for emission measurements 18 Table 12 – Settings of the RF measurement equipment 19 Table 13 – Specifications for DPI tests 20 Table 14 – Required DPI tests for functional status class A IC evaluation of standard LIN transceiver ICs 21 Table 15 – Required DPI tests for functional status class A IC evaluation of ICs with embedded LIN transceiver 22 Table 16 – Required DPI tests for functional status class C IC or D IC evaluation of standard LIN transceiver ICs and ICs with embedded LIN transceiver 22 Table 17 – Specifications for impulse immunity tests 24 Table 18 – Parameters for impulse immunity test 24 Table 19 – Required impulse immunity tests for functional status class A IC evaluation of standard LIN transceiver ICs 25 Table 20 – Required impulse immunity tests for functional status class A IC evaluation of ICs with embedded LIN transceiver 25 Table 21 – Required impulse immunity tests for functional status class C IC or D IC evaluation of standard LIN transceiver ICs and ICs with embedded LIN transceiver 26 Table 22 – Recommendations for direct ESD tests 28 Table B.1 – Parameter ESD test circuit board 34 Table C.1 – Example of limits for impulse immunity for functional status class C IC or D IC 37 Table D.1 – Specifications for indirect ESD tests 40 BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 –5– INTERNATIONAL ELECTROTECHNICAL COMMISSION INTEGRATED CIRCUITS – EMC EVALUATION OF TRANSCEIVERS – Part 2: LIN transceivers FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC National Committees) The object of IEC is to promote international co-operation on all questions concerning standardization in the electrical and electronic fields To this end and in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC Publication(s)”) Their preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with may participate in this preparatory work International, governmental and nongovernmental organizations liaising with the IEC also participate in this preparation IEC collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions determined by agreement between the two organizations 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international consensus of opinion on the relevant subjects since each technical committee has representation from all interested IEC National Committees 3) IEC Publications have the form of recommendations for international use and are accepted by IEC National Committees in that sense While all reasonable efforts are made to ensure that the technical content of IEC Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any misinterpretation by any end user 4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications transparently to the maximum extent possible in their national and regional publications Any divergence between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter 5) IEC itself does not provide any attestation of conformity Independent certification bodies provide conformity assessment services and, in some areas, access to IEC marks of conformity IEC is not responsible for any services carried out by independent certification bodies 6) All users should ensure that they have the latest edition of this publication 7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and members of its technical committees and IEC National Committees for any personal injury, property damage or other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC Publications 8) Attention is drawn to the Normative references cited in this publication Use of the referenced publications is indispensable for the correct application of this publication 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights IEC shall not be held responsible for identifying any or all such patent rights International Standard IEC 62228-2 has been prepared by subcommittee 47A: Integrated circuits, of IEC technical committee 47: Semiconductor devices The text of this standard is based on the following documents: FDIS Report on voting 47A/994/FDIS 47A/998/RVD Full information on the voting for the approval of this standard can be found in the report on voting indicated in the above table This publication has been drafted in accordance with the ISO/IEC Directives, Part –6– BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 A list of all parts in the IEC 62228 series, published under the general title Integrated circuits – EMC evaluation of transceivers, can be found on the IEC website The committee has decided that the contents of this publication will remain unchanged until the stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to the specific publication At this date, the publication will be • reconfirmed, • withdrawn, • replaced by a revised edition, or • amended IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates that it contains colours which are considered to be useful for the correct understanding of its contents Users should therefore print this document using a colour printer – 28 – 6.4.3 BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 Test procedure and parameters To determine the ESD robustness of LIN transceiver ICs against damages, tests shall be carried out following the recommendations given in Table 22 Table 22 – Recommendations for direct ESD tests Item Parameter Type of discharge Contact Discharge circuit R = 330 Ω, C = 150 pF Discharge voltage levels start level kV stop level V ESD_damage or 25 kV Discharge voltage steps kV step up to V ESD = 15 kV, kV step above V ESD = 15 kV Test procedure 1) reference measurement of LIN signal in normal mode (DUT transmitting) and I-V characteristic of all pins to be tested (pin to GND) 2) ESD pulses with positive polarity on discharge point DP2 (V BAT ) with s delay in between, after each single ESD pulse the pin or discharge point has to be discharged to the ground to ensure zero potential before the next ESD pulse 3) failure validation 4) proceed with points 2) to 3) with discharge points DP3 (Wake) 5) proceed with points 2) to 3) with discharge points DP1 (LIN) 6) proceed with point 2) to 5) with negative polarity 7) proceed with point 2) to 6) with the next higher ESD test voltage up to damage of the tested pin If one pin is damaged, a new IC should be used continuing the test of the other pins Failure validation a) evaluation of I-V characteristic according to section 5.5.3 b) additional functional test at each test voltage level: Evaluation of LIN signal The maximum allowed deviation to the reference signal shall be smaller than % Test report The following items should be included in the test report: • schematic diagram of test configurations; • failure criteria, used at immunity tests; • picture or drawing of test circuit boards; • transfer characteristics of coupling and decoupling networks; • description of test equipment; • description of the used protocol version; • description of any deviation from previously defined test parameter, and • test results BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 – 29 – Annex A (normative) LIN test circuits A.1 General The LIN test circuits define the details of the complete test circuitry for testing the LIN transceiver ICs in functional operating modes under network condition and in unpowered mode of a single LIN transceiver IC for ESD It defines mandatory and optional components for LIN transceiver IC functions and components for coupling networks, decoupling networks which are used for power supply, stimulation, monitoring and testing of the DUT The LIN test circuit is basic for the test results and their interpretation A.2 LIN test circuit for standard LIN transceiver ICs for functional tests A general drawing of the test circuit diagram of a LIN test network for testing standard LIN transceiver ICs in functional operating modes in a minimum communication network with two LIN nodes is given in Figure A.1 Node operates as a transmitter for test signals, which emulates a LIN message to be received and monitored at output ports of nodes in the configured network A LIN node consists of transceiver (A1, A2), the LIN bus filter (C13, C23), mandatory external components (D11, C11, C12, R11, R12, R13, D21, C21, C22, R21, R22, R23) and decoupling networks at monitored pins or inputs (R13, R14, R15, R16, R23, R24, R25, R26) All mandatory external components (except components for LIN bus) shall be used according to the specification of the LIN transceiver IC If special components for LIN bus are defined in the specification, this circuitry should be tested in addition The resistor values at the wake pin shall be set to the maximum specified value (default R = 3,3 kΩ) for R11, R21 and to the minimum specified value (default R = 33 kΩ) for R12, R22 For RF decoupling of monitored pins RxD, INH and input TxD the resistor value is set to R = kΩ In order to avoid a floating voltage at pin INH in sleep mode a pull down resistor (R17, R27) shall be used with values according to the IC specifications (default R = 10 kΩ) Every control input setting the DUT either to normal or sleep mode shall be connected/configured according to the IC specification Connections to the peripheral control equipment shall be decoupled from the test circuit board (A4 optocoupler, R41, R42, R43, R44) As regards the bus termination, node has the LIN bus master termination with a resistor (R40 = kΩ) and a diode (D40) For decoupling of external power supplies two-stage LC-filters (L41, L42, C41, C42 and L43, C43, C44, C45) are used separately for V BAT and V CC The impedance of L42 should be greater than 400 Ω in the frequency range of interest Jumper JP41 is opened to disconnect the supply voltage and the RF decoupling filter network at V BAT during the impulse tests at V BAT In this case the voltage supply V BAT is directly provided via the IMP2 coupling network BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 – 30 – VBATc VBAText L41 C41 VCCext JP41 L42 VBATh VCC R41 R42 10 11 12 13 14 15 16 C42 L43 VCC C43 C44 EN2 EN1 VBATc C45 GND Node R40 Ccp1 C13 Rcp1 Rcp1t VBATc D11 CP3 Ccp3 C11 C12 GND TX LIN Wake Vsup EN INH RX R12 R13 EN1 LIN Standard TC VCC R14 TxD1 R15 RxD1 R16 INH1 R17 Node Rcp2 R43 R44 JP21 C23 Ccp2 VBATc R11 A1 Rcp3 Rcp3t CP2 Mode Opto coupler JP11 D40 CP1 A4 VBATh Rcp2t D21 C21 C22 A2 GND TX LIN Wake EN Vsup RX INH R21 VBATc R22 EN3 LIN Standard TC R28 R23 VCC R24 TxD2 R25 RxD2 R26 INH2 R27 IEC Key Components A1, A2 Standard LIN transceiver IC A4 Optocoupler C11, C21, C45 capacitor C = 22 µF C12, C22 capacitor C = 100 nF C13, C23 capacitor C = 110 pF (placement dependent on test case) Ccp1, Ccp2, Ccp3 capacitor (value dependent on test) C41, C43 capacitor C = nF C42, C44 capacitor C = 330 pF D11, D21, D40 diode, general purpose rectifier type JP11, JP21 Jumper L41, L43 inductor L = 47 µH L42 inductor or ferrite, impedance at 100 MHz > 750 Ω R11, R21 resistor R = 3,3 kΩ R12, R22 resistor R = 33 kΩ R13, R23 resistor R = 2,7 kΩ R14, R15, R16, R24, R25, R26 resistor R = kΩ R17, R27 resistor R = 4,7 kΩ R28 resistor R = kΩ (simulates other loads at VBAT network of ECU if available in application) R40, R41, R42, resistor R = kΩ R43, R44, resistor R = 470 Ω Rcp1, Rcp2, Rcp3 resistor (value dependent on test) Rcp1t, Rcp2t, Rcp3t resistor (value dependent on test) Figure A.1 – General drawing of the circuit diagram of test network for standard LIN transceiver ICs for functional test BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 A.3 – 31 – LIN test circuit for IC with embedded LIN transceiver for functional tests A general drawing of a test circuit diagram of a LIN test network for testing ICs with embedded LIN transceivers in functional operating modes in a minimum communication network with two LIN nodes is given in Figure A.2 Depending on the DUT, in normal mode node operates either as LIN master or as LIN slave The DUT LIN transmission is monitored for failure validation LIN node is a standard LIN transceiver IC in basic configuration for normal mode LIN node is the IC with embedded LIN transceiver to be tested, including mandatory external components and decoupling networks (D21, C21, C22) VBATc VBAText L41 C41 JP41 L42 C42 VBATh VBATc VBATc VCCext D40 L43 C43 VCC C44 Node R40 C45 C13 GND VBATc D11 CP1 Ccp1 C11 C12 A1 GND TX LIN Wake Vsup EN INH RX R11 R12 VCC R13 R14 L15 TxD1 RxD1 LIN Standard TC R17 Rcp1 Rcp1t C23 CP2 Ccp2 Rcp2t Rcp2 Node / DUT A2 LIN VBAT VBATh D21 C21 C22 R21 GND IC with embedded LIN Transceiver IEC Key Components A1 Standard LIN transceiver IC A2 IC with embedded LIN transceiver (DUT) C11, C21, C45 capacitor C = 22 µF C12, C22 capacitor C = 100 nF C13, C23 capacitor C = 110 pF (placement dependent on test case) Ccp1, Ccp2 capacitor (value dependent on test) C41, C43 capacitor C = nF C42, C44 capacitor C = 330 pF D11, D21, D40 diode, general purpose rectifier type JP41 Jumper L41, L43 inductor L = 47 µH L42 inductor or ferrite, impedance at 100 MHz > 750 Ω L15 ferrite, impedance at 100 MHz > kΩ R11 resistor R = 10 kΩ BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 – 32 – R12 resistor R = 2,7 kΩ R13 resistor R = 2,7 kΩ R14, R40 resistor R = kΩ R17 resistor R = 4,7 kΩ R21 resistor R = kΩ (simulates other loads at VBAT network of ECU if available in application) Rcp1, Rcp2 resistor (value dependent on test) Rcp1t, Rcp2t resistor (value dependent on test) Figure A.2 – General drawing of the circuit diagram of the test network for ICs with embedded LIN transceiver for functional test A.4 LIN test circuit for LIN transceiver ICs for unpowered ESD test A general drawing of the test circuit diagram for testing direct ESD of LIN transceiver ICs in unpowered mode shown for a standard LIN transceiver IC is given in Figure A.3 For ICs with embedded LIN transceivers, the same principle is used R1 ESD3 ESD1 C2 ESD2 R2 to R4 C1 A1 TX GND LIN Wake EN Vsup RX INH Standard LIN Transceiver GND IEC Key Components A1 IC under test (DUT) C1 capacitor C = 100 nF C2 capacitor C = 220 pF (placement dependent on test case) R1 resistor R = 33 kΩ R2, R3, R4 resistor R ≥ 200 kΩ (placement is optional) Figure A.3 – General drawing of the circuit diagram for direct ESD tests of LIN transceiver ICs in unpowered mode The test circuit for LIN transceiver IC ESD test consists of a single LIN transceiver IC (A1) with mandatory external components (C1, R1), LIN bus filter (C2), coupling ports with discharge points (DP1, DP2, DP3) and optional discharge resistors (R2, R3, R4 with R ≥ 200 kΩ) The value for the series resistor on the pin Wake (R1) should be chosen according to the IC specification with minimum value (default R = 33 kΩ) The default parameters of the passive components are for capacitors a tolerance of ±10 %, material X7R according to electronic industry association (EIA) or similar, voltage rating ≥ 50 V and dimension 1206 or 0805 The default parameters for resistors are ±1 % tolerance and dimension 1206 or 0805 BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 – 33 – Annex B (normative) Test circuit boards B.1 Test circuit board for functional tests For functional tests of LIN transceiver ICs the test network shall be designed on a printed circuit board To ensure good RF characteristics of the coupling and decoupling networks, an equal design of the circuitry for node and node on a minimum two layer PCB with a GND layer should be used The length of the coupling paths on the test board should be kept as short as possible The trace length for IC interconnections (LIN) is recommended to be shorter than 30 mm from the star point of the interconnection to the IC pins and the RF injection point when applicable The DUT shall be soldered on the test board to minimize parasitic effects A layout example is shown in Figure B.1 For proper shielding, all connections to the test peripheral of the test board should be connected via coaxial printed circuit board sockets except for the filtered power supplies and GND IEC Figure B.1 – Example of IC interconnections of LIN signal B.2 ESD test For ESD tests, a printed circuit board shall be used At least a two-layer construction of the PCB with GND layer shall be chosen The pads for the discharge points DP to shall be carried out in a way that a proper contact to the discharge tip of the test generator is ensured (e.g by rounded vias in the layout of the ESD test board) The discharge point shall be directly connected by a trace to the respective pin under test of the transceiver IC The passive components of the network shall be placed close to the transceiver IC to reduce parasitic effects The DUT should be soldered on the test board to ensure application like conditions and avoid parasitic setup effects by sockets The insulation distance between the signal lines and pads of the passive components and the extensive ground area should be designed in a way that a spark over at these points can be prevented up to the intended test voltage level A layout example is shown in Figure B.2 – 34 – BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 IEC Figure B.2 – Example of ESD test board for LIN transceiver ICs Further requirements to the ESD test board are defined in Table B.1 Table B.1 – Parameter ESD test circuit board Parameter Value Trace length between transceiver pads and discharge point mm 15 +5 Trace width of the conducting path 0,254 mm If a test adapter is used for functional and leakage current failure validation the test board should enable direct contacting of the transceiver pins (e.g by additional test pads) BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 – 35 – Annex C (informative) Examples for test limits for LIN transceiver in automotive application C.1 General The purpose of this Annex C is to show examples of limits for LIN transceiver ICs used in automotive applications For specific limit selection refer to the applicable test method documents C.2 Emission of RF disturbances Figure C.1 shows an example of limits for RF emission measurements at the pins LIN, V BAT and Wake for the 150 Ω direct coupling method according to IEC 61967-4 Limit class lll Limit class ll Limit class l (dBµV) LIN without bus filter 90 80 70 60 50 40 30 20 10 0,1 10 100 000 (MHz) IEC Limit class lll Limit class ll Limit class l (dBµV) LIN with bus filter 90 80 70 60 50 40 30 20 10 0,1 10 100 000 (MHz) IEC BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 – 36 – VBAT Limit class lll Limit class ll Limit class l (dBµV) Wake 90 80 70 60 50 40 30 20 10 0,1 10 100 000 (MHz) IEC Figure C.1 – Example of limits for RF emission C.3 Immunity to RF disturbances Figure C.2 and Figure C.3 give an example of limits for RF immunity tests at the pins LIN, V BAT and Wake for the DPI test method according to IEC 62132-4 There are different target levels for functional tests related to functional status class A IC and functional status class C IC or D IC Limit class lll (A_IC) Limit class ll (A_IC) Limit class l (A_IC) (dBm) LIN without bus filter 40 35 30 25 20 15 10 10 100 000 (MHz) IEC (dBm) LIN with bus filter VBAT 40 Limit class lll (A_IC) Limit class ll (A_IC) Limit class l (A_IC) Wake 35 30 25 20 15 10 10 100 000 (MHz) IEC Figure C.2 – Example of limits for RF immunity for functional status class AIC BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 – 37 – (dBm) LIN with bus filter VBAT 40 Limit class lll (C_IC / D_IC) Limit class ll (C_IC / D_IC) Limit class l (C_IC / D_IC) Wake 35 30 25 20 15 10 10 000 100 (MHz) IEC Figure C.3 – Example of limits for RF immunity for functional status class C IC or D IC C.4 Immunity to impulses Table C.1 gives an example of limits for impulse immunity tests defined for functional status class C IC or D IC evaluation at the pins LIN, V BAT and Wake using the non-synchronous transient injection method according to IEC 62215-3 Table C.1 – Example of limits for impulse immunity for functional status class C IC or D IC C.5 Test pulse Vsmax V −100 2a +75 3a −150 3b +100 Electrostatic Discharge (ESD) For test of ESD immunity to damage of the pins LIN, V BAT and Wake the limit value V ESD = ±6 kV is recommended BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 – 38 – Annex D (informative) Test of indirect ESD discharge D.1 General Annex D describes an additional test to evaluate the immunity of LIN transceiver ICs against indirect ESD discharges The intention of this test is to apply an ESD discharge current wave form to the DUT comparable to ECU testing of LIN networks according to ISO 10605 indirect ESD test D.2 Test setup The indirect ESD immunity tests of LIN transceiver ICs shall be carried out using a test setup according to Figure D.1 It extends the test setup for direct ESD test with a specific coupling cable and L-C network The ESD discharge point, DP1, of the basic test board for direct ESD according to 6.4.2 is connected to the inner conductor of the specific coupling cable Discharge on shield of cable DUT TC I Discharge 1,6 m IEC Key LIN transceiver IC (DUT) ESD test setup of direct discharge test Capacitor on slave node (C Slave = 220 pF) Ground plane Coupling cable (l = 1,6 m, coax cable type RG402 or similar) Insulting support (h = 20 mm) Master node simulation network; L = 2,2 µH; C = 2,2 nF (1 kV) Discharge point at shield at far end of coupling cable Figure D.1 – Test setup for indirect ESD tests The ESD discharge is applied to the shield at the far end of the coupling cable The shape of the coupling cable arrangement placed on the insulation support is not important (it can be placed e.g as meander or straight leads) The shield of the coupling cable is connected to test board GND but is floating at the ESD discharge point (far end of the coupling cable) The BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 – 39 – inner conductor of the coupling cable is connected to the LIN pin of the DUT on one side and at the far end to the ground plane via a L-C network This network represents the Master bus capacitance and the inductance of a typical connection cable at the ECU application test The combination of coupling cable and L-C network has an influence on the current shape of indirect discharge applied to the DUT D.3 Typical current wave form for indirect ESD test (A) An example of an indirect ESD current wave form is given in Figure D.2 For the current measurement in this configuration the LIN transceiver is replaced by a 10 Ω resistor (5 × R = 51 Ω in parallel) connected between LIN and GND pad on the test board The current trough this load resistor is measured using a current probe with appropriate bandwidth and current capability 16 14 12 10 –2 –4 –6 50 100 150 200 (ns) IEC Figure D.2 – Example of ESD current wave form for indirect ESD test at V ESD = -8 kV D.4 Test procedure and parameters To determine transceiver immunity against damages caused by indirect ESD tests similar to ISO 10605 should be done for the LIN pin with the procedure and parameters defined in Table D.1 – 40 – BS EN 62228-2:2017 IEC 62228-2:2016 © IEC 2016 Table D.1 – Specifications for indirect ESD tests Item Parameter Type of discharge Contact Discharge circuit R = 330 Ω, C = 150 pF Discharge voltage levels start level kV stop level V ESD_damage or 15 kV Discharge voltage steps kV step up to V ESD = 15 kV, Test procedure 1) reference measurement of LIN signal in normal mode (DUT transmitting) and I-V characteristic of all pins to be tested (pin to GND) 2) 10 ESD pulses with positive polarity on discharge point coupling cable with s delay in between, after each single ESD pulse the pin or discharge point has to be discharged to the ground to ensure zero potential before the next ESD pulse 3) failure validation Failure validation 4) proceed with point 2) to 3) with negative polarity 5) proceed with point 2) to 4) with the next higher ESD test voltage up to damage of the tested pin or maximum test voltage a) evaluation of I-V characteristic according to section 5.5.3 b) additional functional test at each test voltage level: Evaluation of LIN signal The maximum allowed deviation to the reference signal shall be smaller than % For the evaluation of damages a specific test extension frame or IC adapter may be used for contacting the pins of the transceiver _ This page deliberately left blank NO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAW British Standards Institution (BSI) BSI is the national body responsible for preparing British Standards and other standards-related publications, information and services BSI is incorporated by Royal Charter British Standards and other standardization products are published by BSI Standards Limited About us Reproducing extracts We bring together business, industry, government, consumers, innovators and others to shape their combined experience and expertise into standards -based solutions For permission to reproduce content from BSI publications contact the BSI Copyright & Licensing team The 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