BS EN 16602-60-02:2014 BSI Standards Publication Space product assurance — ASIC and FPGA development BS EN 16602-60-02:2014 BRITISH STANDARD National foreword This British Standard is the UK implementation of EN 16602-60-02:2014 The UK participation in its preparation was entrusted to Technical Committee ACE/68, Space systems and operations A list of organizations represented on this committee can be obtained on request to its secretary This publication does not purport to include all the necessary provisions of a contract Users are responsible for its correct application © The British Standards Institution 2014 Published by BSI Standards Limited 2014 ISBN 978 580 84273 ICS 49.140 Compliance with a British Standard cannot confer immunity from legal obligations This British Standard was published under the authority of the Standards Policy and Strategy Committee on 30 September 2014 Amendments/corrigenda issued since publication Date Text affected EN 16602-60-02 EUROPEAN STANDARD NORME EUROPÉENNE EUROPÄISCHE NORM September 2014 ICS 49.140 English version Space product assurance - ASIC and FPGA development Assurance produit des projets spatiaux - développement des ASIC et FPGA Raumfahrtproduktsicherung - Entwicklung von ASIG und FPGA This European Standard was approved by CEN on 13 March 2014 CEN and CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC Management Centre or to any CEN and CENELEC member This European Standard exists in three official versions (English, French, German) A version in any other language made by translation under the responsibility of a CEN and CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the same status as the official versions CEN and CENELEC members are the national standards bodies and national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and United Kingdom CEN-CENELEC Management Centre: Avenue Marnix 17, B-1000 Brussels © 2014 CEN/CENELEC All rights of exploitation in any form and by any means reserved worldwide for CEN national Members and for CENELEC Members Ref No EN 16602-60-02:2014 E BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) Table of contents Foreword Introduction Scope Normative references Terms, definitions and abbreviated terms 3.1 Terms from other standards 3.2 Terms specific to the present standard .9 3.3 Abbreviated terms 12 ASIC and FPGA programme management 14 4.1 General 14 4.1.1 Introduction .14 4.1.2 Organization 14 4.1.3 Planning 14 4.2 ASIC and FPGA control plan 14 4.3 Management planning tools 15 4.4 4.3.1 ASIC and FPGA development plan 15 4.3.2 Verification plan 15 4.3.3 Design validation plan 15 Experience summary report 15 ASIC and FPGA engineering 16 5.1 Introduction .16 5.2 General requirements .16 5.3 Definition phase 19 5.4 5.3.1 Introduction .19 5.3.2 General requirements 19 5.3.3 Feasibility and risk assessment 19 5.3.4 ASIC and FPGA development plan 20 5.3.5 System requirements review 20 Architectural design 22 5.4.1 General requirements .22 5.4.2 Architecture definition 22 BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) 5.5 5.6 5.7 5.8 5.4.3 Verification plan 23 5.4.4 Architecture verification and optimization 23 5.4.5 Preliminary data sheet 24 5.4.6 Preliminary design review 24 Detailed design .24 5.5.1 Introduction .24 5.5.2 General requirements .25 5.5.3 Design entry 25 5.5.4 Netlist generation 26 5.5.5 Netlist verification 27 5.5.6 Updated data sheet 28 5.5.7 Detailed design review 28 Layout 29 5.6.1 General requirements 29 5.6.2 Layout generation .29 5.6.3 Layout verification .30 5.6.4 Design validation plan .31 5.6.5 Updated data sheet 31 5.6.6 Draft detail specification 31 5.6.7 Critical design review 31 Prototype implementation .32 5.7.1 Introduction .32 5.7.2 Production and test 32 Design validation and release 33 5.8.1 Design validation .33 5.8.2 Radiation test performance 33 5.8.3 Design release and FM production preparation 34 5.8.4 Experience summary report 34 5.8.5 Final versions of application and procurement documents 34 5.8.6 Qualification and acceptance review 35 Quality assurance system 36 6.1 General 36 6.2 Review meetings 36 6.3 Risk assessment and risk management 38 Development documentation 39 7.1 General 39 7.2 Management documentation 39 BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) 7.3 7.4 Design documentation 40 7.3.1 General .40 7.3.2 Definition phase documentation 42 7.3.3 Architectural design documentation 42 7.3.4 Detailed design documentation 42 7.3.5 Layout documentation .43 7.3.6 Design validation documentation 43 Application and procurement documents 43 7.4.1 Data sheet 43 7.4.2 Application note 43 7.4.3 Detail specification 44 Deliverables 45 8.1 General 45 8.2 Deliverable items 45 Annex A (normative) ASIC and FPGA control plan (ACP) – DRD 46 Annex B (normative) ASIC and FPGA development plan (ADP) – DRD 48 Annex C (normative) ASIC and FPGA requirements specification (ARS) – DRD 50 Annex D (normative) Feasibility and risk assessment report (FRA) - DRD 52 Annex E (normative) Verification plan (VP) – DRD 53 Annex F (normative) Design validation plan (DVP) – DRD 54 Annex G (normative) Data sheet – DRD 55 Annex H (normative) Detail specification (DS) – DRD 57 Annex I (normative) Experience summary report – DRD 59 Annex J (informative) Document requirements list and configuration items to be delivered 60 Bibliography 61 Figures Figure 5-1: Development flow (example) 17 Figure 7-1: Design documentation .41 Tables Table J-1 : Deliverables of the ASIC and FPGA development 60 BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) Foreword This document (EN 16602-60-02:2014) has been prepared by Technical Committee CEN/CLC/TC “Space”, the secretariat of which is held by DIN This standard (EN 16602-60-02:2014) originates from ECSS-Q-ST-60-02C This European Standard shall be given the status of a national standard, either by publication of an identical text or by endorsement, at the latest by March 2015, and conflicting national standards shall be withdrawn at the latest by March 2015 Attention is drawn to the possibility that some of the elements of this document may be the subject of patent rights CEN [and/or CENELEC] shall not be held responsible for identifying any or all such patent rights This document has been prepared under a mandate given to CEN by the European Commission and the European Free Trade Association This document has been developed to cover specifically space systems and has therefore precedence over any EN covering the same scope but with a wider domain of applicability (e.g : aerospace) According to the CEN-CENELEC Internal Regulations, the national standards organizations of the following countries are bound to implement this European Standard: Austria, Belgium, Bulgaria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and the United Kingdom BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) Introduction The added responsibilities of developing custom designed devices, as opposed to using off-the-shelf components, make certain management activities crucial to the success of the procurement programme This was already considered by the applicable standard for “Space product assurance - EEE components”, ECSS-Q-ST-60 that classifies custom designed devices, such as ASIC components, under “Specific components”, for which particular requirements are applicable The supplier accepts requirements for the development of custom designed components within the boundaries of this standard based on the requirements of the system and its elements, and takes into consideration the operational and environmental requirements of the programme The supplier implements those requirements into a system which enables to control for instance the technology selection, design, synthesis and simulation, layout and design validation in a schedule compatible with his requirements, and in a cost-efficient way BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) Scope This Standard defines a comprehensive set of requirements for the user development of digital, analog and mixed analog-digital custom designed integrated circuits, such as application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs) The user development includes all activities beginning with setting initial requirements and ending with the validation and release of prototype devices This Standard is aimed at ensuring that the custom designed components used in space projects meet their requirements in terms of functionality, quality, reliability, schedule and cost The support of appropriate planning and risk management is essential to ensure that each stage of the development activity is consolidated before starting the subsequent one and to minimize or avoid additional iterations For the development of standard devices, such as application specific standard products (ASSPs) and IP cores, and devices which implement safety related applications, additional requirements can be included which are not in the scope of this document The principal clauses of this Standard correspond to the main concurrent activities of a circuit development programme These include: • ASIC and FPGA programme management, • ASIC and FPGA engineering, • ASIC and FPGA quality assurance The provisions of this document apply to all actors involved in all levels in the realization of space segment hardware and its interfaces This standard may be tailored for the specific characteristics and constraints of a space project, in accordance with ECSS-S-ST-00 BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) Normative references The following normative documents contain provisions which, through reference in this text, constitute provisions of this ECSS Standard For dated references, subsequent amendments to, or revisions of any of these publications not apply However, parties to agreements based on this ECSS Standard are encouraged to investigate the possibility of applying the most recent editions of the normative documents indicated below For undated references the latest edition of the publication referred to applies EN reference Reference in text Title EN 16601-00-01 ECSS-S-ST-00-01 ECSS system – Glossary of terms EN 16602-10 ECSS-Q-ST-10 Space product assurance – Product assurance management EN 16602-20 ECSS-Q-ST-20 Space product assurance – Quality assurance EN 16602-30 ECSS-Q-ST-30 Space product assurance – Dependability EN 16602-60 ECSS-Q-ST-60 Space product assurance – Electrical, electronic and electromechanical (EEE) components EN 16603-10 ECSS-E-ST-10 Space engineering – System engineering general requirements EN 16601-10 ECSS-M-ST-10 Space project management – Project planning and implementation EN 16601-10-01 ECSS-M-ST-10-01 Space project management – Organization and conduct of reviews EN 16601-40 ECSS-M-ST-40 Space project management – Configuration and information management BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) Annex C (normative) ASIC and FPGA requirements specification (ARS) – DRD C.1 DRD identification C.1.1 Requirement identification and source document This DRD is called by the ECSS-Q-ST-60-02, requirements 5.3.2b and 7.3.2a.2 C.1.2 Purpose and objective The purpose of the ASIC and FPGA requirement specifications (ARS) is to specify a complete set of traceable ASIC and FPGA requirements C.2 Expected response C.2.1 a Scope and content The ARS shall include the following items: Overall system partitioning, system configurations and operating modes; Interfaces of the ASIC and FPGA to the system and communication protocols to external devices, including memory mapping; Operating frequency range; Electrical constraints (e.g voltage and current supply, drive capabilities and external load); Functional requirements; Applicable algorithms; Power-up and initialization state; Reset and power cycling requirements; Error handling; BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) 10 Test modes: system and device tests, on ground and in flight; 11 Fault coverage required at production test; NOTE 12 Timing of critical signals; 13 Radiation environment constraints; 14 Thermal environment constraints; 15 Power budget and dissipation; 16 Physical and mechanical constraints: pin assignment, size, encapsulation; 17 Reusability or additional functions for future applications; 18 Portability to different or newer technologies; 19 Intellectual property rights of the design to be developed; 20 Proprietary designs (IP cores) to be used as building blocks of the design to be developed, if already identified C.2.2 None This is only applicable for digital ASIC designs Special remarks BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) Annex D (normative) Feasibility and risk assessment report (FRA) - DRD D.1 DRD identification D.1.1 Requirement identification and source document This DRD is called by the ECSS-Q-ST-60-02, requirement 5.3.3.2b D.1.2 Purpose and objective The purpose of the FRA is to provide a judgement on the feasibility of the ASIC and FPGA development as defined by the ASIC and FPGA requirements specification, as well as an assessment of the risks involved D.2 Expected response D.2.1 a The FRA shall include the following items: Assurance that the collected ASIC and FPGA requirements are complete, settled and unambiguous; Maturity of envisaged ASIC or FPGA manufacturers and possible technologies; Experience and familiarity of engineering resources with the design type, tools, technology and the potential foundries; Risk of underestimation of design and verification effort; Risk of underestimation of debug and repair efforts; Risk of overestimation of actual gate capacity and clocking frequency; Risk of undetermined I/O behaviour during power-up D.2.2 None Scope and content Special remarks BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) Annex E (normative) Verification plan (VP) – DRD E.1 DRD identification E.1.1 Requirement identification and source document This DRD is called by ECSS-Q-ST-60-02, requirements 4.3.2a and 5.4.3a E.1.2 Purpose and objective The purpose of the verification plan is to define how the functionality and nonfunctional requirements stated in the definition phase documentation are demonstrated at all levels of modelling, starting from the behavioural level down to the gate level E.2 Expected response E.2.1 a The VP shall include a description of the following items: In the case of complex digital ASIC developments, verification by FPGA prototyping or emulation; Requirements for code coverage in digital designs; Requirements for hardware-software interaction, possibly by performing co-simulation; Application of coding rules E.2.2 None Scope and content Special remarks BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) Annex F (normative) Design validation plan (DVP) – DRD F.1 DRD identification F.1.1 Requirement identification and source document This DRD is called by the ECSS-Q-ST-60-02, requirements 4.3.3a and 5.6.4a F.1.2 Purpose and objective The purpose of the design validation plan is to specify the measurements that are performed on the prototypes in order to verify that the new implemented devices contain the functionality and the characteristic they are designed for F.2 Expected response F.2.1 a The DVP shall include the following items: description and requirements for the test set-up or system breadboard; operating modes and test conditions of the prototypes under test; characteristics and functions to be validated and checked against the ASIC and FPGA requirements specification; if a radiation test is required by the customer, the corresponding radiation verification test plan F.2.2 None Scope and content Special remarks BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) Annex G (normative) Data sheet – DRD G.1 DRD identification G.1.1 Requirement identification and source document This DRD is called by ECSS-Q-ST-60-02, requirements 5.4.5a and 7.4.1a G.1.2 Purpose and objective The purpose of the data sheet is to gather all technical data obtained from the architectural design until the final design validation and release It is used as an input for application and procurement G.2 Expected response G.2.1 a Scope and content Each page shall contain the device name and number and the date of issue NOTE The first page contain a summary of the device functionality, a block diagram and short list of features, such as operating frequency, technology and the foundry address b All characteristics and limitations introduced during the design shall be described, such as detailed interface descriptions, register definitions and memory maps c The data sheet shall include a system overview of the device and a description of how to use the device in a representative system environment, including an application block diagram d The full functionality and all operating modes shall be specified in detail e All signal interfaces shall be described in detail including for instance a description of all signals, test and power pins, specifying e.g the usage of the signals and the signal polarity f The signal descriptions shall be grouped according to their function BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) g All electrical and mechanical data shall be specified, together with their relevant applicable conditions (e.g temperature and capacitive load), including: Absolute maximum ratings, including storage temperature, operating temperature, supply voltage, maximum input current for any pin, total dose, single event upset, latch-up, electrostatic discharge and reliability figures; DC parameters, including voltage levels, leakage currents, pin capacitances and output currents; Static and dynamic (per MHz) power dissipation, allowing the power consumption at lower operating frequencies to be calculated, if representative; AC parameters, including e.g set-up and hold times, cycle periods, output delays and tri-state delays, together with waveform diagrams; Evidences that timing parameters relate to the relevant reference signal edges; Package description, including pin assignment, package figure with pin numbers and preferably signal names, and a mechanical drawing for the package dimensions including information on the thermal characteristic of the package such as wall thickness, thermal coefficient of material or package h A preliminary data sheet shall contain all parts of a final data sheet, with the same level of detail i When data does not exist, estimates shall be used and clearly indicated to be estimates G.2.2 None Special remarks BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) Annex H (normative) Detail specification (DS) – DRD H.1 DRD identification H.1.1 Requirement identification and source document This DRD is called by ECSS-Q-ST-60-02, requirements 5.6.6a and 7.4.3c H.1.2 Purpose and objective The purpose of the detail specification is to collect all the engineering information from the layout activity (at the end of which a draft detail specification is established) to the design validation and release activity (at the end of which the final detail specification is produced) It is used as an input for application and procurement H.2 Expected response H.2.1 a Scope and content The final detail specification shall include the following items: relevant electrical and mechanical parameters; screening, burn-in, and acceptance requirements; deviations from the generic specification; documentation and data requirements; delta limits, when applicable; criteria for percent defective allowable; lot acceptance tests or quality conformance inspections; marking; storage requirements; 10 requirements for lot homogeneity; 11 serialization, when applicable; BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) 12 protective packaging and handling requirements; 13 radiation verification testing requirements, when applicable H.2.2 None Special remarks BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) Annex I (normative) Experience summary report – DRD I.1 DRD identification I.1.1 Requirement identification and source document This DRD is called by ECSS-Q-ST-60-02, requirement 4.4a and 5.8.4a I.1.2 Purpose and objective The purpose of the experience summary report is to collect and to evaluate any relevant information resulting from the experience gained during the execution of the ASIC and FPGA procurement programme I.2 Expected response I.2.1 a I.2.2 None Scope and content The experience summary report shall include the following items: A summary of the main design objectives and constraints; An assessment of the actual development programme with respect to the original ADP; Controls, schedule, design iterations and communications; An assessment of EDA tool suitability and performance; An assessment of the manufacturer support; A presentation of non-conformances and problem areas; In the case of usage of existing IP cores, experiences gained in terms of product quality and suitability; synthesis results, modelling, test stimuli, application support and problems encountered; Recommendations and lessons learned Special remarks documentation, BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) Annex J (informative) Document requirements list and configuration items to be delivered Table J-1: Deliverables of the ASIC and FPGA development Development phase Definition phase Architectural design Documentation DRD A/F control plan (ACP) Annex A A/F requirements specification (ARS) Annex C Feasibility and risk analysis (FRA) Annex D A/F development plan (ADP) Annex B MoM of SRR - Architecture definition report - Verification plan Annex E Architecture verification and optimization report - Preliminary data sheet MoM of PDR Detailed design Design entry report Hardware Design database containing: Simulation models Verification results Annex G - Updated design database containing: Netlist generation report - Netlist verification report - Pre-layout netlist Updated data sheet Annex G Constraints for layout Layout generation report - Layout verification report - Updated design database containing: Design validation plan (DVP) Annex F Post-layout netlist Updated data sheet Annex G Draft detail specification Annex H Corresponding parasitic information MoM of CDR - MoM of DDR Layout Software Prototype Production test results and reports implementation Burn-in or any other production test results, specification, pattern - Design validation and release Validation report - Radiation test report - Release report - Final data sheet Annex G Final detail specification Annex H Application note - Experience summary report Annex I MoM of QR/AR - - Test vectors for production Agreed number of tested devices (ASICs or FPGAs) Validation breadboard Burn-in or screening test boards for FM parts BS EN 16602-60-02:2014 EN 16602-60-02:2014 (E) Bibliography EN reference Reference in text Title EN 16601-00 ECSS-S-ST-00 ECSS system – Description, implementation and general requirements IEEE 61691-1-1 Behavioural languages Part 1-1: VHDL language reference manual IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture EN 16602-60-02:2014 (E) This page deliberately left blank This page deliberately left blank NO COPYING WITHOUT BSI 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